Group : dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg
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Group Instance : mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 82 1 T185 2 T186 2 T187 2
others[1] 78 1 T185 1 T187 3 T336 2
others[2] 84 1 T185 4 T186 3 T187 2
others[3] 121 1 T186 2 T187 2 T336 3
false 28713 1 T1 1 T2 2 T3 9
true 23601 1 T1 1 T2 1 T4 358


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 7 1 T63 1 T88 1 T337 1
others[1] 3 1 T132 1 T338 1 T339 1
others[2] 6 1 T15 1 T183 1 T340 1
others[3] 6 1 T89 1 T341 1 T342 1
false 12513 1 T1 1 T2 2 T3 9
true 3 1 T42 1 T343 1 T344 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2479 1 T4 45 T45 72 T29 2
others[1] 2468 1 T4 42 T45 83 T90 65
others[2] 2565 1 T4 31 T45 83 T90 85
others[3] 4227 1 T4 70 T45 146 T30 2
false 7324 1 T1 1 T2 2 T3 9
true 1503 1 T1 1 T2 1 T17 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2492 1 T4 37 T45 74 T90 76
others[1] 2532 1 T4 48 T45 93 T29 2
others[2] 2559 1 T4 32 T45 77 T90 116
others[3] 4148 1 T4 66 T45 129 T30 2
false 7303 1 T1 1 T2 2 T3 9
true 1496 1 T1 1 T2 1 T17 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 2466 1 T4 30 T45 82 T90 87
others[1] 2403 1 T4 22 T45 69 T29 2
others[2] 2508 1 T4 51 T45 75 T30 2
others[3] 4169 1 T4 91 T45 160 T30 2
false 7770 1 T1 1 T2 2 T3 9
true 31 1 T127 1 T99 1 T345 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 71 1 T185 2 T186 2 T187 2
others[1] 85 1 T185 1 T186 1 T187 1
others[2] 83 1 T186 3 T187 2 T336 1
others[3] 155 1 T185 2 T186 2 T187 3
false 28687 1 T1 1 T3 9 T4 385
true 23701 1 T1 1 T2 3 T4 349


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 8234 1 T4 133 T45 271 T29 1
others[1] 8202 1 T4 140 T45 283 T29 2
others[2] 8068 1 T4 137 T45 263 T29 3
others[3] 13504 1 T4 200 T45 487 T29 10
false 4092 1 T4 51 T45 149 T29 3
true 19893 1 T1 1 T2 2 T3 9

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