Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T20,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1608631912	1605262228	0	0
CheckNGreaterZero_A	4184	4184	0	0
GntImpliesReady_A	1608631912	406217797	0	0
GntImpliesValid_A	1608631912	406217797	0	0
GrantKnown_A	1608631912	1605262228	0	0
IdxKnown_A	1608631912	1605262228	0	0
IndexIsCorrect_A	1608631912	406217797	0	0
NoReadyValidNoGrant_A	1608631912	173865571	0	0
Priority_A	1608631912	430545000	0	0
ReadyAndValidImplyGrant_A	1608631912	406217797	0	0
ReqAndReadyImplyGrant_A	1608631912	406217797	0	0
ReqImpliesValid_A	1608631912	430545000	0	0
ValidKnown_A	1608631912	1605262228	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	1605262228	0	0
T1	454564	454536	0	0
T2	2342224	2341520	0	0
T3	15872	13288	0	0
T4	785880	749752	0	0
T10	14036	10920	0	0
T11	15056	12404	0	0
T17	11436	11132	0	0
T18	22144	21900	0	0
T19	3850784	3850268	0	0
T20	6860	6396	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4184	4184	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	406217797	0	0
T1	454564	1198916	0	0
T2	2342224	35808	0	0
T3	15872	372	0	0
T4	785880	165858	0	0
T5	0	58158	0	0
T6	0	41178	0	0
T10	14036	292	0	0
T11	15056	350	0	0
T15	0	520	0	0
T17	11436	804	0	0
T18	22144	64	0	0
T19	3850784	1410	0	0
T20	6860	388	0	0
T21	0	318	0	0
T23	0	8	0	0
T53	0	520	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	406217797	0	0
T1	454564	1198916	0	0
T2	2342224	35808	0	0
T3	15872	372	0	0
T4	785880	165858	0	0
T5	0	58158	0	0
T6	0	41178	0	0
T10	14036	292	0	0
T11	15056	350	0	0
T15	0	520	0	0
T17	11436	804	0	0
T18	22144	64	0	0
T19	3850784	1410	0	0
T20	6860	388	0	0
T21	0	318	0	0
T23	0	8	0	0
T53	0	520	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	1605262228	0	0
T1	454564	454536	0	0
T2	2342224	2341520	0	0
T3	15872	13288	0	0
T4	785880	749752	0	0
T10	14036	10920	0	0
T11	15056	12404	0	0
T17	11436	11132	0	0
T18	22144	21900	0	0
T19	3850784	3850268	0	0
T20	6860	6396	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	1605262228	0	0
T1	454564	454536	0	0
T2	2342224	2341520	0	0
T3	15872	13288	0	0
T4	785880	749752	0	0
T10	14036	10920	0	0
T11	15056	12404	0	0
T17	11436	11132	0	0
T18	22144	21900	0	0
T19	3850784	3850268	0	0
T20	6860	6396	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	406217797	0	0
T1	454564	1198916	0	0
T2	2342224	35808	0	0
T3	15872	372	0	0
T4	785880	165858	0	0
T5	0	58158	0	0
T6	0	41178	0	0
T10	14036	292	0	0
T11	15056	350	0	0
T15	0	520	0	0
T17	11436	804	0	0
T18	22144	64	0	0
T19	3850784	1410	0	0
T20	6860	388	0	0
T21	0	318	0	0
T23	0	8	0	0
T53	0	520	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	173865571	0	0
T1	454564	11600	0	0
T2	2342224	1221190	0	0
T3	15872	1336	0	0
T4	785880	44944	0	0
T5	0	4226	0	0
T6	0	112468	0	0
T10	14036	1116	0	0
T11	15056	1348	0	0
T17	11436	272	0	0
T18	22144	256	0	0
T19	3850784	384	0	0
T20	6860	832	0	0
T23	0	32	0	0
T25	0	358	0	0
T33	0	806400	0	0
T47	0	1622	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	430545000	0	0
T1	454564	1198916	0	0
T2	2342224	580540	0	0
T3	15872	372	0	0
T4	785880	165858	0	0
T5	0	58178	0	0
T6	0	43102	0	0
T10	14036	292	0	0
T11	15056	350	0	0
T15	0	520	0	0
T17	11436	804	0	0
T18	22144	64	0	0
T19	3850784	1410	0	0
T20	6860	388	0	0
T21	0	318	0	0
T23	0	8	0	0
T53	0	520	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	406217797	0	0
T1	454564	1198916	0	0
T2	2342224	35808	0	0
T3	15872	372	0	0
T4	785880	165858	0	0
T5	0	58158	0	0
T6	0	41178	0	0
T10	14036	292	0	0
T11	15056	350	0	0
T15	0	520	0	0
T17	11436	804	0	0
T18	22144	64	0	0
T19	3850784	1410	0	0
T20	6860	388	0	0
T21	0	318	0	0
T23	0	8	0	0
T53	0	520	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	406217797	0	0
T1	454564	1198916	0	0
T2	2342224	35808	0	0
T3	15872	372	0	0
T4	785880	165858	0	0
T5	0	58158	0	0
T6	0	41178	0	0
T10	14036	292	0	0
T11	15056	350	0	0
T15	0	520	0	0
T17	11436	804	0	0
T18	22144	64	0	0
T19	3850784	1410	0	0
T20	6860	388	0	0
T21	0	318	0	0
T23	0	8	0	0
T53	0	520	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	430545000	0	0
T1	454564	1198916	0	0
T2	2342224	580540	0	0
T3	15872	372	0	0
T4	785880	165858	0	0
T5	0	58178	0	0
T6	0	43102	0	0
T10	14036	292	0	0
T11	15056	350	0	0
T15	0	520	0	0
T17	11436	804	0	0
T18	22144	64	0	0
T19	3850784	1410	0	0
T20	6860	388	0	0
T21	0	318	0	0
T23	0	8	0	0
T53	0	520	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608631912	1605262228	0	0
T1	454564	454536	0	0
T2	2342224	2341520	0	0
T3	15872	13288	0	0
T4	785880	749752	0	0
T10	14036	10920	0	0
T11	15056	12404	0	0
T17	11436	11132	0	0
T18	22144	21900	0	0
T19	3850784	3850268	0	0
T20	6860	6396	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T20,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402157978	401315557	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	402157978	108924437	0	0
GntImpliesValid_A	402157978	108924437	0	0
GrantKnown_A	402157978	401315557	0	0
IdxKnown_A	402157978	401315557	0	0
IndexIsCorrect_A	402157978	108924437	0	0
NoReadyValidNoGrant_A	402157978	45393615	0	0
Priority_A	402157978	115032378	0	0
ReadyAndValidImplyGrant_A	402157978	108924437	0	0
ReqAndReadyImplyGrant_A	402157978	108924437	0	0
ReqImpliesValid_A	402157978	115032378	0	0
ValidKnown_A	402157978	401315557	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	108924437	0	0
T1	113641	48625	0	0
T2	585556	9790	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	108924437	0	0
T1	113641	48625	0	0
T2	585556	9790	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	108924437	0	0
T1	113641	48625	0	0
T2	585556	9790	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	45393615	0	0
T1	113641	2611	0	0
T2	585556	325934	0	0
T3	3968	668	0	0
T4	196470	22472	0	0
T10	3509	558	0	0
T11	3764	674	0	0
T17	2859	131	0	0
T18	5536	128	0	0
T19	962696	192	0	0
T20	1715	396	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	115032378	0	0
T1	113641	48625	0	0
T2	585556	157054	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	108924437	0	0
T1	113641	48625	0	0
T2	585556	9790	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	108924437	0	0
T1	113641	48625	0	0
T2	585556	9790	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	115032378	0	0
T1	113641	48625	0	0
T2	585556	157054	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T20,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402157978	401315557	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	402157978	108924494	0	0
GntImpliesValid_A	402157978	108924494	0	0
GrantKnown_A	402157978	401315557	0	0
IdxKnown_A	402157978	401315557	0	0
IndexIsCorrect_A	402157978	108924494	0	0
NoReadyValidNoGrant_A	402157978	45393612	0	0
Priority_A	402157978	115032438	0	0
ReadyAndValidImplyGrant_A	402157978	108924494	0	0
ReqAndReadyImplyGrant_A	402157978	108924494	0	0
ReqImpliesValid_A	402157978	115032438	0	0
ValidKnown_A	402157978	401315557	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	108924494	0	0
T1	113641	48625	0	0
T2	585556	9790	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	108924494	0	0
T1	113641	48625	0	0
T2	585556	9790	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	108924494	0	0
T1	113641	48625	0	0
T2	585556	9790	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	45393612	0	0
T1	113641	2611	0	0
T2	585556	325934	0	0
T3	3968	668	0	0
T4	196470	22472	0	0
T10	3509	558	0	0
T11	3764	674	0	0
T17	2859	131	0	0
T18	5536	128	0	0
T19	962696	192	0	0
T20	1715	396	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	115032438	0	0
T1	113641	48625	0	0
T2	585556	157054	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	108924494	0	0
T1	113641	48625	0	0
T2	585556	9790	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	108924494	0	0
T1	113641	48625	0	0
T2	585556	9790	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	115032438	0	0
T1	113641	48625	0	0
T2	585556	157054	0	0
T3	3968	186	0	0
T4	196470	82929	0	0
T10	3509	146	0	0
T11	3764	175	0	0
T17	2859	34	0	0
T18	5536	32	0	0
T19	962696	705	0	0
T20	1715	123	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T17,T20
1	0	Covered	T2,T20,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T5
1	0	Covered	T1,T17,T20
1	1	Covered	T2,T20,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5
1	1	Covered	T1,T17,T20

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5
1	1	Covered	T1,T2,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402157978	401315557	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	402157978	94184478	0	0
GntImpliesValid_A	402157978	94184478	0	0
GrantKnown_A	402157978	401315557	0	0
IdxKnown_A	402157978	401315557	0	0
IndexIsCorrect_A	402157978	94184478	0	0
NoReadyValidNoGrant_A	402157978	41539172	0	0
Priority_A	402157978	100240137	0	0
ReadyAndValidImplyGrant_A	402157978	94184478	0	0
ReqAndReadyImplyGrant_A	402157978	94184478	0	0
ReqImpliesValid_A	402157978	100240137	0	0
ValidKnown_A	402157978	401315557	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	94184478	0	0
T1	113641	550833	0	0
T2	585556	8114	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29079	0	0
T6	0	20589	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	94184478	0	0
T1	113641	550833	0	0
T2	585556	8114	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29079	0	0
T6	0	20589	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	94184478	0	0
T1	113641	550833	0	0
T2	585556	8114	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29079	0	0
T6	0	20589	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	41539172	0	0
T1	113641	3189	0	0
T2	585556	284661	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	2113	0	0
T6	0	56234	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T17	2859	5	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	20	0	0
T23	0	16	0	0
T25	0	179	0	0
T33	0	403200	0	0
T47	0	811	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	100240137	0	0
T1	113641	550833	0	0
T2	585556	133216	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29089	0	0
T6	0	21551	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	94184478	0	0
T1	113641	550833	0	0
T2	585556	8114	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29079	0	0
T6	0	20589	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	94184478	0	0
T1	113641	550833	0	0
T2	585556	8114	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29079	0	0
T6	0	20589	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	100240137	0	0
T1	113641	550833	0	0
T2	585556	133216	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29089	0	0
T6	0	21551	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T17,T20
1	0	Covered	T2,T20,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T5
1	0	Covered	T1,T17,T20
1	1	Covered	T2,T20,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5
1	1	Covered	T1,T17,T20

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T5
1	1	Covered	T1,T2,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402157978	401315557	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	402157978	94184388	0	0
GntImpliesValid_A	402157978	94184388	0	0
GrantKnown_A	402157978	401315557	0	0
IdxKnown_A	402157978	401315557	0	0
IndexIsCorrect_A	402157978	94184388	0	0
NoReadyValidNoGrant_A	402157978	41539172	0	0
Priority_A	402157978	100240047	0	0
ReadyAndValidImplyGrant_A	402157978	94184388	0	0
ReqAndReadyImplyGrant_A	402157978	94184388	0	0
ReqImpliesValid_A	402157978	100240047	0	0
ValidKnown_A	402157978	401315557	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	94184388	0	0
T1	113641	550833	0	0
T2	585556	8114	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29079	0	0
T6	0	20589	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	94184388	0	0
T1	113641	550833	0	0
T2	585556	8114	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29079	0	0
T6	0	20589	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	94184388	0	0
T1	113641	550833	0	0
T2	585556	8114	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29079	0	0
T6	0	20589	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	41539172	0	0
T1	113641	3189	0	0
T2	585556	284661	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	2113	0	0
T6	0	56234	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T17	2859	5	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	20	0	0
T23	0	16	0	0
T25	0	179	0	0
T33	0	403200	0	0
T47	0	811	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	100240047	0	0
T1	113641	550833	0	0
T2	585556	133216	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29089	0	0
T6	0	21551	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	94184388	0	0
T1	113641	550833	0	0
T2	585556	8114	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29079	0	0
T6	0	20589	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	94184388	0	0
T1	113641	550833	0	0
T2	585556	8114	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29079	0	0
T6	0	20589	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	100240047	0	0
T1	113641	550833	0	0
T2	585556	133216	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	29089	0	0
T6	0	21551	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T15	0	260	0	0
T17	2859	368	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	71	0	0
T21	0	159	0	0
T23	0	4	0	0
T53	0	260	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0