Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.69	100.00	98.46		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.74	100.00	98.46	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T155,T7,T184
1	0	Covered	T155,T7,T184

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T17
1	1	Covered	T155,T7,T184

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T85
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T155,T7,T184
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T17,T21

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T17

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T17,T38

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T17,T38

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T17

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T4,T17

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T17,T21

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T17,T21

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T17,T20
1	Covered	T4,T19,T5

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T4,T17

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T4,T17

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T17

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T19,T5
1	1	Covered	T4,T19,T5

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T19,T5
1	1	Covered	T4,T19,T5

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T17
1	1	0	Covered	T1,T4,T17
1	1	1	Covered	T1,T4,T17

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T4,T19,T5
StCalcMask	237	Covered	T4,T19,T5
StCalcPlainEcc	215	Covered	T1,T4,T17
StDisabled	193	Covered	T10,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T4,T17
StPostPack	218	Covered	T1,T17,T21
StPrePack	195	Covered	T1,T17,T38
StReqFlash	237	Covered	T1,T4,T17
StScrambleData	244	Covered	T4,T19,T5
StWaitFlash	270	Covered	T1,T4,T17

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T4,T19,T5
StCalcMask->StScrambleData	244	Covered	T4,T19,T5
StCalcPlainEcc->StCalcMask	237	Covered	T4,T19,T5
StCalcPlainEcc->StReqFlash	237	Covered	T1,T17,T20
StIdle->StDisabled	193	Covered	T10,T11,T12
StIdle->StPackData	197	Covered	T1,T4,T17
StIdle->StPrePack	195	Covered	T1,T17,T38
StPackData->StCalcPlainEcc	215	Covered	T1,T4,T17
StPackData->StPostPack	218	Covered	T1,T17,T21
StPostPack->StCalcPlainEcc	231	Covered	T1,T17,T21
StPrePack->StPackData	205	Covered	T1,T17,T38
StReqFlash->StIdle	273	Covered	T1,T4,T17
StReqFlash->StWaitFlash	270	Covered	T1,T4,T17
StScrambleData->StCalcEcc	252	Covered	T4,T19,T5
StWaitFlash->StIdle	280	Covered	T1,T4,T17

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T17
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T17
0	0	1	Covered	T1,T4,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T38
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T38
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T21
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T17,T21
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T13,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T19,T5
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T17,T20
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T4,T19,T5
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T19,T5
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T19,T5
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T19,T5
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T19,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T4,T17
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T4,T17
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T4,T17
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T4,T17
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T17
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T17
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T4,T17
0	0	1	-	-	Covered	T4,T19,T5
0	0	0	1	-	Covered	T4,T19,T5
0	0	0	0	1	Covered	T1,T4,T17
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	804315956	2446384	0	0
PostPackRule_A	804315956	1923	0	0
PrePackRule_A	804315956	1406	0	0
WidthCheck_A	2092	2092	0	0
u_state_regs_A	804315956	802631114	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804315956	2446384	0	0
T1	227282	299	0	0
T2	1171112	0	0	0
T3	7936	0	0	0
T4	392940	173	0	0
T5	0	318	0	0
T10	7018	0	0	0
T11	7528	0	0	0
T17	5718	1	0	0
T18	11072	0	0	0
T19	1925392	4	0	0
T20	3430	1	0	0
T21	0	2	0	0
T23	0	2	0	0
T29	0	66080	0	0
T30	0	132160	0	0
T33	0	8608	0	0
T38	0	18	0	0
T45	0	388	0	0
T58	0	1	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804315956	1923	0	0
T1	227282	7	0	0
T2	1171112	0	0	0
T3	7936	0	0	0
T4	392940	0	0	0
T10	7018	0	0	0
T11	7528	0	0	0
T17	5718	1	0	0
T18	11072	0	0	0
T19	1925392	0	0	0
T20	3430	0	0	0
T21	0	2	0	0
T38	0	16	0	0
T41	0	1	0	0
T118	0	14	0	0
T130	0	20	0	0
T131	0	14	0	0
T138	0	5	0	0
T144	0	5	0	0
T238	0	3	0	0
T239	0	5	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804315956	1406	0	0
T1	227282	5	0	0
T2	1171112	0	0	0
T3	7936	0	0	0
T4	392940	0	0	0
T10	7018	0	0	0
T11	7528	0	0	0
T17	5718	1	0	0
T18	11072	0	0	0
T19	1925392	0	0	0
T20	3430	0	0	0
T38	0	10	0	0
T41	0	2	0	0
T118	0	10	0	0
T130	0	20	0	0
T131	0	12	0	0
T138	0	2	0	0
T144	0	7	0	0
T238	0	4	0	0
T239	0	6	0	0
T240	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2092	2092	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T10	2	2	0	0
T11	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804315956	802631114	0	0
T1	227282	227268	0	0
T2	1171112	1170760	0	0
T3	7936	6644	0	0
T4	392940	374876	0	0
T10	7018	5460	0	0
T11	7528	6202	0	0
T17	5718	5566	0	0
T18	11072	10950	0	0
T19	1925392	1925134	0	0
T20	3430	3198	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T20

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T20

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T85
1	0	Covered	T7,T85

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T20
1	1	Covered	T7,T85

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T85
1	0	Covered	T1,T2,T17

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T20

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T17,T20
1	Covered	T1,T17,T21

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T20
1	0	Covered	T1,T17,T20
1	1	Covered	T1,T17,T20

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T20

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T20
1	1	Covered	T1,T17,T38

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T17,T38

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T20
1	0	Covered	T1,T17,T20
1	1	Covered	T1,T17,T20

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T17,T20
1	Covered	T1,T17,T20

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T5
1	0	Covered	T1,T17,T20
1	1	Covered	T1,T17,T21

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T17,T21

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T17,T20
1	Covered	T5,T58,T29

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T17,T5
1	Covered	T1,T17,T20

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T17,T5
1	Covered	T1,T17,T5

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T17,T5
1	1	Covered	T1,T17,T20

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T6
1	0	Covered	T5,T58,T29
1	1	Covered	T5,T58,T29

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T6
1	0	Covered	T5,T58,T29
1	1	Covered	T5,T58,T29

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T17,T20
1	1	0	Covered	T1,T17,T20
1	1	1	Covered	T1,T17,T20

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T20

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T5,T58,T26
StCalcMask	237	Covered	T5,T58,T26
StCalcPlainEcc	215	Covered	T1,T17,T20
StDisabled	193	Covered	T10,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T17,T20
StPostPack	218	Covered	T1,T17,T21
StPrePack	195	Covered	T1,T17,T38
StReqFlash	237	Covered	T1,T17,T20
StScrambleData	244	Covered	T5,T58,T26
StWaitFlash	270	Covered	T1,T17,T20

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T5,T58,T26
StCalcMask->StScrambleData	244	Covered	T5,T58,T26
StCalcPlainEcc->StCalcMask	237	Covered	T5,T58,T26
StCalcPlainEcc->StReqFlash	237	Covered	T1,T17,T20
StIdle->StDisabled	193	Covered	T10,T11,T12
StIdle->StPackData	197	Covered	T1,T17,T20
StIdle->StPrePack	195	Covered	T1,T17,T38
StPackData->StCalcPlainEcc	215	Covered	T1,T17,T20
StPackData->StPostPack	218	Covered	T1,T17,T21
StPostPack->StCalcPlainEcc	231	Covered	T1,T17,T21
StPrePack->StPackData	205	Covered	T1,T17,T38
StReqFlash->StIdle	273	Covered	T1,T17,T5
StReqFlash->StWaitFlash	270	Covered	T1,T17,T20
StScrambleData->StCalcEcc	252	Covered	T5,T58,T26
StWaitFlash->StIdle	280	Covered	T1,T17,T20

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T17,T20
0	1	Covered	T1,T2,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T17,T20
0	0	1	Covered	T1,T17,T20
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T38
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T20
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T38
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T20
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T21
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T17,T20
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T17,T20
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T17,T21
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T13,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T58,T29
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T17,T20
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T58,T29
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T58,T29
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T58,T29
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T58,T29
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T58,T29
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T17,T20
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T17,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T17,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T17,T5
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T17,T20
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T17,T20
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T17,T20
0	0	1	-	-	Covered	T5,T58,T29
0	0	0	1	-	Covered	T5,T58,T29
0	0	0	0	1	Covered	T1,T17,T20
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T17,T20
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	402157978	1203444	0	0
PostPackRule_A	402157978	954	0	0
PrePackRule_A	402157978	709	0	0
WidthCheck_A	1046	1046	0	0
u_state_regs_A	402157978	401315557	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	1203444	0	0
T1	113641	104	0	0
T2	585556	0	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T5	0	157	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T17	2859	1	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	1	0	0
T21	0	1	0	0
T29	0	32800	0	0
T30	0	65600	0	0
T33	0	8608	0	0
T38	0	11	0	0
T58	0	1	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	954	0	0
T1	113641	4	0	0
T2	585556	0	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T17	2859	1	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	0	0	0
T21	0	1	0	0
T38	0	11	0	0
T41	0	1	0	0
T118	0	8	0	0
T130	0	11	0	0
T131	0	11	0	0
T238	0	1	0	0
T239	0	4	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	709	0	0
T1	113641	2	0	0
T2	585556	0	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T17	2859	1	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	0	0	0
T38	0	6	0	0
T41	0	2	0	0
T118	0	5	0	0
T130	0	10	0	0
T131	0	8	0	0
T144	0	3	0	0
T238	0	1	0	0
T239	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T155,T7,T184
1	0	Covered	T155,T7,T184

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T19
1	1	Covered	T155,T7,T184

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T85
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T155,T7,T184
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T1,T21,T38

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T4,T19

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T38,T118

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T38,T118

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T4,T19

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T1,T4,T19

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T21,T38

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T21,T38

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T21,T38
1	Covered	T4,T19,T5

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T19

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T19

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T19

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T19,T5
1	1	Covered	T4,T19,T5

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T19,T5
1	1	Covered	T4,T19,T5

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T19
1	1	0	Covered	T1,T4,T19
1	1	1	Covered	T1,T4,T19

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T19

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T4,T19,T5
StCalcMask	237	Covered	T4,T19,T5
StCalcPlainEcc	215	Covered	T1,T4,T19
StDisabled	193	Covered	T10,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T4,T19
StPostPack	218	Covered	T1,T21,T38
StPrePack	195	Covered	T1,T38,T118
StReqFlash	237	Covered	T1,T4,T19
StScrambleData	244	Covered	T4,T19,T5
StWaitFlash	270	Covered	T1,T4,T19

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T4,T19,T5
StCalcMask->StScrambleData	244	Covered	T4,T19,T5
StCalcPlainEcc->StCalcMask	237	Covered	T4,T19,T5
StCalcPlainEcc->StReqFlash	237	Covered	T1,T21,T38
StIdle->StDisabled	193	Covered	T10,T11,T12
StIdle->StPackData	197	Covered	T1,T4,T19
StIdle->StPrePack	195	Covered	T1,T38,T118
StPackData->StCalcPlainEcc	215	Covered	T1,T4,T19
StPackData->StPostPack	218	Covered	T1,T21,T38
StPostPack->StCalcPlainEcc	231	Covered	T1,T21,T38
StPrePack->StPackData	205	Covered	T1,T38,T118
StReqFlash->StIdle	273	Covered	T1,T4,T19
StReqFlash->StWaitFlash	270	Covered	T1,T4,T19
StScrambleData->StCalcEcc	252	Covered	T4,T19,T5
StWaitFlash->StIdle	280	Covered	T1,T4,T19

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T19
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T19
0	0	1	Covered	T1,T4,T19
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T38,T118
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T19
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T38,T118
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T19
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T38
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T4,T19
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T19
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T21,T38
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T13,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T19,T5
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T21,T38
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T4,T19,T5
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T19,T5
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T19,T5
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T19,T5
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T19,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T4,T19
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T4,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T4,T19
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T4,T5
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T19
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T19
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T4,T19
0	0	1	-	-	Covered	T4,T19,T5
0	0	0	1	-	Covered	T4,T19,T5
0	0	0	0	1	Covered	T1,T4,T19
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T19
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	402157978	1242940	0	0
PostPackRule_A	402157978	969	0	0
PrePackRule_A	402157978	697	0	0
WidthCheck_A	1046	1046	0	0
u_state_regs_A	402157978	401315557	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	1242940	0	0
T1	113641	195	0	0
T2	585556	0	0	0
T3	3968	0	0	0
T4	196470	173	0	0
T5	0	161	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T17	2859	0	0	0
T18	5536	0	0	0
T19	962696	4	0	0
T20	1715	0	0	0
T21	0	1	0	0
T23	0	2	0	0
T29	0	33280	0	0
T30	0	66560	0	0
T38	0	7	0	0
T45	0	388	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	969	0	0
T1	113641	3	0	0
T2	585556	0	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T17	2859	0	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	0	0	0
T21	0	1	0	0
T38	0	5	0	0
T118	0	6	0	0
T130	0	9	0	0
T131	0	3	0	0
T138	0	5	0	0
T144	0	5	0	0
T238	0	2	0	0
T239	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	697	0	0
T1	113641	3	0	0
T2	585556	0	0	0
T3	3968	0	0	0
T4	196470	0	0	0
T10	3509	0	0	0
T11	3764	0	0	0
T17	2859	0	0	0
T18	5536	0	0	0
T19	962696	0	0	0
T20	1715	0	0	0
T38	0	4	0	0
T118	0	5	0	0
T130	0	10	0	0
T131	0	4	0	0
T138	0	2	0	0
T144	0	4	0	0
T238	0	3	0	0
T239	0	5	0	0
T240	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402157978	401315557	0	0
T1	113641	113634	0	0
T2	585556	585380	0	0
T3	3968	3322	0	0
T4	196470	187438	0	0
T10	3509	2730	0	0
T11	3764	3101	0	0
T17	2859	2783	0	0
T18	5536	5475	0	0
T19	962696	962567	0	0
T20	1715	1599	0	0