| T1063 |
/workspace/coverage/default/33.flash_ctrl_rw_evict.1668281280 |
|
|
Jul 12 07:21:07 PM PDT 24 |
Jul 12 07:21:52 PM PDT 24 |
26744900 ps |
| T1064 |
/workspace/coverage/default/1.flash_ctrl_ro_serr.3602361917 |
|
|
Jul 12 07:09:08 PM PDT 24 |
Jul 12 07:11:13 PM PDT 24 |
1878098400 ps |
| T1065 |
/workspace/coverage/default/0.flash_ctrl_connect.1987829953 |
|
|
Jul 12 07:08:49 PM PDT 24 |
Jul 12 07:09:12 PM PDT 24 |
24876800 ps |
| T1066 |
/workspace/coverage/default/13.flash_ctrl_prog_reset.3089125862 |
|
|
Jul 12 07:17:13 PM PDT 24 |
Jul 12 07:18:07 PM PDT 24 |
47934400 ps |
| T1067 |
/workspace/coverage/default/18.flash_ctrl_rw_evict.2477253225 |
|
|
Jul 12 07:18:56 PM PDT 24 |
Jul 12 07:19:41 PM PDT 24 |
75736600 ps |
| T1068 |
/workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.3041261766 |
|
|
Jul 12 07:12:12 PM PDT 24 |
Jul 12 07:13:39 PM PDT 24 |
67438100 ps |
| T1069 |
/workspace/coverage/default/7.flash_ctrl_ro_derr.362999923 |
|
|
Jul 12 07:14:06 PM PDT 24 |
Jul 12 07:16:56 PM PDT 24 |
546936400 ps |
| T389 |
/workspace/coverage/default/3.flash_ctrl_fs_sup.251613895 |
|
|
Jul 12 07:11:54 PM PDT 24 |
Jul 12 07:13:43 PM PDT 24 |
696626200 ps |
| T1070 |
/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3043575988 |
|
|
Jul 12 07:09:14 PM PDT 24 |
Jul 12 07:12:14 PM PDT 24 |
41262585800 ps |
| T1071 |
/workspace/coverage/default/4.flash_ctrl_host_dir_rd.3897332575 |
|
|
Jul 12 07:11:53 PM PDT 24 |
Jul 12 07:13:36 PM PDT 24 |
86014700 ps |
| T1072 |
/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.424147113 |
|
|
Jul 12 07:15:40 PM PDT 24 |
Jul 12 07:18:22 PM PDT 24 |
10012431000 ps |
| T1073 |
/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3140594068 |
|
|
Jul 12 07:19:41 PM PDT 24 |
Jul 12 07:22:56 PM PDT 24 |
16611355200 ps |
| T1074 |
/workspace/coverage/default/20.flash_ctrl_smoke.3206295939 |
|
|
Jul 12 07:19:25 PM PDT 24 |
Jul 12 07:21:43 PM PDT 24 |
77303500 ps |
| T1075 |
/workspace/coverage/default/2.flash_ctrl_serr_address.3838856509 |
|
|
Jul 12 07:09:51 PM PDT 24 |
Jul 12 07:11:12 PM PDT 24 |
5186326700 ps |
| T1076 |
/workspace/coverage/default/4.flash_ctrl_otp_reset.1249164812 |
|
|
Jul 12 07:12:02 PM PDT 24 |
Jul 12 07:15:09 PM PDT 24 |
77216600 ps |
| T1077 |
/workspace/coverage/default/4.flash_ctrl_rw_serr.3084161683 |
|
|
Jul 12 07:12:12 PM PDT 24 |
Jul 12 07:22:51 PM PDT 24 |
5911007600 ps |
| T1078 |
/workspace/coverage/default/45.flash_ctrl_connect.591869620 |
|
|
Jul 12 07:22:01 PM PDT 24 |
Jul 12 07:22:22 PM PDT 24 |
39427900 ps |
| T1079 |
/workspace/coverage/default/23.flash_ctrl_connect.462050308 |
|
|
Jul 12 07:19:42 PM PDT 24 |
Jul 12 07:20:16 PM PDT 24 |
26160500 ps |
| T1080 |
/workspace/coverage/default/8.flash_ctrl_intr_rd.2015676973 |
|
|
Jul 12 07:15:22 PM PDT 24 |
Jul 12 07:19:34 PM PDT 24 |
10143945100 ps |
| T1081 |
/workspace/coverage/default/35.flash_ctrl_sec_info_access.3111908494 |
|
|
Jul 12 07:21:11 PM PDT 24 |
Jul 12 07:22:48 PM PDT 24 |
5018026100 ps |
| T1082 |
/workspace/coverage/default/43.flash_ctrl_hw_sec_otp.3490770581 |
|
|
Jul 12 07:21:54 PM PDT 24 |
Jul 12 07:23:28 PM PDT 24 |
1767980200 ps |
| T1083 |
/workspace/coverage/default/18.flash_ctrl_mp_regions.1757205400 |
|
|
Jul 12 07:18:43 PM PDT 24 |
Jul 12 07:24:54 PM PDT 24 |
10875173000 ps |
| T1084 |
/workspace/coverage/default/11.flash_ctrl_alert_test.1424285402 |
|
|
Jul 12 07:16:28 PM PDT 24 |
Jul 12 07:17:18 PM PDT 24 |
44818800 ps |
| T1085 |
/workspace/coverage/default/4.flash_ctrl_ro_serr.4052775495 |
|
|
Jul 12 07:12:14 PM PDT 24 |
Jul 12 07:15:40 PM PDT 24 |
7358939300 ps |
| T1086 |
/workspace/coverage/default/35.flash_ctrl_otp_reset.2637380726 |
|
|
Jul 12 07:21:03 PM PDT 24 |
Jul 12 07:23:30 PM PDT 24 |
37073300 ps |
| T1087 |
/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3583601868 |
|
|
Jul 12 07:17:57 PM PDT 24 |
Jul 12 07:19:54 PM PDT 24 |
10018811600 ps |
| T1088 |
/workspace/coverage/default/7.flash_ctrl_hw_sec_otp.2479175451 |
|
|
Jul 12 07:13:49 PM PDT 24 |
Jul 12 07:15:11 PM PDT 24 |
3498939100 ps |
| T1089 |
/workspace/coverage/default/4.flash_ctrl_erase_suspend.3291704845 |
|
|
Jul 12 07:11:55 PM PDT 24 |
Jul 12 07:20:25 PM PDT 24 |
2701918500 ps |
| T1090 |
/workspace/coverage/default/62.flash_ctrl_connect.661496490 |
|
|
Jul 12 07:22:22 PM PDT 24 |
Jul 12 07:22:41 PM PDT 24 |
52267500 ps |
| T1091 |
/workspace/coverage/default/58.flash_ctrl_otp_reset.3417643538 |
|
|
Jul 12 07:22:24 PM PDT 24 |
Jul 12 07:24:39 PM PDT 24 |
86313800 ps |
| T1092 |
/workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1772209819 |
|
|
Jul 12 07:15:29 PM PDT 24 |
Jul 12 07:18:27 PM PDT 24 |
12203551800 ps |
| T1093 |
/workspace/coverage/default/5.flash_ctrl_ro.2630630901 |
|
|
Jul 12 07:12:37 PM PDT 24 |
Jul 12 07:15:07 PM PDT 24 |
1065792200 ps |
| T1094 |
/workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3982642205 |
|
|
Jul 12 07:12:16 PM PDT 24 |
Jul 12 07:16:18 PM PDT 24 |
22522114100 ps |
| T1095 |
/workspace/coverage/default/46.flash_ctrl_connect.373259994 |
|
|
Jul 12 07:22:09 PM PDT 24 |
Jul 12 07:22:31 PM PDT 24 |
22034000 ps |
| T1096 |
/workspace/coverage/default/1.flash_ctrl_intr_wr.1462811125 |
|
|
Jul 12 07:09:14 PM PDT 24 |
Jul 12 07:10:29 PM PDT 24 |
2279698000 ps |
| T1097 |
/workspace/coverage/default/0.flash_ctrl_smoke_hw.1654391000 |
|
|
Jul 12 07:08:38 PM PDT 24 |
Jul 12 07:09:08 PM PDT 24 |
20370500 ps |
| T1098 |
/workspace/coverage/default/36.flash_ctrl_alert_test.994131958 |
|
|
Jul 12 07:21:10 PM PDT 24 |
Jul 12 07:21:38 PM PDT 24 |
54468000 ps |
| T1099 |
/workspace/coverage/default/21.flash_ctrl_prog_reset.4127089589 |
|
|
Jul 12 07:19:35 PM PDT 24 |
Jul 12 07:22:39 PM PDT 24 |
8232130400 ps |
| T1100 |
/workspace/coverage/default/0.flash_ctrl_prog_reset.1500708319 |
|
|
Jul 12 07:08:48 PM PDT 24 |
Jul 12 07:09:11 PM PDT 24 |
20968600 ps |
| T1101 |
/workspace/coverage/default/19.flash_ctrl_invalid_op.651351879 |
|
|
Jul 12 07:19:07 PM PDT 24 |
Jul 12 07:20:27 PM PDT 24 |
8763740500 ps |
| T1102 |
/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.4194629279 |
|
|
Jul 12 07:17:51 PM PDT 24 |
Jul 12 07:18:57 PM PDT 24 |
27887700 ps |
| T1103 |
/workspace/coverage/default/17.flash_ctrl_re_evict.2827268933 |
|
|
Jul 12 07:18:32 PM PDT 24 |
Jul 12 07:19:35 PM PDT 24 |
74480400 ps |
| T1104 |
/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.2693722390 |
|
|
Jul 12 07:15:22 PM PDT 24 |
Jul 12 07:16:41 PM PDT 24 |
29209900 ps |
| T1105 |
/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1266309547 |
|
|
Jul 12 07:10:42 PM PDT 24 |
Jul 12 07:12:58 PM PDT 24 |
5903917400 ps |
| T1106 |
/workspace/coverage/default/4.flash_ctrl_intr_rd.1761657950 |
|
|
Jul 12 07:12:14 PM PDT 24 |
Jul 12 07:15:27 PM PDT 24 |
2157202900 ps |
| T1107 |
/workspace/coverage/default/8.flash_ctrl_mp_regions.751587843 |
|
|
Jul 12 07:15:17 PM PDT 24 |
Jul 12 07:21:37 PM PDT 24 |
10790824700 ps |
| T91 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1328953612 |
|
|
Jul 12 06:43:24 PM PDT 24 |
Jul 12 06:43:45 PM PDT 24 |
53003900 ps |
| T1108 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2713262303 |
|
|
Jul 12 06:43:27 PM PDT 24 |
Jul 12 06:43:43 PM PDT 24 |
46762700 ps |
| T92 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3816650134 |
|
|
Jul 12 06:43:33 PM PDT 24 |
Jul 12 06:43:55 PM PDT 24 |
112679500 ps |
| T245 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.202808943 |
|
|
Jul 12 06:43:34 PM PDT 24 |
Jul 12 06:43:51 PM PDT 24 |
18354400 ps |
| T1109 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.287870972 |
|
|
Jul 12 06:43:24 PM PDT 24 |
Jul 12 06:43:40 PM PDT 24 |
12038300 ps |
| T246 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2401573529 |
|
|
Jul 12 06:43:31 PM PDT 24 |
Jul 12 06:43:51 PM PDT 24 |
52364800 ps |
| T65 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2211107693 |
|
|
Jul 12 06:43:14 PM PDT 24 |
Jul 12 06:44:20 PM PDT 24 |
2581350600 ps |
| T1110 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1187009429 |
|
|
Jul 12 06:43:25 PM PDT 24 |
Jul 12 06:43:43 PM PDT 24 |
36178200 ps |
| T247 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2977489333 |
|
|
Jul 12 06:43:32 PM PDT 24 |
Jul 12 06:43:48 PM PDT 24 |
39539400 ps |
| T66 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.762181507 |
|
|
Jul 12 06:43:18 PM PDT 24 |
Jul 12 06:58:28 PM PDT 24 |
1596011000 ps |
| T1111 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2578633331 |
|
|
Jul 12 06:43:14 PM PDT 24 |
Jul 12 06:43:32 PM PDT 24 |
21551800 ps |
| T1112 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.452871146 |
|
|
Jul 12 06:43:23 PM PDT 24 |
Jul 12 06:43:37 PM PDT 24 |
22681800 ps |
| T188 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.403476993 |
|
|
Jul 12 06:43:33 PM PDT 24 |
Jul 12 06:43:51 PM PDT 24 |
57502900 ps |
| T221 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2311916142 |
|
|
Jul 12 06:43:25 PM PDT 24 |
Jul 12 06:43:40 PM PDT 24 |
18792800 ps |
| T1113 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3979684972 |
|
|
Jul 12 06:43:34 PM PDT 24 |
Jul 12 06:43:52 PM PDT 24 |
46886900 ps |
| T67 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1581727880 |
|
|
Jul 12 06:43:22 PM PDT 24 |
Jul 12 06:44:10 PM PDT 24 |
1197863600 ps |
| T305 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1785589231 |
|
|
Jul 12 06:43:25 PM PDT 24 |
Jul 12 06:43:40 PM PDT 24 |
54176400 ps |
| T93 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3494193406 |
|
|
Jul 12 06:43:38 PM PDT 24 |
Jul 12 06:56:19 PM PDT 24 |
2042037900 ps |
| T243 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4167863539 |
|
|
Jul 12 06:43:22 PM PDT 24 |
Jul 12 06:44:01 PM PDT 24 |
785746400 ps |
| T1114 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.780664168 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:43:46 PM PDT 24 |
11614000 ps |
| T242 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1248351438 |
|
|
Jul 12 06:43:39 PM PDT 24 |
Jul 12 06:44:02 PM PDT 24 |
74894400 ps |
| T1115 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.13056343 |
|
|
Jul 12 06:43:25 PM PDT 24 |
Jul 12 06:43:40 PM PDT 24 |
16786300 ps |
| T94 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1646051081 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:43:49 PM PDT 24 |
102118500 ps |
| T1116 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2941257685 |
|
|
Jul 12 06:43:23 PM PDT 24 |
Jul 12 06:43:39 PM PDT 24 |
35461000 ps |
| T278 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.132615392 |
|
|
Jul 12 06:43:48 PM PDT 24 |
Jul 12 06:44:32 PM PDT 24 |
223882100 ps |
| T306 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2592055817 |
|
|
Jul 12 06:43:24 PM PDT 24 |
Jul 12 06:43:40 PM PDT 24 |
15428300 ps |
| T216 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.77017247 |
|
|
Jul 12 06:43:24 PM PDT 24 |
Jul 12 06:43:42 PM PDT 24 |
31646900 ps |
| T279 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1542347669 |
|
|
Jul 12 06:43:06 PM PDT 24 |
Jul 12 06:43:27 PM PDT 24 |
259195200 ps |
| T307 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3045086458 |
|
|
Jul 12 06:43:21 PM PDT 24 |
Jul 12 06:43:35 PM PDT 24 |
41371100 ps |
| T1117 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2584301483 |
|
|
Jul 12 06:43:24 PM PDT 24 |
Jul 12 06:44:00 PM PDT 24 |
675857500 ps |
| T217 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3422610547 |
|
|
Jul 12 06:43:21 PM PDT 24 |
Jul 12 06:43:41 PM PDT 24 |
430597800 ps |
| T218 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3972178455 |
|
|
Jul 12 06:43:30 PM PDT 24 |
Jul 12 06:43:50 PM PDT 24 |
55139500 ps |
| T219 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2014815628 |
|
|
Jul 12 06:43:44 PM PDT 24 |
Jul 12 06:44:12 PM PDT 24 |
469393500 ps |
| T1118 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3208458451 |
|
|
Jul 12 06:43:10 PM PDT 24 |
Jul 12 06:44:29 PM PDT 24 |
2366377000 ps |
| T220 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3320767434 |
|
|
Jul 12 06:43:21 PM PDT 24 |
Jul 12 06:43:50 PM PDT 24 |
39254600 ps |
| T308 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1907770602 |
|
|
Jul 12 06:43:38 PM PDT 24 |
Jul 12 06:43:57 PM PDT 24 |
43258700 ps |
| T1119 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3493981814 |
|
|
Jul 12 06:43:39 PM PDT 24 |
Jul 12 06:44:04 PM PDT 24 |
132179400 ps |
| T280 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.306545419 |
|
|
Jul 12 06:43:32 PM PDT 24 |
Jul 12 06:43:53 PM PDT 24 |
443448700 ps |
| T1120 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4278706380 |
|
|
Jul 12 06:43:42 PM PDT 24 |
Jul 12 06:44:01 PM PDT 24 |
21487100 ps |
| T309 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1021265530 |
|
|
Jul 12 06:43:31 PM PDT 24 |
Jul 12 06:43:47 PM PDT 24 |
23582000 ps |
| T1121 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2538314475 |
|
|
Jul 12 06:43:38 PM PDT 24 |
Jul 12 06:43:57 PM PDT 24 |
21223700 ps |
| T1122 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1812194340 |
|
|
Jul 12 06:43:53 PM PDT 24 |
Jul 12 06:44:12 PM PDT 24 |
17911000 ps |
| T241 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3467464149 |
|
|
Jul 12 06:43:43 PM PDT 24 |
Jul 12 06:59:19 PM PDT 24 |
3992605400 ps |
| T248 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1351486116 |
|
|
Jul 12 06:43:29 PM PDT 24 |
Jul 12 06:43:48 PM PDT 24 |
36720800 ps |
| T253 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3172321894 |
|
|
Jul 12 06:43:29 PM PDT 24 |
Jul 12 06:49:57 PM PDT 24 |
1408977200 ps |
| T1123 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1543634693 |
|
|
Jul 12 06:43:31 PM PDT 24 |
Jul 12 06:43:49 PM PDT 24 |
16161900 ps |
| T1124 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3251942777 |
|
|
Jul 12 06:43:22 PM PDT 24 |
Jul 12 06:43:41 PM PDT 24 |
127981300 ps |
| T1125 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.902923306 |
|
|
Jul 12 06:43:30 PM PDT 24 |
Jul 12 06:43:47 PM PDT 24 |
48453700 ps |
| T1126 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1410587312 |
|
|
Jul 12 06:43:25 PM PDT 24 |
Jul 12 06:44:02 PM PDT 24 |
489951500 ps |
| T1127 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2552620441 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:44:31 PM PDT 24 |
647552000 ps |
| T1128 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1910318788 |
|
|
Jul 12 06:43:44 PM PDT 24 |
Jul 12 06:44:05 PM PDT 24 |
62545400 ps |
| T1129 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3320147158 |
|
|
Jul 12 06:43:39 PM PDT 24 |
Jul 12 06:43:57 PM PDT 24 |
64119900 ps |
| T244 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2109380411 |
|
|
Jul 12 06:43:17 PM PDT 24 |
Jul 12 06:43:38 PM PDT 24 |
52629100 ps |
| T1130 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1805002711 |
|
|
Jul 12 06:43:29 PM PDT 24 |
Jul 12 06:43:47 PM PDT 24 |
17846800 ps |
| T1131 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3398103021 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:43:46 PM PDT 24 |
14775300 ps |
| T1132 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2780591370 |
|
|
Jul 12 06:43:52 PM PDT 24 |
Jul 12 06:44:11 PM PDT 24 |
161969800 ps |
| T1133 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.694374250 |
|
|
Jul 12 06:43:49 PM PDT 24 |
Jul 12 06:44:12 PM PDT 24 |
15462600 ps |
| T252 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1593108124 |
|
|
Jul 12 06:43:24 PM PDT 24 |
Jul 12 06:43:45 PM PDT 24 |
64230800 ps |
| T1134 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2334034068 |
|
|
Jul 12 06:43:23 PM PDT 24 |
Jul 12 06:43:38 PM PDT 24 |
16454400 ps |
| T1135 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2317466320 |
|
|
Jul 12 06:43:15 PM PDT 24 |
Jul 12 06:43:49 PM PDT 24 |
471583800 ps |
| T322 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1860334475 |
|
|
Jul 12 06:43:18 PM PDT 24 |
Jul 12 06:55:53 PM PDT 24 |
1502117200 ps |
| T1136 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2043959443 |
|
|
Jul 12 06:43:15 PM PDT 24 |
Jul 12 06:43:32 PM PDT 24 |
51116300 ps |
| T325 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4047170631 |
|
|
Jul 12 06:43:49 PM PDT 24 |
Jul 12 06:51:34 PM PDT 24 |
679291200 ps |
| T330 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1957667436 |
|
|
Jul 12 06:43:17 PM PDT 24 |
Jul 12 06:58:22 PM PDT 24 |
1441849300 ps |
| T281 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2803321503 |
|
|
Jul 12 06:43:19 PM PDT 24 |
Jul 12 06:44:17 PM PDT 24 |
10341192800 ps |
| T1137 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1697019267 |
|
|
Jul 12 06:43:44 PM PDT 24 |
Jul 12 06:44:37 PM PDT 24 |
259097100 ps |
| T1138 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.4014680036 |
|
|
Jul 12 06:43:47 PM PDT 24 |
Jul 12 06:44:08 PM PDT 24 |
23009900 ps |
| T1139 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.804161986 |
|
|
Jul 12 06:43:09 PM PDT 24 |
Jul 12 06:43:27 PM PDT 24 |
90799900 ps |
| T1140 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1759431705 |
|
|
Jul 12 06:43:02 PM PDT 24 |
Jul 12 06:43:19 PM PDT 24 |
25513300 ps |
| T1141 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3670384889 |
|
|
Jul 12 06:43:53 PM PDT 24 |
Jul 12 06:44:13 PM PDT 24 |
27811300 ps |
| T1142 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3455727292 |
|
|
Jul 12 06:43:48 PM PDT 24 |
Jul 12 06:44:09 PM PDT 24 |
54815900 ps |
| T1143 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.727923140 |
|
|
Jul 12 06:43:44 PM PDT 24 |
Jul 12 06:44:11 PM PDT 24 |
59352700 ps |
| T1144 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3632756022 |
|
|
Jul 12 06:43:37 PM PDT 24 |
Jul 12 06:43:55 PM PDT 24 |
13044300 ps |
| T1145 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3591200067 |
|
|
Jul 12 06:43:56 PM PDT 24 |
Jul 12 06:44:17 PM PDT 24 |
25398600 ps |
| T282 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3150484294 |
|
|
Jul 12 06:43:27 PM PDT 24 |
Jul 12 06:43:45 PM PDT 24 |
101309300 ps |
| T1146 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3325096055 |
|
|
Jul 12 06:43:38 PM PDT 24 |
Jul 12 06:43:56 PM PDT 24 |
14701500 ps |
| T1147 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2303989344 |
|
|
Jul 12 06:43:33 PM PDT 24 |
Jul 12 06:43:49 PM PDT 24 |
16406300 ps |
| T323 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4035608821 |
|
|
Jul 12 06:43:33 PM PDT 24 |
Jul 12 06:51:07 PM PDT 24 |
380391900 ps |
| T1148 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.357801665 |
|
|
Jul 12 06:43:22 PM PDT 24 |
Jul 12 06:43:39 PM PDT 24 |
15658200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3781116267 |
|
|
Jul 12 06:43:30 PM PDT 24 |
Jul 12 06:43:49 PM PDT 24 |
61256300 ps |
| T1150 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.366163560 |
|
|
Jul 12 06:43:30 PM PDT 24 |
Jul 12 06:43:49 PM PDT 24 |
24320200 ps |
| T1151 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.233566391 |
|
|
Jul 12 06:43:25 PM PDT 24 |
Jul 12 06:43:39 PM PDT 24 |
29162500 ps |
| T251 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3912981163 |
|
|
Jul 12 06:43:08 PM PDT 24 |
Jul 12 06:43:31 PM PDT 24 |
102802700 ps |
| T283 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3108010899 |
|
|
Jul 12 06:43:25 PM PDT 24 |
Jul 12 06:43:46 PM PDT 24 |
530109300 ps |
| T1152 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2766178699 |
|
|
Jul 12 06:43:20 PM PDT 24 |
Jul 12 06:43:36 PM PDT 24 |
34850700 ps |
| T1153 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2375903094 |
|
|
Jul 12 06:43:21 PM PDT 24 |
Jul 12 06:43:35 PM PDT 24 |
24139800 ps |
| T284 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1290927498 |
|
|
Jul 12 06:43:09 PM PDT 24 |
Jul 12 06:43:44 PM PDT 24 |
56537000 ps |
| T1154 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.231146335 |
|
|
Jul 12 06:43:32 PM PDT 24 |
Jul 12 06:43:50 PM PDT 24 |
21491900 ps |
| T1155 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3190846291 |
|
|
Jul 12 06:43:48 PM PDT 24 |
Jul 12 06:44:09 PM PDT 24 |
54150100 ps |
| T254 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1192302870 |
|
|
Jul 12 06:43:26 PM PDT 24 |
Jul 12 06:43:44 PM PDT 24 |
105988800 ps |
| T324 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3067758999 |
|
|
Jul 12 06:43:09 PM PDT 24 |
Jul 12 06:58:23 PM PDT 24 |
1230214100 ps |
| T1156 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3593452356 |
|
|
Jul 12 06:43:43 PM PDT 24 |
Jul 12 06:44:05 PM PDT 24 |
17342700 ps |
| T285 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4141657923 |
|
|
Jul 12 06:43:26 PM PDT 24 |
Jul 12 06:43:44 PM PDT 24 |
68796000 ps |
| T1157 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.416646366 |
|
|
Jul 12 06:43:47 PM PDT 24 |
Jul 12 06:44:10 PM PDT 24 |
23990700 ps |
| T286 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3582725460 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:44:16 PM PDT 24 |
164480800 ps |
| T1158 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4282850865 |
|
|
Jul 12 06:43:43 PM PDT 24 |
Jul 12 06:44:07 PM PDT 24 |
30089200 ps |
| T1159 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1582974492 |
|
|
Jul 12 06:43:09 PM PDT 24 |
Jul 12 06:43:29 PM PDT 24 |
344313600 ps |
| T249 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4153582424 |
|
|
Jul 12 06:43:32 PM PDT 24 |
Jul 12 06:43:54 PM PDT 24 |
79046100 ps |
| T1160 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2606596490 |
|
|
Jul 12 06:43:42 PM PDT 24 |
Jul 12 06:44:02 PM PDT 24 |
52128300 ps |
| T331 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.484913040 |
|
|
Jul 12 06:43:17 PM PDT 24 |
Jul 12 06:50:59 PM PDT 24 |
497972600 ps |
| T1161 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2941018762 |
|
|
Jul 12 06:43:19 PM PDT 24 |
Jul 12 06:43:36 PM PDT 24 |
14581600 ps |
| T1162 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3034274718 |
|
|
Jul 12 06:43:27 PM PDT 24 |
Jul 12 06:43:48 PM PDT 24 |
319993400 ps |
| T1163 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.4089380883 |
|
|
Jul 12 06:43:08 PM PDT 24 |
Jul 12 06:43:30 PM PDT 24 |
48021000 ps |
| T1164 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1766051966 |
|
|
Jul 12 06:43:42 PM PDT 24 |
Jul 12 06:44:02 PM PDT 24 |
245010500 ps |
| T1165 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.73568807 |
|
|
Jul 12 06:43:26 PM PDT 24 |
Jul 12 06:44:04 PM PDT 24 |
178237900 ps |
| T1166 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3845686017 |
|
|
Jul 12 06:43:38 PM PDT 24 |
Jul 12 06:43:59 PM PDT 24 |
55492800 ps |
| T1167 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.503732402 |
|
|
Jul 12 06:43:13 PM PDT 24 |
Jul 12 06:43:29 PM PDT 24 |
14260300 ps |
| T1168 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4250264807 |
|
|
Jul 12 06:43:15 PM PDT 24 |
Jul 12 06:43:34 PM PDT 24 |
200818000 ps |
| T1169 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3256587460 |
|
|
Jul 12 06:43:10 PM PDT 24 |
Jul 12 06:43:28 PM PDT 24 |
50380900 ps |
| T1170 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3216981985 |
|
|
Jul 12 06:43:47 PM PDT 24 |
Jul 12 06:44:09 PM PDT 24 |
11931200 ps |
| T1171 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.504457292 |
|
|
Jul 12 06:43:30 PM PDT 24 |
Jul 12 06:43:52 PM PDT 24 |
318898200 ps |
| T1172 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2120184526 |
|
|
Jul 12 06:43:32 PM PDT 24 |
Jul 12 06:43:48 PM PDT 24 |
81015100 ps |
| T1173 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.640780674 |
|
|
Jul 12 06:43:47 PM PDT 24 |
Jul 12 06:44:08 PM PDT 24 |
18002800 ps |
| T1174 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1231711019 |
|
|
Jul 12 06:50:42 PM PDT 24 |
Jul 12 06:51:03 PM PDT 24 |
129160700 ps |
| T1175 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3431492412 |
|
|
Jul 12 06:43:06 PM PDT 24 |
Jul 12 06:43:26 PM PDT 24 |
126883200 ps |
| T222 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3106175640 |
|
|
Jul 12 06:43:16 PM PDT 24 |
Jul 12 06:43:31 PM PDT 24 |
85103600 ps |
| T1176 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1760863375 |
|
|
Jul 12 06:43:43 PM PDT 24 |
Jul 12 06:44:04 PM PDT 24 |
77213100 ps |
| T1177 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2988670132 |
|
|
Jul 12 06:43:47 PM PDT 24 |
Jul 12 06:44:12 PM PDT 24 |
54475200 ps |
| T326 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1205377826 |
|
|
Jul 12 06:43:20 PM PDT 24 |
Jul 12 06:58:35 PM PDT 24 |
1322847700 ps |
| T332 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.941449227 |
|
|
Jul 12 06:43:38 PM PDT 24 |
Jul 12 06:56:34 PM PDT 24 |
2650551200 ps |
| T1178 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1735538611 |
|
|
Jul 12 06:43:33 PM PDT 24 |
Jul 12 06:43:50 PM PDT 24 |
65528200 ps |
| T1179 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3362596263 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:43:43 PM PDT 24 |
30310800 ps |
| T223 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3410816759 |
|
|
Jul 12 06:43:02 PM PDT 24 |
Jul 12 06:43:19 PM PDT 24 |
115864700 ps |
| T333 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.612810882 |
|
|
Jul 12 06:43:27 PM PDT 24 |
Jul 12 06:51:06 PM PDT 24 |
351406500 ps |
| T287 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3127644747 |
|
|
Jul 12 06:43:14 PM PDT 24 |
Jul 12 06:43:34 PM PDT 24 |
96442400 ps |
| T1180 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.753715328 |
|
|
Jul 12 06:43:46 PM PDT 24 |
Jul 12 06:44:07 PM PDT 24 |
43782600 ps |
| T1181 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3551167831 |
|
|
Jul 12 06:43:29 PM PDT 24 |
Jul 12 06:43:45 PM PDT 24 |
32301800 ps |
| T1182 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3697832167 |
|
|
Jul 12 06:43:48 PM PDT 24 |
Jul 12 06:44:12 PM PDT 24 |
280534900 ps |
| T250 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3674600365 |
|
|
Jul 12 06:43:19 PM PDT 24 |
Jul 12 06:55:49 PM PDT 24 |
669687100 ps |
| T1183 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2805823084 |
|
|
Jul 12 06:43:43 PM PDT 24 |
Jul 12 06:44:03 PM PDT 24 |
97901600 ps |
| T327 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2754914439 |
|
|
Jul 12 06:43:20 PM PDT 24 |
Jul 12 06:58:18 PM PDT 24 |
4637877700 ps |
| T1184 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2781430457 |
|
|
Jul 12 06:43:46 PM PDT 24 |
Jul 12 06:44:07 PM PDT 24 |
22997300 ps |
| T1185 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.901381095 |
|
|
Jul 12 06:43:42 PM PDT 24 |
Jul 12 06:44:02 PM PDT 24 |
18530200 ps |
| T1186 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3050515996 |
|
|
Jul 12 06:43:44 PM PDT 24 |
Jul 12 06:44:06 PM PDT 24 |
34420600 ps |
| T1187 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1973884681 |
|
|
Jul 12 06:43:05 PM PDT 24 |
Jul 12 06:43:21 PM PDT 24 |
19102200 ps |
| T329 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3889112332 |
|
|
Jul 12 06:43:22 PM PDT 24 |
Jul 12 06:51:02 PM PDT 24 |
729385300 ps |
| T1188 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.697234425 |
|
|
Jul 12 06:43:26 PM PDT 24 |
Jul 12 06:43:43 PM PDT 24 |
28814300 ps |
| T1189 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3637122400 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:43:45 PM PDT 24 |
193625100 ps |
| T288 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1943114675 |
|
|
Jul 12 06:43:39 PM PDT 24 |
Jul 12 06:44:03 PM PDT 24 |
433776400 ps |
| T1190 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3423192649 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:43:48 PM PDT 24 |
111945200 ps |
| T1191 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3035668540 |
|
|
Jul 12 06:43:46 PM PDT 24 |
Jul 12 06:44:09 PM PDT 24 |
21279600 ps |
| T1192 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.366335650 |
|
|
Jul 12 06:43:39 PM PDT 24 |
Jul 12 06:43:58 PM PDT 24 |
51062900 ps |
| T1193 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1194347546 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:44:01 PM PDT 24 |
804754200 ps |
| T1194 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.284981401 |
|
|
Jul 12 06:43:23 PM PDT 24 |
Jul 12 06:43:38 PM PDT 24 |
114314200 ps |
| T1195 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1131827727 |
|
|
Jul 12 06:43:23 PM PDT 24 |
Jul 12 06:43:42 PM PDT 24 |
225150100 ps |
| T1196 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3904359265 |
|
|
Jul 12 06:43:27 PM PDT 24 |
Jul 12 06:43:41 PM PDT 24 |
14784500 ps |
| T1197 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1314143476 |
|
|
Jul 12 06:43:24 PM PDT 24 |
Jul 12 06:43:39 PM PDT 24 |
77612200 ps |
| T1198 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1405462915 |
|
|
Jul 12 06:43:29 PM PDT 24 |
Jul 12 06:43:48 PM PDT 24 |
476550500 ps |
| T1199 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1966396931 |
|
|
Jul 12 06:43:36 PM PDT 24 |
Jul 12 06:43:56 PM PDT 24 |
109280800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.289937871 |
|
|
Jul 12 06:43:30 PM PDT 24 |
Jul 12 06:43:49 PM PDT 24 |
24753200 ps |
| T1201 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2359247472 |
|
|
Jul 12 06:43:21 PM PDT 24 |
Jul 12 06:43:36 PM PDT 24 |
69552200 ps |
| T1202 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.157141719 |
|
|
Jul 12 06:43:20 PM PDT 24 |
Jul 12 06:43:38 PM PDT 24 |
53790000 ps |
| T1203 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4190908188 |
|
|
Jul 12 06:43:20 PM PDT 24 |
Jul 12 06:43:35 PM PDT 24 |
84343100 ps |
| T1204 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2838110644 |
|
|
Jul 12 06:43:40 PM PDT 24 |
Jul 12 06:56:24 PM PDT 24 |
1436793400 ps |
| T1205 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3021520907 |
|
|
Jul 12 06:43:19 PM PDT 24 |
Jul 12 06:43:33 PM PDT 24 |
16045800 ps |
| T1206 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.371599399 |
|
|
Jul 12 06:43:48 PM PDT 24 |
Jul 12 06:44:09 PM PDT 24 |
16359900 ps |
| T1207 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2980169221 |
|
|
Jul 12 06:43:18 PM PDT 24 |
Jul 12 06:43:37 PM PDT 24 |
656450100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2524125877 |
|
|
Jul 12 06:43:16 PM PDT 24 |
Jul 12 06:43:34 PM PDT 24 |
13747700 ps |
| T1209 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1241295431 |
|
|
Jul 12 06:43:37 PM PDT 24 |
Jul 12 06:43:54 PM PDT 24 |
14764300 ps |
| T1210 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3170533557 |
|
|
Jul 12 06:43:10 PM PDT 24 |
Jul 12 06:43:33 PM PDT 24 |
57886200 ps |
| T1211 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2143008451 |
|
|
Jul 12 06:43:31 PM PDT 24 |
Jul 12 06:43:47 PM PDT 24 |
25096300 ps |
| T1212 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3089421956 |
|
|
Jul 12 06:43:13 PM PDT 24 |
Jul 12 06:43:36 PM PDT 24 |
151046300 ps |
| T1213 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1910234920 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:43:44 PM PDT 24 |
71006200 ps |
| T1214 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3605950465 |
|
|
Jul 12 06:43:25 PM PDT 24 |
Jul 12 06:44:00 PM PDT 24 |
440658400 ps |
| T1215 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3144689241 |
|
|
Jul 12 06:43:30 PM PDT 24 |
Jul 12 06:43:47 PM PDT 24 |
18684400 ps |
| T1216 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1732920805 |
|
|
Jul 12 06:43:36 PM PDT 24 |
Jul 12 06:43:59 PM PDT 24 |
560476600 ps |
| T1217 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3544516303 |
|
|
Jul 12 06:43:34 PM PDT 24 |
Jul 12 06:43:55 PM PDT 24 |
341397800 ps |
| T1218 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1463329168 |
|
|
Jul 12 06:43:27 PM PDT 24 |
Jul 12 06:44:03 PM PDT 24 |
886409300 ps |
| T1219 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1596097215 |
|
|
Jul 12 06:43:38 PM PDT 24 |
Jul 12 06:43:57 PM PDT 24 |
30227200 ps |
| T1220 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1434026124 |
|
|
Jul 12 06:43:26 PM PDT 24 |
Jul 12 06:43:47 PM PDT 24 |
100622800 ps |
| T1221 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2976518618 |
|
|
Jul 12 06:43:54 PM PDT 24 |
Jul 12 06:44:14 PM PDT 24 |
61225200 ps |
| T1222 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.455120794 |
|
|
Jul 12 06:43:37 PM PDT 24 |
Jul 12 06:43:55 PM PDT 24 |
17208000 ps |
| T1223 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.583561122 |
|
|
Jul 12 06:43:25 PM PDT 24 |
Jul 12 06:43:43 PM PDT 24 |
14500000 ps |
| T1224 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1620481382 |
|
|
Jul 12 06:43:19 PM PDT 24 |
Jul 12 06:43:35 PM PDT 24 |
27086000 ps |
| T1225 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.278208017 |
|
|
Jul 12 06:43:39 PM PDT 24 |
Jul 12 06:43:59 PM PDT 24 |
18471300 ps |
| T1226 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3068342614 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:43:49 PM PDT 24 |
39736900 ps |
| T334 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.4239127582 |
|
|
Jul 12 06:43:43 PM PDT 24 |
Jul 12 06:51:33 PM PDT 24 |
690027500 ps |
| T1227 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2934068959 |
|
|
Jul 12 06:43:20 PM PDT 24 |
Jul 12 06:43:37 PM PDT 24 |
30846300 ps |
| T1228 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3562177 |
|
|
Jul 12 06:43:27 PM PDT 24 |
Jul 12 06:43:50 PM PDT 24 |
63223500 ps |
| T1229 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.4079675204 |
|
|
Jul 12 06:43:13 PM PDT 24 |
Jul 12 06:43:30 PM PDT 24 |
37884600 ps |
| T1230 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2672949053 |
|
|
Jul 12 06:43:24 PM PDT 24 |
Jul 12 06:43:42 PM PDT 24 |
75346400 ps |
| T1231 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1650613518 |
|
|
Jul 12 06:43:11 PM PDT 24 |
Jul 12 06:43:30 PM PDT 24 |
22978100 ps |
| T1232 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1631078238 |
|
|
Jul 12 06:43:05 PM PDT 24 |
Jul 12 06:43:57 PM PDT 24 |
4943553700 ps |
| T1233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3080103922 |
|
|
Jul 12 06:43:20 PM PDT 24 |
Jul 12 06:44:27 PM PDT 24 |
8983080600 ps |
| T1234 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2049320005 |
|
|
Jul 12 06:43:36 PM PDT 24 |
Jul 12 06:43:53 PM PDT 24 |
26475300 ps |
| T1235 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2829449515 |
|
|
Jul 12 06:43:17 PM PDT 24 |
Jul 12 06:43:32 PM PDT 24 |
19219800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3760244272 |
|
|
Jul 12 06:43:41 PM PDT 24 |
Jul 12 06:44:03 PM PDT 24 |
61431400 ps |
| T1237 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2010436748 |
|
|
Jul 12 06:43:44 PM PDT 24 |
Jul 12 06:44:06 PM PDT 24 |
15256700 ps |
| T1238 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2122893642 |
|
|
Jul 12 06:43:18 PM PDT 24 |
Jul 12 06:43:34 PM PDT 24 |
46612000 ps |
| T1239 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.250191236 |
|
|
Jul 12 06:43:57 PM PDT 24 |
Jul 12 06:44:19 PM PDT 24 |
22975400 ps |
| T1240 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.744535020 |
|
|
Jul 12 06:43:43 PM PDT 24 |
Jul 12 06:44:07 PM PDT 24 |
12430900 ps |
| T1241 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3187735002 |
|
|
Jul 12 06:43:16 PM PDT 24 |
Jul 12 06:43:38 PM PDT 24 |
130825000 ps |
| T1242 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.196187289 |
|
|
Jul 12 06:43:55 PM PDT 24 |
Jul 12 06:44:14 PM PDT 24 |
16386600 ps |
| T1243 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2049399339 |
|
|
Jul 12 06:43:12 PM PDT 24 |
Jul 12 06:43:33 PM PDT 24 |
77042800 ps |
| T1244 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2021332331 |
|
|
Jul 12 06:43:27 PM PDT 24 |
Jul 12 06:43:45 PM PDT 24 |
13397000 ps |
| T1245 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3893045010 |
|
|
Jul 12 06:43:22 PM PDT 24 |
Jul 12 06:55:59 PM PDT 24 |
5269551100 ps |
| T1246 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1235728498 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:43:45 PM PDT 24 |
180903700 ps |
| T1247 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.868004099 |
|
|
Jul 12 06:43:38 PM PDT 24 |
Jul 12 06:43:59 PM PDT 24 |
115552800 ps |
| T1248 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.771576577 |
|
|
Jul 12 06:43:30 PM PDT 24 |
Jul 12 06:43:46 PM PDT 24 |
31044800 ps |
| T1249 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2949623492 |
|
|
Jul 12 06:43:33 PM PDT 24 |
Jul 12 06:43:55 PM PDT 24 |
963196000 ps |
| T224 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1217684836 |
|
|
Jul 12 06:43:28 PM PDT 24 |
Jul 12 06:43:44 PM PDT 24 |
25682200 ps |
| T1250 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2995265994 |
|
|
Jul 12 06:43:31 PM PDT 24 |
Jul 12 06:43:52 PM PDT 24 |
49743500 ps |
| T1251 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3017923945 |
|
|
Jul 12 06:43:08 PM PDT 24 |
Jul 12 06:43:50 PM PDT 24 |
2549204200 ps |
| T1252 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1349798770 |
|
|
Jul 12 06:43:21 PM PDT 24 |
Jul 12 06:43:36 PM PDT 24 |
16928900 ps |