Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.26	95.73	93.98	98.31	92.52	98.25	96.80	98.24

Total test records in report: 1261

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T328	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3440853752			Jul 12 06:43:11 PM PDT 24	Jul 12 06:49:38 PM PDT 24	648141700 ps
T1253	/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.989765434			Jul 12 06:43:39 PM PDT 24	Jul 12 06:43:58 PM PDT 24	17255900 ps
T1254	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.786011723			Jul 12 06:43:15 PM PDT 24	Jul 12 06:43:32 PM PDT 24	164027300 ps
T1255	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2341902739			Jul 12 06:43:37 PM PDT 24	Jul 12 06:44:01 PM PDT 24	228856800 ps
T1256	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2338841638			Jul 12 06:43:26 PM PDT 24	Jul 12 06:43:45 PM PDT 24	174306300 ps
T1257	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.951060714			Jul 12 06:43:27 PM PDT 24	Jul 12 06:43:46 PM PDT 24	217289500 ps
T1258	/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.984023427			Jul 12 06:43:35 PM PDT 24	Jul 12 06:43:52 PM PDT 24	27136200 ps
T1259	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.154716307			Jul 12 06:43:23 PM PDT 24	Jul 12 06:43:55 PM PDT 24	57986800 ps
T1260	/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4206916956			Jul 12 06:43:29 PM PDT 24	Jul 12 06:43:52 PM PDT 24	444622800 ps
T225	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1411240341			Jul 12 06:43:23 PM PDT 24	Jul 12 06:43:39 PM PDT 24	52377100 ps
T1261	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.494740791			Jul 12 06:43:37 PM PDT 24	Jul 12 06:43:59 PM PDT 24	304430700 ps

Test location	/workspace/coverage/default/4.flash_ctrl_mp_regions.2542213145
Short name	T1
Test name
Test status
Simulation time	22728245600 ps
CPU time	278.72 seconds
Started	Jul 12 07:12:03 PM PDT 24
Finished	Jul 12 07:17:42 PM PDT 24
Peak memory	274360 kb
Host	smart-8e5e253c-2237-42d6-a194-0045b1a9621a
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542213145 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.2542213145
Directory	/workspace/4.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.2290753244
Short name	T2
Test name
Test status
Simulation time	23422347100 ps
CPU time	172.68 seconds
Started	Jul 12 07:21:09 PM PDT 24
Finished	Jul 12 07:24:17 PM PDT 24
Peak memory	285104 kb
Host	smart-5bcf8519-be4f-4991-bbd4-6d9daaa71355
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290753244 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.2290753244
Directory	/workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.762181507
Short name	T66
Test name
Test status
Simulation time	1596011000 ps
CPU time	908.96 seconds
Started	Jul 12 06:43:18 PM PDT 24
Finished	Jul 12 06:58:28 PM PDT 24
Peak memory	263732 kb
Host	smart-af1b6dd2-e854-41d8-9537-30bf40a3ea70
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762181507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl _tl_intg_err.762181507
Directory	/workspace/11.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rma_err.495389103
Short name	T29
Test name
Test status
Simulation time	80565484200 ps
CPU time	917.24 seconds
Started	Jul 12 07:09:22 PM PDT 24
Finished	Jul 12 07:24:49 PM PDT 24
Peak memory	262564 kb
Host	smart-bedfea6f-4e15-4fd3-8422-fb12f2115a63
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495389103 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.495389103
Directory	/workspace/1.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd.1629888154
Short name	T6
Test name
Test status
Simulation time	3559301600 ps
CPU time	226.23 seconds
Started	Jul 12 07:18:05 PM PDT 24
Finished	Jul 12 07:22:23 PM PDT 24
Peak memory	291012 kb
Host	smart-5c85fa03-c0e8-4bf4-939e-287fcb1ea0b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629888154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_intr_rd.1629888154
Directory	/workspace/16.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_cm.266110061
Short name	T16
Test name
Test status
Simulation time	4101469600 ps
CPU time	4916.14 seconds
Started	Jul 12 07:08:50 PM PDT 24
Finished	Jul 12 08:30:57 PM PDT 24
Peak memory	285820 kb
Host	smart-e6092c6c-2ff2-45fe-a72e-86478c174eff
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266110061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.266110061
Directory	/workspace/0.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1646051081
Short name	T94
Test name
Test status
Simulation time	102118500 ps
CPU time	19.09 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:43:49 PM PDT 24
Peak memory	271988 kb
Host	smart-999e5e36-787f-4c79-aa3b-fea2dbf2dcfd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646051081 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1646051081
Directory	/workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/31.flash_ctrl_otp_reset.1016472080
Short name	T10
Test name
Test status
Simulation time	584856600 ps
CPU time	131.89 seconds
Started	Jul 12 07:20:55 PM PDT 24
Finished	Jul 12 07:23:19 PM PDT 24
Peak memory	260120 kb
Host	smart-5711e068-cc89-4627-abf0-088f6d23eef8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016472080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o tp_reset.1016472080
Directory	/workspace/31.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_erase_suspend.4051421511
Short name	T136
Test name
Test status
Simulation time	30820544100 ps
CPU time	555.47 seconds
Started	Jul 12 07:09:23 PM PDT 24
Finished	Jul 12 07:18:48 PM PDT 24
Peak memory	263448 kb
Host	smart-6493734b-0a29-4a92-bb4e-cfdb2743749c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4051421511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.4051421511
Directory	/workspace/2.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/2.flash_ctrl_otp_reset.1538764410
Short name	T3
Test name
Test status
Simulation time	40492800 ps
CPU time	110.39 seconds
Started	Jul 12 07:09:23 PM PDT 24
Finished	Jul 12 07:11:23 PM PDT 24
Peak memory	259996 kb
Host	smart-ee53b4fe-39cd-44ec-84dd-33fdc56bfbd6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538764410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot p_reset.1538764410
Directory	/workspace/2.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_oversize_error.2674374653
Short name	T62
Test name
Test status
Simulation time	6291288200 ps
CPU time	225.99 seconds
Started	Jul 12 07:08:41 PM PDT 24
Finished	Jul 12 07:12:35 PM PDT 24
Peak memory	281800 kb
Host	smart-04b54926-3cdb-4821-91ba-da6f145ed998
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674374653 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.2674374653
Directory	/workspace/0.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mid_op_rst.4170007541
Short name	T81
Test name
Test status
Simulation time	3452967600 ps
CPU time	70.61 seconds
Started	Jul 12 07:12:03 PM PDT 24
Finished	Jul 12 07:14:14 PM PDT 24
Peak memory	260516 kb
Host	smart-547f0e7b-5fa0-4d77-8955-e069381932fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170007541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.4170007541
Directory	/workspace/4.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3521567467
Short name	T8
Test name
Test status
Simulation time	24538100 ps
CPU time	13.96 seconds
Started	Jul 12 07:09:14 PM PDT 24
Finished	Jul 12 07:09:35 PM PDT 24
Peak memory	265536 kb
Host	smart-a2a81bb1-2ac0-4f0f-aa5c-50093bfe4650
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521567467 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3521567467
Directory	/workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_otp_reset.319092850
Short name	T69
Test name
Test status
Simulation time	91172400 ps
CPU time	131.72 seconds
Started	Jul 12 07:10:30 PM PDT 24
Finished	Jul 12 07:12:50 PM PDT 24
Peak memory	261120 kb
Host	smart-11b5d281-04f1-4e9a-b154-c7b3a121f947
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319092850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp _reset.319092850
Directory	/workspace/3.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2131320799
Short name	T155
Test name
Test status
Simulation time	10012540600 ps
CPU time	123.91 seconds
Started	Jul 12 07:17:30 PM PDT 24
Finished	Jul 12 07:20:09 PM PDT 24
Peak memory	351240 kb
Host	smart-0e6f49ad-0329-464d-afc4-690bfda3e3c6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131320799 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.2131320799
Directory	/workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.14753244
Short name	T97
Test name
Test status
Simulation time	284162196800 ps
CPU time	2762.89 seconds
Started	Jul 12 07:08:34 PM PDT 24
Finished	Jul 12 07:54:43 PM PDT 24
Peak memory	264040 kb
Host	smart-44e93edd-fb56-4a27-8940-a3205f67d444
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14753244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST _SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.flash_ctrl_host_ctrl_arb.14753244
Directory	/workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_derr.3941901639
Short name	T51
Test name
Test status
Simulation time	2295111400 ps
CPU time	143.31 seconds
Started	Jul 12 07:12:37 PM PDT 24
Finished	Jul 12 07:15:39 PM PDT 24
Peak memory	281760 kb
Host	smart-40e73331-1d1f-4b0f-abb1-421994e0e4cd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3941901639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.3941901639
Directory	/workspace/5.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.202808943
Short name	T245
Test name
Test status
Simulation time	18354400 ps
CPU time	13.94 seconds
Started	Jul 12 06:43:34 PM PDT 24
Finished	Jul 12 06:43:51 PM PDT 24
Peak memory	261212 kb
Host	smart-e170d942-5c1f-40f7-ab1b-07ca5d3a0822
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202808943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.202808943
Directory	/workspace/26.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.1057335201
Short name	T227
Test name
Test status
Simulation time	1025855000 ps
CPU time	76.25 seconds
Started	Jul 12 07:12:30 PM PDT 24
Finished	Jul 12 07:14:29 PM PDT 24
Peak memory	261988 kb
Host	smart-a9083b57-09dd-4f20-9cf0-9bfc0a974df7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057335201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h w_sec_otp.1057335201
Directory	/workspace/5.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/33.flash_ctrl_sec_info_access.4198652019
Short name	T367
Test name
Test status
Simulation time	1446679100 ps
CPU time	69.23 seconds
Started	Jul 12 07:21:12 PM PDT 24
Finished	Jul 12 07:22:36 PM PDT 24
Peak memory	264896 kb
Host	smart-59a19cf1-9027-4ee7-8281-7c0e1ca6dd72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4198652019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.4198652019
Directory	/workspace/33.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3816650134
Short name	T92
Test name
Test status
Simulation time	112679500 ps
CPU time	19.12 seconds
Started	Jul 12 06:43:33 PM PDT 24
Finished	Jul 12 06:43:55 PM PDT 24
Peak memory	263676 kb
Host	smart-69c267a4-be1c-4a70-be41-b7f40ea7374d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816650134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors. 3816650134
Directory	/workspace/17.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.1193110094
Short name	T182
Test name
Test status
Simulation time	10012664000 ps
CPU time	310.53 seconds
Started	Jul 12 07:18:14 PM PDT 24
Finished	Jul 12 07:23:56 PM PDT 24
Peak memory	310612 kb
Host	smart-b96f7906-9c4e-4fa4-8f09-e9102b2d01a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193110094 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.1193110094
Directory	/workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/39.flash_ctrl_disable.2155992646
Short name	T15
Test name
Test status
Simulation time	21720300 ps
CPU time	20.93 seconds
Started	Jul 12 07:21:34 PM PDT 24
Finished	Jul 12 07:22:06 PM PDT 24
Peak memory	273608 kb
Host	smart-0d92dfc9-e113-419c-b613-424272c44b84
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155992646 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_disable.2155992646
Directory	/workspace/39.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fetch_code.1302577034
Short name	T47
Test name
Test status
Simulation time	459876700 ps
CPU time	26.4 seconds
Started	Jul 12 07:08:56 PM PDT 24
Finished	Jul 12 07:09:31 PM PDT 24
Peak memory	262500 kb
Host	smart-7ef0e951-a92f-483e-9ab3-f252323d5bfa
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302577034 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.1302577034
Directory	/workspace/1.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/23.flash_ctrl_otp_reset.553915721
Short name	T166
Test name
Test status
Simulation time	77994900 ps
CPU time	134.64 seconds
Started	Jul 12 07:19:46 PM PDT 24
Finished	Jul 12 07:22:18 PM PDT 24
Peak memory	261020 kb
Host	smart-7b3cfdbe-c079-499b-8c35-43dd25a61325
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553915721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_ot p_reset.553915721
Directory	/workspace/23.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_alert_test.3399580847
Short name	T419
Test name
Test status
Simulation time	49583200 ps
CPU time	13.76 seconds
Started	Jul 12 07:08:51 PM PDT 24
Finished	Jul 12 07:09:15 PM PDT 24
Peak memory	258280 kb
Host	smart-42d06619-4447-4c71-8944-c440c7e14251
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399580847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3 399580847
Directory	/workspace/0.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.flash_ctrl_otp_reset.1346014431
Short name	T1024
Test name
Test status
Simulation time	455957300 ps
CPU time	113.28 seconds
Started	Jul 12 07:21:21 PM PDT 24
Finished	Jul 12 07:23:27 PM PDT 24
Peak memory	261172 kb
Host	smart-8469eb18-6b04-46de-8a49-be6ae2506000
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346014431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o tp_reset.1346014431
Directory	/workspace/38.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_serr.621862950
Short name	T86
Test name
Test status
Simulation time	4011687300 ps
CPU time	631.17 seconds
Started	Jul 12 07:13:16 PM PDT 24
Finished	Jul 12 07:23:58 PM PDT 24
Peak memory	320856 kb
Host	smart-376b26e3-c1f0-4a78-bb06-f18c7e04064d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621862950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_se rr.621862950
Directory	/workspace/6.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mid_op_rst.1217652048
Short name	T174
Test name
Test status
Simulation time	4337458500 ps
CPU time	67.94 seconds
Started	Jul 12 07:09:33 PM PDT 24
Finished	Jul 12 07:10:47 PM PDT 24
Peak memory	260404 kb
Host	smart-be136353-8edc-4c55-a84a-e3598493c0d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217652048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.1217652048
Directory	/workspace/2.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/19.flash_ctrl_re_evict.3910460273
Short name	T266
Test name
Test status
Simulation time	137461400 ps
CPU time	34.83 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:20:09 PM PDT 24
Peak memory	275632 kb
Host	smart-ed27233d-1e37-4cce-8108-ac5c5ffd1d80
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910460273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_re_evict.3910460273
Directory	/workspace/19.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2978195787
Short name	T77
Test name
Test status
Simulation time	20706072400 ps
CPU time	303.14 seconds
Started	Jul 12 07:17:11 PM PDT 24
Finished	Jul 12 07:22:53 PM PDT 24
Peak memory	293188 kb
Host	smart-cb4542a7-3414-4710-8a5b-c361b6952fbf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978195787 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.2978195787
Directory	/workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/15.flash_ctrl_mp_regions.1612343812
Short name	T118
Test name
Test status
Simulation time	55708264600 ps
CPU time	402.16 seconds
Started	Jul 12 07:17:36 PM PDT 24
Finished	Jul 12 07:24:55 PM PDT 24
Peak memory	275172 kb
Host	smart-f89e1625-4f83-4102-86ba-5a98a75ee0a6
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612343812 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.1612343812
Directory	/workspace/15.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.4080719472
Short name	T149
Test name
Test status
Simulation time	46538200 ps
CPU time	13.92 seconds
Started	Jul 12 07:16:18 PM PDT 24
Finished	Jul 12 07:17:10 PM PDT 24
Peak memory	259932 kb
Host	smart-a0850a55-f644-46ed-a65c-c83fbc0e45b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080719472 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.4080719472
Directory	/workspace/11.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4153582424
Short name	T249
Test name
Test status
Simulation time	79046100 ps
CPU time	19.12 seconds
Started	Jul 12 06:43:32 PM PDT 24
Finished	Jul 12 06:43:54 PM PDT 24
Peak memory	263696 kb
Host	smart-317473d3-8aee-45c3-a44d-ad50c71dd061
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153582424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors. 4153582424
Directory	/workspace/14.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/16.flash_ctrl_invalid_op.2689712037
Short name	T143
Test name
Test status
Simulation time	6134830300 ps
CPU time	87.94 seconds
Started	Jul 12 07:18:04 PM PDT 24
Finished	Jul 12 07:20:05 PM PDT 24
Peak memory	260584 kb
Host	smart-e8ae428c-8856-45be-b63a-87a57081c619
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689712037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2 689712037
Directory	/workspace/16.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.889605065
Short name	T23
Test name
Test status
Simulation time	360387000 ps
CPU time	30.97 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:20:07 PM PDT 24
Peak memory	268520 kb
Host	smart-44eda0a8-c032-486b-917a-1de1b43cb2e2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889605065 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.889605065
Directory	/workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1860334475
Short name	T322
Test name
Test status
Simulation time	1502117200 ps
CPU time	754.84 seconds
Started	Jul 12 06:43:18 PM PDT 24
Finished	Jul 12 06:55:53 PM PDT 24
Peak memory	263824 kb
Host	smart-70c85b97-7d1e-419a-a5b3-f19416b9ea03
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860334475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl _tl_intg_err.1860334475
Directory	/workspace/7.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3045086458
Short name	T307
Test name
Test status
Simulation time	41371100 ps
CPU time	13.26 seconds
Started	Jul 12 06:43:21 PM PDT 24
Finished	Jul 12 06:43:35 PM PDT 24
Peak memory	261176 kb
Host	smart-5c4473ef-e858-4fc8-be12-36fb93a2f92f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045086458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.3 045086458
Directory	/workspace/9.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wr_intg.1716323868
Short name	T85
Test name
Test status
Simulation time	167286100 ps
CPU time	16.3 seconds
Started	Jul 12 07:10:00 PM PDT 24
Finished	Jul 12 07:10:23 PM PDT 24
Peak memory	260768 kb
Host	smart-43cb6e0b-a4cb-4cf2-af2d-a575e1d1f5f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716323868 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.1716323868
Directory	/workspace/2.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3410816759
Short name	T223
Test name
Test status
Simulation time	115864700 ps
CPU time	13.63 seconds
Started	Jul 12 06:43:02 PM PDT 24
Finished	Jul 12 06:43:19 PM PDT 24
Peak memory	262724 kb
Host	smart-0da7346d-ef57-4ce4-8667-1bd16a1bd6de
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410816759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_mem_partial_access.3410816759
Directory	/workspace/0.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd.1006424381
Short name	T313
Test name
Test status
Simulation time	2717902000 ps
CPU time	172.58 seconds
Started	Jul 12 07:21:03 PM PDT 24
Finished	Jul 12 07:24:10 PM PDT 24
Peak memory	291660 kb
Host	smart-209b2520-6043-4cee-a631-8ff4842a3fb5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006424381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla sh_ctrl_intr_rd.1006424381
Directory	/workspace/35.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_derr.125893751
Short name	T190
Test name
Test status
Simulation time	8346088800 ps
CPU time	660.25 seconds
Started	Jul 12 07:12:10 PM PDT 24
Finished	Jul 12 07:24:07 PM PDT 24
Peak memory	339792 kb
Host	smart-2331777f-a927-4a8e-aa83-084cf5bdbbc1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125893751 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.flash_ctrl_rw_derr.125893751
Directory	/workspace/4.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.2537949839
Short name	T146
Test name
Test status
Simulation time	53313500 ps
CPU time	13.42 seconds
Started	Jul 12 07:15:14 PM PDT 24
Finished	Jul 12 07:16:13 PM PDT 24
Peak memory	265412 kb
Host	smart-66f8f954-1d4a-462b-bea0-0e56d3a56969
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537949839 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.2537949839
Directory	/workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/44.flash_ctrl_sec_info_access.2523880244
Short name	T336
Test name
Test status
Simulation time	4978095400 ps
CPU time	86.28 seconds
Started	Jul 12 07:21:50 PM PDT 24
Finished	Jul 12 07:23:22 PM PDT 24
Peak memory	263492 kb
Host	smart-734e7716-5ee9-4998-8733-117344e6d25b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523880244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.2523880244
Directory	/workspace/44.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.399889981
Short name	T55
Test name
Test status
Simulation time	24754500 ps
CPU time	14.22 seconds
Started	Jul 12 07:10:10 PM PDT 24
Finished	Jul 12 07:10:43 PM PDT 24
Peak memory	277020 kb
Host	smart-ab1a57b3-35f4-4c14-a4c4-57b5629308ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=399889981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.399889981
Directory	/workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/55.flash_ctrl_otp_reset.2474626475
Short name	T448
Test name
Test status
Simulation time	141079200 ps
CPU time	136.09 seconds
Started	Jul 12 07:22:24 PM PDT 24
Finished	Jul 12 07:24:44 PM PDT 24
Peak memory	264220 kb
Host	smart-3bb55721-df7a-48ec-b5fa-999638e0e423
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474626475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o tp_reset.2474626475
Directory	/workspace/55.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb_redun.994909270
Short name	T115
Test name
Test status
Simulation time	656375100 ps
CPU time	19.34 seconds
Started	Jul 12 07:09:14 PM PDT 24
Finished	Jul 12 07:09:39 PM PDT 24
Peak memory	263376 kb
Host	smart-87195838-17e4-413f-908d-84b479dcea8e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994909270 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.994909270
Directory	/workspace/1.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/12.flash_ctrl_re_evict.2886198663
Short name	T200
Test name
Test status
Simulation time	52657100 ps
CPU time	34.14 seconds
Started	Jul 12 07:17:13 PM PDT 24
Finished	Jul 12 07:18:28 PM PDT 24
Peak memory	268468 kb
Host	smart-37242345-61ad-428e-9cf6-653c3d73e695
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886198663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_re_evict.2886198663
Directory	/workspace/12.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/65.flash_ctrl_connect.2214323181
Short name	T99
Test name
Test status
Simulation time	24104300 ps
CPU time	13.34 seconds
Started	Jul 12 07:22:32 PM PDT 24
Finished	Jul 12 07:22:50 PM PDT 24
Peak memory	274864 kb
Host	smart-42a37562-03f5-4705-b201-65bc052a8f0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2214323181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2214323181
Directory	/workspace/65.flash_ctrl_connect/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2109380411
Short name	T244
Test name
Test status
Simulation time	52629100 ps
CPU time	19.39 seconds
Started	Jul 12 06:43:17 PM PDT 24
Finished	Jul 12 06:43:38 PM PDT 24
Peak memory	263716 kb
Host	smart-9eb23c5e-3256-46aa-bf1c-413e79b79691
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109380411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2 109380411
Directory	/workspace/4.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd.2489067976
Short name	T31
Test name
Test status
Simulation time	868943300 ps
CPU time	124.6 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:21:41 PM PDT 24
Peak memory	293944 kb
Host	smart-87b20d64-3c9a-4be4-a102-3c2f469edf79
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489067976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla sh_ctrl_intr_rd.2489067976
Directory	/workspace/20.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2754914439
Short name	T327
Test name
Test status
Simulation time	4637877700 ps
CPU time	896.09 seconds
Started	Jul 12 06:43:20 PM PDT 24
Finished	Jul 12 06:58:18 PM PDT 24
Peak memory	263724 kb
Host	smart-e780a1ea-4bce-457c-a5de-f46bdf722263
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754914439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr l_tl_intg_err.2754914439
Directory	/workspace/10.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.743724297
Short name	T396
Test name
Test status
Simulation time	88348000 ps
CPU time	31.48 seconds
Started	Jul 12 07:17:28 PM PDT 24
Finished	Jul 12 07:18:37 PM PDT 24
Peak memory	275628 kb
Host	smart-a0b1d9a5-86b7-4fa8-9232-43b2963a63f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743724297 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.743724297
Directory	/workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_counter.2905965130
Short name	T799
Test name
Test status
Simulation time	1364304500 ps
CPU time	83.62 seconds
Started	Jul 12 07:09:50 PM PDT 24
Finished	Jul 12 07:11:22 PM PDT 24
Peak memory	274100 kb
Host	smart-e1952375-d33f-4c8a-b7c6-c7adb8213ad2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905965130 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_serr_counter.2905965130
Directory	/workspace/2.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_cm.527998275
Short name	T54
Test name
Test status
Simulation time	6940502600 ps
CPU time	4899.97 seconds
Started	Jul 12 07:09:16 PM PDT 24
Finished	Jul 12 08:31:06 PM PDT 24
Peak memory	288528 kb
Host	smart-995a330b-4512-472c-9116-5b8b23713a59
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527998275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.527998275
Directory	/workspace/1.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_type.1821001312
Short name	T76
Test name
Test status
Simulation time	981701900 ps
CPU time	3144.47 seconds
Started	Jul 12 07:08:35 PM PDT 24
Finished	Jul 12 08:01:05 PM PDT 24
Peak memory	262060 kb
Host	smart-c24ab502-bca9-4237-86ad-ca8d6421cefb
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821001312 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.1821001312
Directory	/workspace/0.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict.2220650175
Short name	T381
Test name
Test status
Simulation time	32309600 ps
CPU time	28.94 seconds
Started	Jul 12 07:15:52 PM PDT 24
Finished	Jul 12 07:17:03 PM PDT 24
Peak memory	274680 kb
Host	smart-7e423651-6dba-4af0-8cea-7157ba995f0c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220650175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_rw_evict.2220650175
Directory	/workspace/10.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fs_sup.251613895
Short name	T389
Test name
Test status
Simulation time	696626200 ps
CPU time	44.2 seconds
Started	Jul 12 07:11:54 PM PDT 24
Finished	Jul 12 07:13:43 PM PDT 24
Peak memory	263008 kb
Host	smart-e0977109-4bb2-452a-8d87-2210202353f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251613895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_fs_sup.251613895
Directory	/workspace/3.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.1022286697
Short name	T128
Test name
Test status
Simulation time	144550300 ps
CPU time	13.27 seconds
Started	Jul 12 07:08:49 PM PDT 24
Finished	Jul 12 07:09:12 PM PDT 24
Peak memory	265012 kb
Host	smart-04c212de-0266-4586-824a-dcf92366d4ef
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022286697 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.1022286697
Directory	/workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.165425025
Short name	T1061
Test name
Test status
Simulation time	10012429100 ps
CPU time	129.62 seconds
Started	Jul 12 07:09:27 PM PDT 24
Finished	Jul 12 07:11:45 PM PDT 24
Peak memory	323460 kb
Host	smart-057394e9-bbf1-48dd-bb9f-6802c598d6a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165425025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.165425025
Directory	/workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4047170631
Short name	T325
Test name
Test status
Simulation time	679291200 ps
CPU time	457.67 seconds
Started	Jul 12 06:43:49 PM PDT 24
Finished	Jul 12 06:51:34 PM PDT 24
Peak memory	263748 kb
Host	smart-5733279c-de17-4213-8f48-94b99ac72a5d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047170631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr l_tl_intg_err.4047170631
Directory	/workspace/14.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3591200067
Short name	T1145
Test name
Test status
Simulation time	25398600 ps
CPU time	13.62 seconds
Started	Jul 12 06:43:56 PM PDT 24
Finished	Jul 12 06:44:17 PM PDT 24
Peak memory	261096 kb
Host	smart-e89f91ec-7b90-48ff-86e0-83c9f5033abb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591200067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test. 3591200067
Directory	/workspace/48.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2179801807
Short name	T310
Test name
Test status
Simulation time	78028176400 ps
CPU time	518.63 seconds
Started	Jul 12 07:08:41 PM PDT 24
Finished	Jul 12 07:17:28 PM PDT 24
Peak memory	284820 kb
Host	smart-686e5bb9-c186-406e-83fa-49fee752a794
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179801807 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.2179801807
Directory	/workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_info_access.692982113
Short name	T365
Test name
Test status
Simulation time	466873800 ps
CPU time	62.37 seconds
Started	Jul 12 07:08:51 PM PDT 24
Finished	Jul 12 07:10:03 PM PDT 24
Peak memory	263616 kb
Host	smart-2f55f0d4-6715-4967-9156-7fc7267eade4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692982113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.692982113
Directory	/workspace/0.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd.3920420244
Short name	T211
Test name
Test status
Simulation time	681065000 ps
CPU time	136.02 seconds
Started	Jul 12 07:15:53 PM PDT 24
Finished	Jul 12 07:18:50 PM PDT 24
Peak memory	291456 kb
Host	smart-8f02feaf-ec82-45e2-93d1-b16cb9abfe75
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920420244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_intr_rd.3920420244
Directory	/workspace/10.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/12.flash_ctrl_sec_info_access.3225899061
Short name	T356
Test name
Test status
Simulation time	2352735800 ps
CPU time	84.49 seconds
Started	Jul 12 07:16:53 PM PDT 24
Finished	Jul 12 07:18:55 PM PDT 24
Peak memory	263688 kb
Host	smart-e7f73aa6-d597-46e8-96cb-3cfdd48fe1f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3225899061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.3225899061
Directory	/workspace/12.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/15.flash_ctrl_sec_info_access.398100713
Short name	T362
Test name
Test status
Simulation time	1729505700 ps
CPU time	74.76 seconds
Started	Jul 12 07:17:51 PM PDT 24
Finished	Jul 12 07:19:40 PM PDT 24
Peak memory	265040 kb
Host	smart-9ee10db0-bbd3-4580-9fcc-fa8c132e14fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398100713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.398100713
Directory	/workspace/15.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/36.flash_ctrl_sec_info_access.3261354238
Short name	T358
Test name
Test status
Simulation time	756727900 ps
CPU time	59.69 seconds
Started	Jul 12 07:21:10 PM PDT 24
Finished	Jul 12 07:22:25 PM PDT 24
Peak memory	263672 kb
Host	smart-4755df0b-ea16-4ae8-8c74-a5cd48c9610e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3261354238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.3261354238
Directory	/workspace/36.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/8.flash_ctrl_disable.2902134291
Short name	T132
Test name
Test status
Simulation time	23375400 ps
CPU time	21.82 seconds
Started	Jul 12 07:15:24 PM PDT 24
Finished	Jul 12 07:16:32 PM PDT 24
Peak memory	273560 kb
Host	smart-5fa759d7-e2f1-4be2-8093-997a83ac2a3f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902134291 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_disable.2902134291
Directory	/workspace/8.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.3666068694
Short name	T112
Test name
Test status
Simulation time	856265000 ps
CPU time	18.03 seconds
Started	Jul 12 07:11:56 PM PDT 24
Finished	Jul 12 07:13:19 PM PDT 24
Peak memory	264316 kb
Host	smart-14179688-42f3-4f92-9ee6-c4378705ff0c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666068694 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3666068694
Directory	/workspace/3.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/0.flash_ctrl_access_after_disable.3970665360
Short name	T22
Test name
Test status
Simulation time	12312200 ps
CPU time	13.72 seconds
Started	Jul 12 07:08:53 PM PDT 24
Finished	Jul 12 07:09:17 PM PDT 24
Peak memory	265444 kb
Host	smart-c2b98070-7206-4ff2-b501-64278993e094
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970665360 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3970665360
Directory	/workspace/0.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.3302993673
Short name	T257
Test name
Test status
Simulation time	1476904300 ps
CPU time	115.95 seconds
Started	Jul 12 07:08:52 PM PDT 24
Finished	Jul 12 07:10:58 PM PDT 24
Peak memory	262852 kb
Host	smart-8e965e3a-6f3c-4b3a-bab1-3058abae62eb
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3302993673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3302993673
Directory	/workspace/1.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_disable.2505621191
Short name	T342
Test name
Test status
Simulation time	15453700 ps
CPU time	20.5 seconds
Started	Jul 12 07:17:11 PM PDT 24
Finished	Jul 12 07:18:11 PM PDT 24
Peak memory	273796 kb
Host	smart-0ab29762-969d-43cb-aa2c-be5834a29a4c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505621191 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_disable.2505621191
Directory	/workspace/13.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_config_regwen.3301624058
Short name	T335
Test name
Test status
Simulation time	35584000 ps
CPU time	13.68 seconds
Started	Jul 12 07:10:19 PM PDT 24
Finished	Jul 12 07:10:46 PM PDT 24
Peak memory	261536 kb
Host	smart-a04c77f3-0b35-413b-ac4b-311e55c3f76e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301624058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .flash_ctrl_config_regwen.3301624058
Directory	/workspace/2.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/3.flash_ctrl_invalid_op.1652114839
Short name	T377
Test name
Test status
Simulation time	12142859800 ps
CPU time	100.45 seconds
Started	Jul 12 07:10:37 PM PDT 24
Finished	Jul 12 07:12:23 PM PDT 24
Peak memory	260872 kb
Host	smart-e6a75c73-3199-4846-ac24-5d9849256110
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652114839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.1652114839
Directory	/workspace/3.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_sec_otp.1778242062
Short name	T295
Test name
Test status
Simulation time	27114500000 ps
CPU time	162.05 seconds
Started	Jul 12 07:08:53 PM PDT 24
Finished	Jul 12 07:11:45 PM PDT 24
Peak memory	263352 kb
Host	smart-0faf5a9e-c739-4869-bb0c-3e5cd88885a4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778242062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h w_sec_otp.1778242062
Directory	/workspace/1.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.548053716
Short name	T116
Test name
Test status
Simulation time	793696900 ps
CPU time	18.49 seconds
Started	Jul 12 07:12:21 PM PDT 24
Finished	Jul 12 07:13:26 PM PDT 24
Peak memory	265472 kb
Host	smart-45b2fdf9-3f91-4293-9ed1-3edb26a61fdd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548053716 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.548053716
Directory	/workspace/4.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/10.flash_ctrl_lcmgr_intg.218332458
Short name	T462
Test name
Test status
Simulation time	25622100 ps
CPU time	13.67 seconds
Started	Jul 12 07:15:51 PM PDT 24
Finished	Jul 12 07:16:47 PM PDT 24
Peak memory	259948 kb
Host	smart-9aed6c38-1358-44c9-b4cd-191eff63e0d3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218332458 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.218332458
Directory	/workspace/10.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.612810882
Short name	T333
Test name
Test status
Simulation time	351406500 ps
CPU time	458.13 seconds
Started	Jul 12 06:43:27 PM PDT 24
Finished	Jul 12 06:51:06 PM PDT 24
Peak memory	263756 kb
Host	smart-1c07360a-b852-4029-b612-f16b77e30078
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612810882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ tl_intg_err.612810882
Directory	/workspace/1.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3467464149
Short name	T241
Test name
Test status
Simulation time	3992605400 ps
CPU time	929.33 seconds
Started	Jul 12 06:43:43 PM PDT 24
Finished	Jul 12 06:59:19 PM PDT 24
Peak memory	263736 kb
Host	smart-4be6d434-9c9a-4a96-b7a0-9a57a40534cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467464149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr l_tl_intg_err.3467464149
Directory	/workspace/15.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_disable.4181910958
Short name	T859
Test name
Test status
Simulation time	10327500 ps
CPU time	21.78 seconds
Started	Jul 12 07:15:53 PM PDT 24
Finished	Jul 12 07:16:56 PM PDT 24
Peak memory	273600 kb
Host	smart-63eb8927-6b26-44bf-82f5-ec1aeef1c5ad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181910958 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_disable.4181910958
Directory	/workspace/10.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.2104460804
Short name	T397
Test name
Test status
Simulation time	88315100 ps
CPU time	31.38 seconds
Started	Jul 12 07:16:52 PM PDT 24
Finished	Jul 12 07:18:02 PM PDT 24
Peak memory	275712 kb
Host	smart-6d90903e-b9d5-4a40-ab8f-9bc770ccd421
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104460804 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.2104460804
Directory	/workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/15.flash_ctrl_disable.3363174725
Short name	T587
Test name
Test status
Simulation time	24017100 ps
CPU time	20.39 seconds
Started	Jul 12 07:17:51 PM PDT 24
Finished	Jul 12 07:18:46 PM PDT 24
Peak memory	273592 kb
Host	smart-d57971bc-11e1-409c-8640-6a79631ef20c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363174725 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_disable.3363174725
Directory	/workspace/15.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/17.flash_ctrl_sec_info_access.2419661666
Short name	T354
Test name
Test status
Simulation time	589399500 ps
CPU time	64.57 seconds
Started	Jul 12 07:18:32 PM PDT 24
Finished	Jul 12 07:20:04 PM PDT 24
Peak memory	263700 kb
Host	smart-48e67b9a-41c4-456d-930f-d231cea15021
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2419661666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.2419661666
Directory	/workspace/17.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/32.flash_ctrl_disable.991769684
Short name	T804
Test name
Test status
Simulation time	16640300 ps
CPU time	22.05 seconds
Started	Jul 12 07:21:19 PM PDT 24
Finished	Jul 12 07:21:54 PM PDT 24
Peak memory	265536 kb
Host	smart-88bcbe60-180f-47d6-b160-705c65b4b314
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991769684 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_disable.991769684
Directory	/workspace/32.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/33.flash_ctrl_disable.335787090
Short name	T42
Test name
Test status
Simulation time	27149200 ps
CPU time	21.47 seconds
Started	Jul 12 07:21:07 PM PDT 24
Finished	Jul 12 07:21:43 PM PDT 24
Peak memory	273604 kb
Host	smart-cbfa773a-569a-4252-b2c2-9fc438886e77
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335787090 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_disable.335787090
Directory	/workspace/33.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/34.flash_ctrl_otp_reset.3712419625
Short name	T348
Test name
Test status
Simulation time	96180700 ps
CPU time	111.54 seconds
Started	Jul 12 07:21:10 PM PDT 24
Finished	Jul 12 07:23:16 PM PDT 24
Peak memory	260168 kb
Host	smart-3fc8083a-0025-4fd7-83cc-f42bc7740828
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712419625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o tp_reset.3712419625
Directory	/workspace/34.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2341902739
Short name	T1255
Test name
Test status
Simulation time	228856800 ps
CPU time	20.33 seconds
Started	Jul 12 06:43:37 PM PDT 24
Finished	Jul 12 06:44:01 PM PDT 24
Peak memory	263720 kb
Host	smart-b790127a-0ee0-45da-bbe9-2edee92b551a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341902739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors. 2341902739
Directory	/workspace/13.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr.64745999
Short name	T26
Test name
Test status
Simulation time	16884296400 ps
CPU time	65.9 seconds
Started	Jul 12 07:08:41 PM PDT 24
Finished	Jul 12 07:09:55 PM PDT 24
Peak memory	261024 kb
Host	smart-886ef312-185e-4c04-b374-98603e76c84e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64745999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U VM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.flash_ctrl_intr_wr.64745999
Directory	/workspace/0.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb_redun.4123016694
Short name	T114
Test name
Test status
Simulation time	865806800 ps
CPU time	18.83 seconds
Started	Jul 12 07:10:10 PM PDT 24
Finished	Jul 12 07:10:47 PM PDT 24
Peak memory	265404 kb
Host	smart-5bb910bb-d96a-4f34-8d85-8e9312282f16
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123016694 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.4123016694
Directory	/workspace/2.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.1555991947
Short name	T214
Test name
Test status
Simulation time	48917000 ps
CPU time	15.04 seconds
Started	Jul 12 07:08:51 PM PDT 24
Finished	Jul 12 07:09:16 PM PDT 24
Peak memory	265048 kb
Host	smart-af2699e1-3473-402a-8609-8617fbcab82b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1555991947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.1555991947
Directory	/workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/3.flash_ctrl_full_mem_access.2144481590
Short name	T33
Test name
Test status
Simulation time	1564757090400 ps
CPU time	3240.58 seconds
Started	Jul 12 07:10:29 PM PDT 24
Finished	Jul 12 08:04:38 PM PDT 24
Peak memory	265200 kb
Host	smart-c3088fba-7665-4d0f-9e4a-86050df3d243
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144481590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_full_mem_access.2144481590
Directory	/workspace/3.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.3743931961
Short name	T14
Test name
Test status
Simulation time	77996900 ps
CPU time	13.93 seconds
Started	Jul 12 07:12:22 PM PDT 24
Finished	Jul 12 07:13:24 PM PDT 24
Peak memory	265012 kb
Host	smart-4cbe4353-593d-4295-87f9-0b01d1e14efe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743931961 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.3743931961
Directory	/workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_mp.3223480073
Short name	T274
Test name
Test status
Simulation time	10523786500 ps
CPU time	2460.95 seconds
Started	Jul 12 07:08:38 PM PDT 24
Finished	Jul 12 07:49:46 PM PDT 24
Peak memory	262864 kb
Host	smart-d122075c-2a9a-454d-bac4-830ded27df83
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3223480073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.3223480073
Directory	/workspace/0.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_win.1163031549
Short name	T275
Test name
Test status
Simulation time	427823300 ps
CPU time	1088.74 seconds
Started	Jul 12 07:08:35 PM PDT 24
Finished	Jul 12 07:26:49 PM PDT 24
Peak memory	273112 kb
Host	smart-a1293da8-c771-46b1-b860-6664fa12ece1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163031549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1163031549
Directory	/workspace/0.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb_redun.60722498
Short name	T113
Test name
Test status
Simulation time	716724200 ps
CPU time	16.47 seconds
Started	Jul 12 07:08:49 PM PDT 24
Finished	Jul 12 07:09:15 PM PDT 24
Peak memory	263032 kb
Host	smart-3f686ec3-0ca3-4d4f-a069-9b9231786f02
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60722498 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.60722498
Directory	/workspace/0.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.2068829258
Short name	T194
Test name
Test status
Simulation time	546842039200 ps
CPU time	2422.06 seconds
Started	Jul 12 07:08:53 PM PDT 24
Finished	Jul 12 07:49:26 PM PDT 24
Peak memory	265208 kb
Host	smart-6a95e114-72c9-4974-b1d2-5088b03ffc6e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068829258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.flash_ctrl_host_ctrl_arb.2068829258
Directory	/workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.2676076838
Short name	T96
Test name
Test status
Simulation time	1239233034000 ps
CPU time	2106.16 seconds
Started	Jul 12 07:10:30 PM PDT 24
Finished	Jul 12 07:45:45 PM PDT 24
Peak memory	264148 kb
Host	smart-35fef165-3b80-47fc-92fb-86d057dedd12
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676076838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.flash_ctrl_host_ctrl_arb.2676076838
Directory	/workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3017923945
Short name	T1251
Test name
Test status
Simulation time	2549204200 ps
CPU time	37.29 seconds
Started	Jul 12 06:43:08 PM PDT 24
Finished	Jul 12 06:43:50 PM PDT 24
Peak memory	261180 kb
Host	smart-3295f368-db6a-4bfe-b37c-9a1ebce3fd78
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017923945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_aliasing.3017923945
Directory	/workspace/0.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1631078238
Short name	T1232
Test name
Test status
Simulation time	4943553700 ps
CPU time	48.54 seconds
Started	Jul 12 06:43:05 PM PDT 24
Finished	Jul 12 06:43:57 PM PDT 24
Peak memory	261372 kb
Host	smart-865140d9-e5f6-450d-a55e-f7d9c9bff2ef
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631078238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_bit_bash.1631078238
Directory	/workspace/0.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4167863539
Short name	T243
Test name
Test status
Simulation time	785746400 ps
CPU time	38.88 seconds
Started	Jul 12 06:43:22 PM PDT 24
Finished	Jul 12 06:44:01 PM PDT 24
Peak memory	261232 kb
Host	smart-89768f98-d279-49cd-9b2f-170d06ed2f46
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167863539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_hw_reset.4167863539
Directory	/workspace/0.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3108010899
Short name	T283
Test name
Test status
Simulation time	530109300 ps
CPU time	19.42 seconds
Started	Jul 12 06:43:25 PM PDT 24
Finished	Jul 12 06:43:46 PM PDT 24
Peak memory	270740 kb
Host	smart-0bcac9e1-566b-45ce-a203-c9bc2807c932
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108010899 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3108010899
Directory	/workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1542347669
Short name	T279
Test name
Test status
Simulation time	259195200 ps
CPU time	17.55 seconds
Started	Jul 12 06:43:06 PM PDT 24
Finished	Jul 12 06:43:27 PM PDT 24
Peak memory	263688 kb
Host	smart-2373533c-8267-46cf-8f81-c359a5aaf241
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542347669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_csr_rw.1542347669
Directory	/workspace/0.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3256587460
Short name	T1169
Test name
Test status
Simulation time	50380900 ps
CPU time	14.13 seconds
Started	Jul 12 06:43:10 PM PDT 24
Finished	Jul 12 06:43:28 PM PDT 24
Peak memory	261124 kb
Host	smart-7afbd3c9-5918-4176-9596-02ad9e03e55c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256587460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3 256587460
Directory	/workspace/0.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.804161986
Short name	T1139
Test name
Test status
Simulation time	90799900 ps
CPU time	13.57 seconds
Started	Jul 12 06:43:09 PM PDT 24
Finished	Jul 12 06:43:27 PM PDT 24
Peak memory	261120 kb
Host	smart-60913bf2-8c7d-4ba1-b87d-2213569e5df5
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804161986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem _walk.804161986
Directory	/workspace/0.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1582974492
Short name	T1159
Test name
Test status
Simulation time	344313600 ps
CPU time	16.14 seconds
Started	Jul 12 06:43:09 PM PDT 24
Finished	Jul 12 06:43:29 PM PDT 24
Peak memory	262404 kb
Host	smart-6225289c-ebf5-41da-99fb-09d68da9dbac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582974492 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.1582974492
Directory	/workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1759431705
Short name	T1140
Test name
Test status
Simulation time	25513300 ps
CPU time	13.29 seconds
Started	Jul 12 06:43:02 PM PDT 24
Finished	Jul 12 06:43:19 PM PDT 24
Peak memory	252992 kb
Host	smart-ff525eda-1883-43a9-95ae-9f86cd491b59
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759431705 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.1759431705
Directory	/workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2829449515
Short name	T1235
Test name
Test status
Simulation time	19219800 ps
CPU time	13.35 seconds
Started	Jul 12 06:43:17 PM PDT 24
Finished	Jul 12 06:43:32 PM PDT 24
Peak memory	253016 kb
Host	smart-e703cbb8-d0e5-4381-b5ab-2c1b66eb8733
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829449515 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.2829449515
Directory	/workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.786011723
Short name	T1254
Test name
Test status
Simulation time	164027300 ps
CPU time	15.56 seconds
Started	Jul 12 06:43:15 PM PDT 24
Finished	Jul 12 06:43:32 PM PDT 24
Peak memory	263704 kb
Host	smart-723e8125-7133-4544-9da5-6a2ce8777846
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786011723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.786011723
Directory	/workspace/0.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3893045010
Short name	T1245
Test name
Test status
Simulation time	5269551100 ps
CPU time	756.94 seconds
Started	Jul 12 06:43:22 PM PDT 24
Finished	Jul 12 06:55:59 PM PDT 24
Peak memory	263744 kb
Host	smart-84f40497-e4c9-4000-a673-893e4631f087
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893045010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl _tl_intg_err.3893045010
Directory	/workspace/0.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3080103922
Short name	T1233
Test name
Test status
Simulation time	8983080600 ps
CPU time	65.97 seconds
Started	Jul 12 06:43:20 PM PDT 24
Finished	Jul 12 06:44:27 PM PDT 24
Peak memory	261296 kb
Host	smart-cd7e881e-d605-41e3-a2ae-cfa009ccd195
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080103922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_aliasing.3080103922
Directory	/workspace/1.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3208458451
Short name	T1118
Test name
Test status
Simulation time	2366377000 ps
CPU time	75.23 seconds
Started	Jul 12 06:43:10 PM PDT 24
Finished	Jul 12 06:44:29 PM PDT 24
Peak memory	261388 kb
Host	smart-2d304f3a-4096-4410-9ff3-435c91e38e20
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208458451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_bit_bash.3208458451
Directory	/workspace/1.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.154716307
Short name	T1259
Test name
Test status
Simulation time	57986800 ps
CPU time	30.46 seconds
Started	Jul 12 06:43:23 PM PDT 24
Finished	Jul 12 06:43:55 PM PDT 24
Peak memory	261288 kb
Host	smart-43282875-f0ac-4285-9c44-a3a58cf9ed36
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154716307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.flash_ctrl_csr_hw_reset.154716307
Directory	/workspace/1.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.951060714
Short name	T1257
Test name
Test status
Simulation time	217289500 ps
CPU time	17.75 seconds
Started	Jul 12 06:43:27 PM PDT 24
Finished	Jul 12 06:43:46 PM PDT 24
Peak memory	263052 kb
Host	smart-f1cb57f7-544c-4f8f-988e-857fcaf29f65
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951060714 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.951060714
Directory	/workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2672949053
Short name	T1230
Test name
Test status
Simulation time	75346400 ps
CPU time	16.65 seconds
Started	Jul 12 06:43:24 PM PDT 24
Finished	Jul 12 06:43:42 PM PDT 24
Peak memory	261340 kb
Host	smart-4d0e4c0a-8e83-45de-b2bb-07d9cfcc50f4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672949053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_csr_rw.2672949053
Directory	/workspace/1.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1910234920
Short name	T1213
Test name
Test status
Simulation time	71006200 ps
CPU time	13.53 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:43:44 PM PDT 24
Peak memory	261184 kb
Host	smart-310c2c6a-4bce-4e86-b4c9-b7ba573c3e55
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910234920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.1 910234920
Directory	/workspace/1.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1411240341
Short name	T225
Test name
Test status
Simulation time	52377100 ps
CPU time	13.82 seconds
Started	Jul 12 06:43:23 PM PDT 24
Finished	Jul 12 06:43:39 PM PDT 24
Peak memory	262048 kb
Host	smart-30e2e46f-6d44-4ae8-ab92-2eae8abc3d2c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411240341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_mem_partial_access.1411240341
Directory	/workspace/1.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1314143476
Short name	T1197
Test name
Test status
Simulation time	77612200 ps
CPU time	13.69 seconds
Started	Jul 12 06:43:24 PM PDT 24
Finished	Jul 12 06:43:39 PM PDT 24
Peak memory	261156 kb
Host	smart-40299bf5-75bc-45eb-8220-a3736bff08c3
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314143476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me m_walk.1314143476
Directory	/workspace/1.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2980169221
Short name	T1207
Test name
Test status
Simulation time	656450100 ps
CPU time	18.98 seconds
Started	Jul 12 06:43:18 PM PDT 24
Finished	Jul 12 06:43:37 PM PDT 24
Peak memory	261268 kb
Host	smart-9ac5f236-c6f8-449d-8be3-e93442fa5932
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980169221 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.2980169221
Directory	/workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.780664168
Short name	T1114
Test name
Test status
Simulation time	11614000 ps
CPU time	15.8 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:43:46 PM PDT 24
Peak memory	253024 kb
Host	smart-d7ec47e7-3061-466d-85fc-f9e503953b62
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780664168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.780664168
Directory	/workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3904359265
Short name	T1196
Test name
Test status
Simulation time	14784500 ps
CPU time	13.16 seconds
Started	Jul 12 06:43:27 PM PDT 24
Finished	Jul 12 06:43:41 PM PDT 24
Peak memory	252964 kb
Host	smart-2a0fbd8c-c2f9-46bb-bbb3-dd90b85bb7f2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904359265 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.3904359265
Directory	/workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3431492412
Short name	T1175
Test name
Test status
Simulation time	126883200 ps
CPU time	15.93 seconds
Started	Jul 12 06:43:06 PM PDT 24
Finished	Jul 12 06:43:26 PM PDT 24
Peak memory	263724 kb
Host	smart-71f64077-ba0c-4487-812a-5224ed6b1c4b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431492412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3 431492412
Directory	/workspace/1.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3320767434
Short name	T220
Test name
Test status
Simulation time	39254600 ps
CPU time	16.97 seconds
Started	Jul 12 06:43:21 PM PDT 24
Finished	Jul 12 06:43:50 PM PDT 24
Peak memory	271148 kb
Host	smart-928bef23-a638-4d7d-9173-03ba7d230a4f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320767434 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3320767434
Directory	/workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4141657923
Short name	T285
Test name
Test status
Simulation time	68796000 ps
CPU time	16.58 seconds
Started	Jul 12 06:43:26 PM PDT 24
Finished	Jul 12 06:43:44 PM PDT 24
Peak memory	263636 kb
Host	smart-d791324e-b8e5-4804-9f99-84eaa67d33df
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141657923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_csr_rw.4141657923
Directory	/workspace/10.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3144689241
Short name	T1215
Test name
Test status
Simulation time	18684400 ps
CPU time	14.29 seconds
Started	Jul 12 06:43:30 PM PDT 24
Finished	Jul 12 06:43:47 PM PDT 24
Peak memory	261036 kb
Host	smart-f2810328-d9e4-40d0-a5c0-5232da8713da
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144689241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test. 3144689241
Directory	/workspace/10.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1194347546
Short name	T1193
Test name
Test status
Simulation time	804754200 ps
CPU time	30.14 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:44:01 PM PDT 24
Peak memory	263452 kb
Host	smart-b29e8ee0-9614-4840-908d-ef11e5af2668
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194347546 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.1194347546
Directory	/workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2941257685
Short name	T1116
Test name
Test status
Simulation time	35461000 ps
CPU time	15.57 seconds
Started	Jul 12 06:43:23 PM PDT 24
Finished	Jul 12 06:43:39 PM PDT 24
Peak memory	252984 kb
Host	smart-5ec803a7-c3b1-4881-bfc9-db117afc113a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941257685 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.2941257685
Directory	/workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2021332331
Short name	T1244
Test name
Test status
Simulation time	13397000 ps
CPU time	15.5 seconds
Started	Jul 12 06:43:27 PM PDT 24
Finished	Jul 12 06:43:45 PM PDT 24
Peak memory	253068 kb
Host	smart-ddf4a415-abe0-4b13-aee5-d1720d89090a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021332331 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.2021332331
Directory	/workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1405462915
Short name	T1198
Test name
Test status
Simulation time	476550500 ps
CPU time	17.19 seconds
Started	Jul 12 06:43:29 PM PDT 24
Finished	Jul 12 06:43:48 PM PDT 24
Peak memory	263888 kb
Host	smart-84c195d7-cc47-4e1f-a786-2fa7fa3f92ba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405462915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors. 1405462915
Directory	/workspace/10.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.504457292
Short name	T1171
Test name
Test status
Simulation time	318898200 ps
CPU time	19.04 seconds
Started	Jul 12 06:43:30 PM PDT 24
Finished	Jul 12 06:43:52 PM PDT 24
Peak memory	271356 kb
Host	smart-79e2e55e-5122-42ca-8518-d2f8ba9c3f11
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504457292 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.504457292
Directory	/workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1735538611
Short name	T1178
Test name
Test status
Simulation time	65528200 ps
CPU time	14.21 seconds
Started	Jul 12 06:43:33 PM PDT 24
Finished	Jul 12 06:43:50 PM PDT 24
Peak memory	261268 kb
Host	smart-586db6e3-a03d-495f-afb5-398eaf9b5fb5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735538611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_csr_rw.1735538611
Directory	/workspace/11.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.771576577
Short name	T1248
Test name
Test status
Simulation time	31044800 ps
CPU time	13.35 seconds
Started	Jul 12 06:43:30 PM PDT 24
Finished	Jul 12 06:43:46 PM PDT 24
Peak memory	261224 kb
Host	smart-6d07fb06-8ce3-4356-aecb-915fb6beaaf2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771576577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.771576577
Directory	/workspace/11.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1410587312
Short name	T1126
Test name
Test status
Simulation time	489951500 ps
CPU time	36.03 seconds
Started	Jul 12 06:43:25 PM PDT 24
Finished	Jul 12 06:44:02 PM PDT 24
Peak memory	263716 kb
Host	smart-d62a72ee-c572-4835-b1e6-a881c99065be
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410587312 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.1410587312
Directory	/workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.697234425
Short name	T1188
Test name
Test status
Simulation time	28814300 ps
CPU time	15.49 seconds
Started	Jul 12 06:43:26 PM PDT 24
Finished	Jul 12 06:43:43 PM PDT 24
Peak memory	253164 kb
Host	smart-70c2277b-72b0-4924-89f3-c4706fb40f27
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697234425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.697234425
Directory	/workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.157141719
Short name	T1202
Test name
Test status
Simulation time	53790000 ps
CPU time	15.79 seconds
Started	Jul 12 06:43:20 PM PDT 24
Finished	Jul 12 06:43:38 PM PDT 24
Peak memory	253028 kb
Host	smart-fead7537-18fe-4156-a327-429183fdd17b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157141719 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.157141719
Directory	/workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3972178455
Short name	T218
Test name
Test status
Simulation time	55139500 ps
CPU time	18.33 seconds
Started	Jul 12 06:43:30 PM PDT 24
Finished	Jul 12 06:43:50 PM PDT 24
Peak memory	263888 kb
Host	smart-2be3391f-852f-43f7-84fd-69ee3692c8e8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972178455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors. 3972178455
Directory	/workspace/11.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3423192649
Short name	T1190
Test name
Test status
Simulation time	111945200 ps
CPU time	17.65 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:43:48 PM PDT 24
Peak memory	271168 kb
Host	smart-064334cb-8309-40dd-b3e8-1425dda6d5cb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423192649 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.3423192649
Directory	/workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2120184526
Short name	T1172
Test name
Test status
Simulation time	81015100 ps
CPU time	14.08 seconds
Started	Jul 12 06:43:32 PM PDT 24
Finished	Jul 12 06:43:48 PM PDT 24
Peak memory	263688 kb
Host	smart-cc33fb6d-f27b-49ce-946f-22933c7ce940
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120184526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_csr_rw.2120184526
Directory	/workspace/12.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.753715328
Short name	T1180
Test name
Test status
Simulation time	43782600 ps
CPU time	14.07 seconds
Started	Jul 12 06:43:46 PM PDT 24
Finished	Jul 12 06:44:07 PM PDT 24
Peak memory	261180 kb
Host	smart-17561c95-f7b7-4612-86de-81912b5ba182
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753715328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.753715328
Directory	/workspace/12.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3150484294
Short name	T282
Test name
Test status
Simulation time	101309300 ps
CPU time	15.67 seconds
Started	Jul 12 06:43:27 PM PDT 24
Finished	Jul 12 06:43:45 PM PDT 24
Peak memory	261808 kb
Host	smart-8be173bf-dbfd-40db-8eb5-081467ccf5a4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150484294 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.3150484294
Directory	/workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.694374250
Short name	T1133
Test name
Test status
Simulation time	15462600 ps
CPU time	15.46 seconds
Started	Jul 12 06:43:49 PM PDT 24
Finished	Jul 12 06:44:12 PM PDT 24
Peak memory	252988 kb
Host	smart-0fd7f71d-6c60-4a84-8d38-8262e73e0ab8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694374250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.694374250
Directory	/workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1805002711
Short name	T1130
Test name
Test status
Simulation time	17846800 ps
CPU time	16.42 seconds
Started	Jul 12 06:43:29 PM PDT 24
Finished	Jul 12 06:43:47 PM PDT 24
Peak memory	252900 kb
Host	smart-b56d5da6-4240-4f80-a305-73947e38b617
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805002711 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.1805002711
Directory	/workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1593108124
Short name	T252
Test name
Test status
Simulation time	64230800 ps
CPU time	20.09 seconds
Started	Jul 12 06:43:24 PM PDT 24
Finished	Jul 12 06:43:45 PM PDT 24
Peak memory	263724 kb
Host	smart-896b1948-279f-4e0f-9c32-bf4dd6c53683
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593108124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors. 1593108124
Directory	/workspace/12.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3172321894
Short name	T253
Test name
Test status
Simulation time	1408977200 ps
CPU time	385.05 seconds
Started	Jul 12 06:43:29 PM PDT 24
Finished	Jul 12 06:49:57 PM PDT 24
Peak memory	263728 kb
Host	smart-520000b8-c738-4add-bec2-f6533f624516
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172321894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr l_tl_intg_err.3172321894
Directory	/workspace/12.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3544516303
Short name	T1217
Test name
Test status
Simulation time	341397800 ps
CPU time	19.37 seconds
Started	Jul 12 06:43:34 PM PDT 24
Finished	Jul 12 06:43:55 PM PDT 24
Peak memory	271588 kb
Host	smart-c66bbcae-8aad-4f91-8def-86087841ec47
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544516303 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.3544516303
Directory	/workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1235728498
Short name	T1246
Test name
Test status
Simulation time	180903700 ps
CPU time	14.3 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:43:45 PM PDT 24
Peak memory	263708 kb
Host	smart-3d52eea1-6f75-4808-a2b8-fda1323081f2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235728498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 13.flash_ctrl_csr_rw.1235728498
Directory	/workspace/13.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2401573529
Short name	T246
Test name
Test status
Simulation time	52364800 ps
CPU time	13.26 seconds
Started	Jul 12 06:43:31 PM PDT 24
Finished	Jul 12 06:43:51 PM PDT 24
Peak memory	261220 kb
Host	smart-71f68fff-b277-4f9c-b772-0b1810930836
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401573529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test. 2401573529
Directory	/workspace/13.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.306545419
Short name	T280
Test name
Test status
Simulation time	443448700 ps
CPU time	18.22 seconds
Started	Jul 12 06:43:32 PM PDT 24
Finished	Jul 12 06:43:53 PM PDT 24
Peak memory	262576 kb
Host	smart-679c5ff1-7dd4-4666-b251-db8ca25a7dc6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306545419 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.306545419
Directory	/workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3216981985
Short name	T1170
Test name
Test status
Simulation time	11931200 ps
CPU time	15.84 seconds
Started	Jul 12 06:43:47 PM PDT 24
Finished	Jul 12 06:44:09 PM PDT 24
Peak memory	253172 kb
Host	smart-70c337ee-ce60-428f-9e37-e11df0acea16
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216981985 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.3216981985
Directory	/workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.278208017
Short name	T1225
Test name
Test status
Simulation time	18471300 ps
CPU time	15.7 seconds
Started	Jul 12 06:43:39 PM PDT 24
Finished	Jul 12 06:43:59 PM PDT 24
Peak memory	253016 kb
Host	smart-45f2bc3b-5ccc-4f15-88cf-4d27c1d4009a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278208017 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.278208017
Directory	/workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3494193406
Short name	T93
Test name
Test status
Simulation time	2042037900 ps
CPU time	755.78 seconds
Started	Jul 12 06:43:38 PM PDT 24
Finished	Jul 12 06:56:19 PM PDT 24
Peak memory	263744 kb
Host	smart-3be9c249-4ff6-4a82-939d-0c1e95290bac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494193406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr l_tl_intg_err.3494193406
Directory	/workspace/13.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1231711019
Short name	T1174
Test name
Test status
Simulation time	129160700 ps
CPU time	19.97 seconds
Started	Jul 12 06:50:42 PM PDT 24
Finished	Jul 12 06:51:03 PM PDT 24
Peak memory	272000 kb
Host	smart-45b91e47-ece3-40a9-9129-e4b7d125899d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231711019 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.1231711019
Directory	/workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3760244272
Short name	T1236
Test name
Test status
Simulation time	61431400 ps
CPU time	16.89 seconds
Started	Jul 12 06:43:41 PM PDT 24
Finished	Jul 12 06:44:03 PM PDT 24
Peak memory	261052 kb
Host	smart-b15ca0bd-80ee-4c9a-9fd8-3a583bea5630
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760244272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_csr_rw.3760244272
Directory	/workspace/14.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2375903094
Short name	T1153
Test name
Test status
Simulation time	24139800 ps
CPU time	13.49 seconds
Started	Jul 12 06:43:21 PM PDT 24
Finished	Jul 12 06:43:35 PM PDT 24
Peak memory	261200 kb
Host	smart-7fa54c17-030b-4cab-866c-c493c6f25cff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375903094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test. 2375903094
Directory	/workspace/14.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1732920805
Short name	T1216
Test name
Test status
Simulation time	560476600 ps
CPU time	18.72 seconds
Started	Jul 12 06:43:36 PM PDT 24
Finished	Jul 12 06:43:59 PM PDT 24
Peak memory	263728 kb
Host	smart-fe53a00b-62c5-401b-9eb8-02318ec21f92
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732920805 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.1732920805
Directory	/workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.357801665
Short name	T1148
Test name
Test status
Simulation time	15658200 ps
CPU time	15.56 seconds
Started	Jul 12 06:43:22 PM PDT 24
Finished	Jul 12 06:43:39 PM PDT 24
Peak memory	252972 kb
Host	smart-dedb1a86-d2a2-4e46-8efb-7b6af9ff0db0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357801665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.357801665
Directory	/workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.744535020
Short name	T1240
Test name
Test status
Simulation time	12430900 ps
CPU time	16.17 seconds
Started	Jul 12 06:43:43 PM PDT 24
Finished	Jul 12 06:44:07 PM PDT 24
Peak memory	252904 kb
Host	smart-acdbeb85-d022-4fd8-b208-4dd70a5b805f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744535020 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.744535020
Directory	/workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3493981814
Short name	T1119
Test name
Test status
Simulation time	132179400 ps
CPU time	18.97 seconds
Started	Jul 12 06:43:39 PM PDT 24
Finished	Jul 12 06:44:04 PM PDT 24
Peak memory	271408 kb
Host	smart-92c17fa4-1e16-48a9-bbf5-82f918f30dc3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493981814 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3493981814
Directory	/workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2988670132
Short name	T1177
Test name
Test status
Simulation time	54475200 ps
CPU time	17.47 seconds
Started	Jul 12 06:43:47 PM PDT 24
Finished	Jul 12 06:44:12 PM PDT 24
Peak memory	261308 kb
Host	smart-8a84484a-2e1d-45e6-b5d7-66608e9dc06d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988670132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_csr_rw.2988670132
Directory	/workspace/15.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1021265530
Short name	T309
Test name
Test status
Simulation time	23582000 ps
CPU time	13.62 seconds
Started	Jul 12 06:43:31 PM PDT 24
Finished	Jul 12 06:43:47 PM PDT 24
Peak memory	261200 kb
Host	smart-2f7e7211-df1a-4deb-9664-3e1070d69753
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021265530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test. 1021265530
Directory	/workspace/15.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3034274718
Short name	T1162
Test name
Test status
Simulation time	319993400 ps
CPU time	18.74 seconds
Started	Jul 12 06:43:27 PM PDT 24
Finished	Jul 12 06:43:48 PM PDT 24
Peak memory	263728 kb
Host	smart-4de64006-b767-486b-802f-64ec09ad6088
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034274718 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.3034274718
Directory	/workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3035668540
Short name	T1191
Test name
Test status
Simulation time	21279600 ps
CPU time	15.83 seconds
Started	Jul 12 06:43:46 PM PDT 24
Finished	Jul 12 06:44:09 PM PDT 24
Peak memory	253052 kb
Host	smart-8f8a07fb-fc88-42fb-8803-8ef021deca04
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035668540 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.3035668540
Directory	/workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3845686017
Short name	T1166
Test name
Test status
Simulation time	55492800 ps
CPU time	15.49 seconds
Started	Jul 12 06:43:38 PM PDT 24
Finished	Jul 12 06:43:59 PM PDT 24
Peak memory	252836 kb
Host	smart-72bb5a22-4212-4e15-b6ac-ffeab01df90b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845686017 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.3845686017
Directory	/workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1351486116
Short name	T248
Test name
Test status
Simulation time	36720800 ps
CPU time	16.51 seconds
Started	Jul 12 06:43:29 PM PDT 24
Finished	Jul 12 06:43:48 PM PDT 24
Peak memory	263700 kb
Host	smart-c2ee8020-4c10-4b71-aac2-06fb0e68e6d2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351486116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors. 1351486116
Directory	/workspace/15.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2995265994
Short name	T1250
Test name
Test status
Simulation time	49743500 ps
CPU time	18.57 seconds
Started	Jul 12 06:43:31 PM PDT 24
Finished	Jul 12 06:43:52 PM PDT 24
Peak memory	272280 kb
Host	smart-90fd2b90-c4b3-408b-8a6d-952e7f76729d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995265994 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.2995265994
Directory	/workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1248351438
Short name	T242
Test name
Test status
Simulation time	74894400 ps
CPU time	17.63 seconds
Started	Jul 12 06:43:39 PM PDT 24
Finished	Jul 12 06:44:02 PM PDT 24
Peak memory	261192 kb
Host	smart-cb7b0b11-4044-4529-b1b3-1f6dd26a8bb0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248351438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_csr_rw.1248351438
Directory	/workspace/16.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1766051966
Short name	T1164
Test name
Test status
Simulation time	245010500 ps
CPU time	13.59 seconds
Started	Jul 12 06:43:42 PM PDT 24
Finished	Jul 12 06:44:02 PM PDT 24
Peak memory	261208 kb
Host	smart-78746b87-76d9-4dbc-818d-3813c6cbafaa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766051966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test. 1766051966
Directory	/workspace/16.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3068342614
Short name	T1226
Test name
Test status
Simulation time	39736900 ps
CPU time	17.72 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:43:49 PM PDT 24
Peak memory	262376 kb
Host	smart-acf9a9db-0a83-42d7-9467-64a877a21399
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068342614 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.3068342614
Directory	/workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2713262303
Short name	T1108
Test name
Test status
Simulation time	46762700 ps
CPU time	13.5 seconds
Started	Jul 12 06:43:27 PM PDT 24
Finished	Jul 12 06:43:43 PM PDT 24
Peak memory	253032 kb
Host	smart-c7647532-bbb6-416f-8986-6ea772b7b5a1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713262303 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.2713262303
Directory	/workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1543634693
Short name	T1123
Test name
Test status
Simulation time	16161900 ps
CPU time	15.76 seconds
Started	Jul 12 06:43:31 PM PDT 24
Finished	Jul 12 06:43:49 PM PDT 24
Peak memory	253068 kb
Host	smart-02ca6cf3-daac-4b37-8410-39dae0f03d19
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543634693 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.1543634693
Directory	/workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.403476993
Short name	T188
Test name
Test status
Simulation time	57502900 ps
CPU time	15.83 seconds
Started	Jul 12 06:43:33 PM PDT 24
Finished	Jul 12 06:43:51 PM PDT 24
Peak memory	263672 kb
Host	smart-4cf6a88a-c945-4b0f-9011-975215288b2e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403476993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.403476993
Directory	/workspace/16.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2838110644
Short name	T1204
Test name
Test status
Simulation time	1436793400 ps
CPU time	757.68 seconds
Started	Jul 12 06:43:40 PM PDT 24
Finished	Jul 12 06:56:24 PM PDT 24
Peak memory	263748 kb
Host	smart-b6859c22-c5e4-454a-9cd4-079c14117a26
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838110644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr l_tl_intg_err.2838110644
Directory	/workspace/16.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.902923306
Short name	T1125
Test name
Test status
Simulation time	48453700 ps
CPU time	15.16 seconds
Started	Jul 12 06:43:30 PM PDT 24
Finished	Jul 12 06:43:47 PM PDT 24
Peak memory	273828 kb
Host	smart-0f4ea342-bb38-4569-b9e4-d9b59277c97a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902923306 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.902923306
Directory	/workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4282850865
Short name	T1158
Test name
Test status
Simulation time	30089200 ps
CPU time	16.99 seconds
Started	Jul 12 06:43:43 PM PDT 24
Finished	Jul 12 06:44:07 PM PDT 24
Peak memory	263720 kb
Host	smart-0869ae7a-1b6f-4184-88a8-2a87204c6703
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282850865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_csr_rw.4282850865
Directory	/workspace/17.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3325096055
Short name	T1146
Test name
Test status
Simulation time	14701500 ps
CPU time	13.44 seconds
Started	Jul 12 06:43:38 PM PDT 24
Finished	Jul 12 06:43:56 PM PDT 24
Peak memory	261212 kb
Host	smart-66f0ba7d-df73-44c1-975d-7355bd6f39a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325096055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test. 3325096055
Directory	/workspace/17.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1943114675
Short name	T288
Test name
Test status
Simulation time	433776400 ps
CPU time	18.87 seconds
Started	Jul 12 06:43:39 PM PDT 24
Finished	Jul 12 06:44:03 PM PDT 24
Peak memory	263724 kb
Host	smart-c78ae2dc-4c8f-4d84-8555-ba287f39d88e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943114675 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.1943114675
Directory	/workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2143008451
Short name	T1211
Test name
Test status
Simulation time	25096300 ps
CPU time	13.05 seconds
Started	Jul 12 06:43:31 PM PDT 24
Finished	Jul 12 06:43:47 PM PDT 24
Peak memory	252964 kb
Host	smart-1e8c8179-7c8a-4b79-9868-2ace0804cfcf
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143008451 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.2143008451
Directory	/workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.231146335
Short name	T1154
Test name
Test status
Simulation time	21491900 ps
CPU time	15.98 seconds
Started	Jul 12 06:43:32 PM PDT 24
Finished	Jul 12 06:43:50 PM PDT 24
Peak memory	252880 kb
Host	smart-f50a39ae-920f-427c-8be2-019ccd4b5bbf
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231146335 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.231146335
Directory	/workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.941449227
Short name	T332
Test name
Test status
Simulation time	2650551200 ps
CPU time	770.47 seconds
Started	Jul 12 06:43:38 PM PDT 24
Finished	Jul 12 06:56:34 PM PDT 24
Peak memory	263692 kb
Host	smart-70164049-6055-4153-8af6-6ed85c2f1345
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941449227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl _tl_intg_err.941449227
Directory	/workspace/17.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1966396931
Short name	T1199
Test name
Test status
Simulation time	109280800 ps
CPU time	15.88 seconds
Started	Jul 12 06:43:36 PM PDT 24
Finished	Jul 12 06:43:56 PM PDT 24
Peak memory	277512 kb
Host	smart-c48940f9-7f3e-4e61-9802-3c6a768169bd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966396931 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1966396931
Directory	/workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3697832167
Short name	T1182
Test name
Test status
Simulation time	280534900 ps
CPU time	16.91 seconds
Started	Jul 12 06:43:48 PM PDT 24
Finished	Jul 12 06:44:12 PM PDT 24
Peak memory	261160 kb
Host	smart-9d9e4a69-52de-415b-83f2-d08e5b8e4508
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697832167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_csr_rw.3697832167
Directory	/workspace/18.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1910318788
Short name	T1128
Test name
Test status
Simulation time	62545400 ps
CPU time	13.28 seconds
Started	Jul 12 06:43:44 PM PDT 24
Finished	Jul 12 06:44:05 PM PDT 24
Peak memory	261140 kb
Host	smart-4ea789b6-707c-418c-a44a-e6f985234b1a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910318788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test. 1910318788
Directory	/workspace/18.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4206916956
Short name	T1260
Test name
Test status
Simulation time	444622800 ps
CPU time	20.05 seconds
Started	Jul 12 06:43:29 PM PDT 24
Finished	Jul 12 06:43:52 PM PDT 24
Peak memory	263100 kb
Host	smart-0faf26dc-eb82-4539-89bb-e98b62565ff6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206916956 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.4206916956
Directory	/workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.416646366
Short name	T1157
Test name
Test status
Simulation time	23990700 ps
CPU time	15.91 seconds
Started	Jul 12 06:43:47 PM PDT 24
Finished	Jul 12 06:44:10 PM PDT 24
Peak memory	252948 kb
Host	smart-bfddab23-fae1-49bd-bbba-620bc24422a5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416646366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.416646366
Directory	/workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4278706380
Short name	T1120
Test name
Test status
Simulation time	21487100 ps
CPU time	13.13 seconds
Started	Jul 12 06:43:42 PM PDT 24
Finished	Jul 12 06:44:01 PM PDT 24
Peak memory	252944 kb
Host	smart-b0095711-e2cd-4d00-ac86-5fed3f6f6610
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278706380 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.4278706380
Directory	/workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2014815628
Short name	T219
Test name
Test status
Simulation time	469393500 ps
CPU time	20.35 seconds
Started	Jul 12 06:43:44 PM PDT 24
Finished	Jul 12 06:44:12 PM PDT 24
Peak memory	263684 kb
Host	smart-2cff7987-b3af-4552-a236-eedd59b3facc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014815628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors. 2014815628
Directory	/workspace/18.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4035608821
Short name	T323
Test name
Test status
Simulation time	380391900 ps
CPU time	451.79 seconds
Started	Jul 12 06:43:33 PM PDT 24
Finished	Jul 12 06:51:07 PM PDT 24
Peak memory	263700 kb
Host	smart-997dee79-6757-48b1-bd70-fb4e2a3d82e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035608821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr l_tl_intg_err.4035608821
Directory	/workspace/18.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.727923140
Short name	T1143
Test name
Test status
Simulation time	59352700 ps
CPU time	18.63 seconds
Started	Jul 12 06:43:44 PM PDT 24
Finished	Jul 12 06:44:11 PM PDT 24
Peak memory	272020 kb
Host	smart-47c2749d-b80a-4ac1-8a6c-bd8f9388ccae
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727923140 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.727923140
Directory	/workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.494740791
Short name	T1261
Test name
Test status
Simulation time	304430700 ps
CPU time	17.34 seconds
Started	Jul 12 06:43:37 PM PDT 24
Finished	Jul 12 06:43:59 PM PDT 24
Peak memory	263736 kb
Host	smart-ebe3b455-0ca5-4947-908d-1a1c83dd76c8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494740791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.flash_ctrl_csr_rw.494740791
Directory	/workspace/19.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.984023427
Short name	T1258
Test name
Test status
Simulation time	27136200 ps
CPU time	13.99 seconds
Started	Jul 12 06:43:35 PM PDT 24
Finished	Jul 12 06:43:52 PM PDT 24
Peak memory	261140 kb
Host	smart-fb7caba4-88d9-4447-a897-eb662ba14439
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984023427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.984023427
Directory	/workspace/19.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.132615392
Short name	T278
Test name
Test status
Simulation time	223882100 ps
CPU time	36.03 seconds
Started	Jul 12 06:43:48 PM PDT 24
Finished	Jul 12 06:44:32 PM PDT 24
Peak memory	261364 kb
Host	smart-25f0b4dc-0cb5-4ab8-9b23-0bb01dbb8126
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132615392 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.132615392
Directory	/workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3632756022
Short name	T1144
Test name
Test status
Simulation time	13044300 ps
CPU time	13.2 seconds
Started	Jul 12 06:43:37 PM PDT 24
Finished	Jul 12 06:43:55 PM PDT 24
Peak memory	253012 kb
Host	smart-7e321b06-fe00-46b1-9aa4-ae8ed613a33a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632756022 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3632756022
Directory	/workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.250191236
Short name	T1239
Test name
Test status
Simulation time	22975400 ps
CPU time	15.9 seconds
Started	Jul 12 06:43:57 PM PDT 24
Finished	Jul 12 06:44:19 PM PDT 24
Peak memory	252884 kb
Host	smart-d3d2d436-d097-43b8-b563-64a9156ad6d3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250191236 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.250191236
Directory	/workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.868004099
Short name	T1247
Test name
Test status
Simulation time	115552800 ps
CPU time	15.67 seconds
Started	Jul 12 06:43:38 PM PDT 24
Finished	Jul 12 06:43:59 PM PDT 24
Peak memory	263716 kb
Host	smart-0205bea7-3ac2-4c0b-a0cd-afa64e42bb60
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868004099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.868004099
Directory	/workspace/19.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.4239127582
Short name	T334
Test name
Test status
Simulation time	690027500 ps
CPU time	463.24 seconds
Started	Jul 12 06:43:43 PM PDT 24
Finished	Jul 12 06:51:33 PM PDT 24
Peak memory	263812 kb
Host	smart-afe79bca-75f3-46e4-9d18-7283d8df208f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239127582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr l_tl_intg_err.4239127582
Directory	/workspace/19.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2317466320
Short name	T1135
Test name
Test status
Simulation time	471583800 ps
CPU time	32.08 seconds
Started	Jul 12 06:43:15 PM PDT 24
Finished	Jul 12 06:43:49 PM PDT 24
Peak memory	261236 kb
Host	smart-b954f508-b316-4f73-8c61-1ed45368ffd9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317466320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_aliasing.2317466320
Directory	/workspace/2.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2552620441
Short name	T1127
Test name
Test status
Simulation time	647552000 ps
CPU time	60.72 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:44:31 PM PDT 24
Peak memory	261228 kb
Host	smart-c6fcf6e7-8fcc-46f3-ad15-b9c4c4bd2afb
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552620441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_bit_bash.2552620441
Directory	/workspace/2.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1290927498
Short name	T284
Test name
Test status
Simulation time	56537000 ps
CPU time	30.53 seconds
Started	Jul 12 06:43:09 PM PDT 24
Finished	Jul 12 06:43:44 PM PDT 24
Peak memory	261084 kb
Host	smart-39bd13c4-3fbe-4086-bce3-b566d6ea09e0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290927498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_hw_reset.1290927498
Directory	/workspace/2.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1620481382
Short name	T1224
Test name
Test status
Simulation time	27086000 ps
CPU time	15.02 seconds
Started	Jul 12 06:43:19 PM PDT 24
Finished	Jul 12 06:43:35 PM PDT 24
Peak memory	263892 kb
Host	smart-63a923ad-52e8-45cb-8d2b-1ab5d22bc2fb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620481382 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.1620481382
Directory	/workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.4089380883
Short name	T1163
Test name
Test status
Simulation time	48021000 ps
CPU time	17.47 seconds
Started	Jul 12 06:43:08 PM PDT 24
Finished	Jul 12 06:43:30 PM PDT 24
Peak memory	263728 kb
Host	smart-ae5da695-3ee9-4113-b43a-2f09214bff2f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089380883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_csr_rw.4089380883
Directory	/workspace/2.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2592055817
Short name	T306
Test name
Test status
Simulation time	15428300 ps
CPU time	14.36 seconds
Started	Jul 12 06:43:24 PM PDT 24
Finished	Jul 12 06:43:40 PM PDT 24
Peak memory	261112 kb
Host	smart-2df40d94-3d66-4155-a189-3408823f4845
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592055817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.2 592055817
Directory	/workspace/2.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1217684836
Short name	T224
Test name
Test status
Simulation time	25682200 ps
CPU time	14.18 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:43:44 PM PDT 24
Peak memory	262716 kb
Host	smart-5ed8b229-34e4-4431-a738-1dd45964c718
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217684836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_mem_partial_access.1217684836
Directory	/workspace/2.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3362596263
Short name	T1179
Test name
Test status
Simulation time	30310800 ps
CPU time	13.34 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:43:43 PM PDT 24
Peak memory	261172 kb
Host	smart-c8ef5d3f-224f-455d-b7ac-b2d46eedfad5
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362596263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me m_walk.3362596263
Directory	/workspace/2.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3170533557
Short name	T1210
Test name
Test status
Simulation time	57886200 ps
CPU time	19.2 seconds
Started	Jul 12 06:43:10 PM PDT 24
Finished	Jul 12 06:43:33 PM PDT 24
Peak memory	261332 kb
Host	smart-d8fc3114-1ea6-4172-82f2-e542cf6763ef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170533557 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.3170533557
Directory	/workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2766178699
Short name	T1152
Test name
Test status
Simulation time	34850700 ps
CPU time	15.71 seconds
Started	Jul 12 06:43:20 PM PDT 24
Finished	Jul 12 06:43:36 PM PDT 24
Peak memory	253004 kb
Host	smart-781c6359-83e9-409c-8900-8a31b75d1f06
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766178699 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2766178699
Directory	/workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3398103021
Short name	T1131
Test name
Test status
Simulation time	14775300 ps
CPU time	15.7 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:43:46 PM PDT 24
Peak memory	252972 kb
Host	smart-66a4f336-e11e-4f24-a828-ff9ff6283d91
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398103021 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.3398103021
Directory	/workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1328953612
Short name	T91
Test name
Test status
Simulation time	53003900 ps
CPU time	19.62 seconds
Started	Jul 12 06:43:24 PM PDT 24
Finished	Jul 12 06:43:45 PM PDT 24
Peak memory	263736 kb
Host	smart-c624227f-0421-4ddb-9f07-f76203aa0364
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328953612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.1 328953612
Directory	/workspace/2.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1957667436
Short name	T330
Test name
Test status
Simulation time	1441849300 ps
CPU time	903.85 seconds
Started	Jul 12 06:43:17 PM PDT 24
Finished	Jul 12 06:58:22 PM PDT 24
Peak memory	263748 kb
Host	smart-b3bea4b8-dc98-4f94-90bb-e39fefc0004e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957667436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl _tl_intg_err.1957667436
Directory	/workspace/2.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.366335650
Short name	T1192
Test name
Test status
Simulation time	51062900 ps
CPU time	13.8 seconds
Started	Jul 12 06:43:39 PM PDT 24
Finished	Jul 12 06:43:58 PM PDT 24
Peak memory	261172 kb
Host	smart-f9b1296e-de0e-40c4-909f-b78b3f8c55c0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366335650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.366335650
Directory	/workspace/20.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3050515996
Short name	T1186
Test name
Test status
Simulation time	34420600 ps
CPU time	14.09 seconds
Started	Jul 12 06:43:44 PM PDT 24
Finished	Jul 12 06:44:06 PM PDT 24
Peak memory	261096 kb
Host	smart-349b2e57-2543-4c09-a7d3-1e067b1fd30f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050515996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test. 3050515996
Directory	/workspace/21.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3320147158
Short name	T1129
Test name
Test status
Simulation time	64119900 ps
CPU time	13.28 seconds
Started	Jul 12 06:43:39 PM PDT 24
Finished	Jul 12 06:43:57 PM PDT 24
Peak memory	261092 kb
Host	smart-1230a1b7-4460-4b38-b730-aade16c56baf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320147158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test. 3320147158
Directory	/workspace/22.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1812194340
Short name	T1122
Test name
Test status
Simulation time	17911000 ps
CPU time	13.27 seconds
Started	Jul 12 06:43:53 PM PDT 24
Finished	Jul 12 06:44:12 PM PDT 24
Peak memory	261072 kb
Host	smart-80d2b064-ddad-424f-80de-5097bc330970
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812194340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test. 1812194340
Directory	/workspace/23.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.196187289
Short name	T1242
Test name
Test status
Simulation time	16386600 ps
CPU time	13.47 seconds
Started	Jul 12 06:43:55 PM PDT 24
Finished	Jul 12 06:44:14 PM PDT 24
Peak memory	261212 kb
Host	smart-1b71fd93-0e8d-4620-ae64-bff297f292a2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196187289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.196187289
Directory	/workspace/24.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.371599399
Short name	T1206
Test name
Test status
Simulation time	16359900 ps
CPU time	14.24 seconds
Started	Jul 12 06:43:48 PM PDT 24
Finished	Jul 12 06:44:09 PM PDT 24
Peak memory	261092 kb
Host	smart-aed0190e-2642-4d37-870f-e32c9ae39fd4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371599399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.371599399
Directory	/workspace/25.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2606596490
Short name	T1160
Test name
Test status
Simulation time	52128300 ps
CPU time	13.36 seconds
Started	Jul 12 06:43:42 PM PDT 24
Finished	Jul 12 06:44:02 PM PDT 24
Peak memory	261168 kb
Host	smart-33905e1a-7dd7-44f3-9b47-1a57a404d729
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606596490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test. 2606596490
Directory	/workspace/27.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3670384889
Short name	T1141
Test name
Test status
Simulation time	27811300 ps
CPU time	14.14 seconds
Started	Jul 12 06:43:53 PM PDT 24
Finished	Jul 12 06:44:13 PM PDT 24
Peak memory	261132 kb
Host	smart-daaed16d-23ee-4205-8e64-20329483af1d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670384889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test. 3670384889
Directory	/workspace/28.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.901381095
Short name	T1185
Test name
Test status
Simulation time	18530200 ps
CPU time	13.41 seconds
Started	Jul 12 06:43:42 PM PDT 24
Finished	Jul 12 06:44:02 PM PDT 24
Peak memory	261168 kb
Host	smart-fdea5ed2-6c34-4e37-94a6-d7200e58e25e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901381095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.901381095
Directory	/workspace/29.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2211107693
Short name	T65
Test name
Test status
Simulation time	2581350600 ps
CPU time	63.38 seconds
Started	Jul 12 06:43:14 PM PDT 24
Finished	Jul 12 06:44:20 PM PDT 24
Peak memory	261224 kb
Host	smart-90f38d69-597a-423f-924f-c24ddef53c12
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211107693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_aliasing.2211107693
Directory	/workspace/3.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2803321503
Short name	T281
Test name
Test status
Simulation time	10341192800 ps
CPU time	57.79 seconds
Started	Jul 12 06:43:19 PM PDT 24
Finished	Jul 12 06:44:17 PM PDT 24
Peak memory	261288 kb
Host	smart-555b7538-e421-4b28-bfae-aefcd5e9ca92
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803321503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_bit_bash.2803321503
Directory	/workspace/3.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3582725460
Short name	T286
Test name
Test status
Simulation time	164480800 ps
CPU time	45.71 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:44:16 PM PDT 24
Peak memory	261360 kb
Host	smart-38664593-5b48-42ac-89ab-071129f9b138
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582725460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_hw_reset.3582725460
Directory	/workspace/3.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2049399339
Short name	T1243
Test name
Test status
Simulation time	77042800 ps
CPU time	17.7 seconds
Started	Jul 12 06:43:12 PM PDT 24
Finished	Jul 12 06:43:33 PM PDT 24
Peak memory	272012 kb
Host	smart-d371b169-d48b-4036-ac37-776f7b410289
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049399339 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.2049399339
Directory	/workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.289937871
Short name	T1200
Test name
Test status
Simulation time	24753200 ps
CPU time	16.89 seconds
Started	Jul 12 06:43:30 PM PDT 24
Finished	Jul 12 06:43:49 PM PDT 24
Peak memory	263704 kb
Host	smart-277d3f1d-72e8-4ea9-9da1-f85c64956663
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289937871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.flash_ctrl_csr_rw.289937871
Directory	/workspace/3.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2049320005
Short name	T1234
Test name
Test status
Simulation time	26475300 ps
CPU time	14.03 seconds
Started	Jul 12 06:43:36 PM PDT 24
Finished	Jul 12 06:43:53 PM PDT 24
Peak memory	261116 kb
Host	smart-06d6514b-be55-47e1-912f-e78969e4da4c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049320005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2 049320005
Directory	/workspace/3.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3106175640
Short name	T222
Test name
Test status
Simulation time	85103600 ps
CPU time	13.65 seconds
Started	Jul 12 06:43:16 PM PDT 24
Finished	Jul 12 06:43:31 PM PDT 24
Peak memory	262000 kb
Host	smart-b5179902-3b2f-41ea-a55b-ce9cf775ed72
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106175640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_mem_partial_access.3106175640
Directory	/workspace/3.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.503732402
Short name	T1167
Test name
Test status
Simulation time	14260300 ps
CPU time	13.74 seconds
Started	Jul 12 06:43:13 PM PDT 24
Finished	Jul 12 06:43:29 PM PDT 24
Peak memory	260840 kb
Host	smart-c136072f-2036-421c-bb90-67ace5446953
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503732402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem _walk.503732402
Directory	/workspace/3.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3089421956
Short name	T1212
Test name
Test status
Simulation time	151046300 ps
CPU time	20.65 seconds
Started	Jul 12 06:43:13 PM PDT 24
Finished	Jul 12 06:43:36 PM PDT 24
Peak memory	262548 kb
Host	smart-d4e36fa9-7700-4c0c-87b1-1982296532f1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089421956 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.3089421956
Directory	/workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1973884681
Short name	T1187
Test name
Test status
Simulation time	19102200 ps
CPU time	13.21 seconds
Started	Jul 12 06:43:05 PM PDT 24
Finished	Jul 12 06:43:21 PM PDT 24
Peak memory	252948 kb
Host	smart-83884ecc-39b8-4fc0-beac-d6f81357c01c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973884681 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.1973884681
Directory	/workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.366163560
Short name	T1150
Test name
Test status
Simulation time	24320200 ps
CPU time	15.76 seconds
Started	Jul 12 06:43:30 PM PDT 24
Finished	Jul 12 06:43:49 PM PDT 24
Peak memory	253080 kb
Host	smart-6e82aa3b-4a42-49bc-bfca-30b5a3bbc3f1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366163560 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.366163560
Directory	/workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3912981163
Short name	T251
Test name
Test status
Simulation time	102802700 ps
CPU time	18.72 seconds
Started	Jul 12 06:43:08 PM PDT 24
Finished	Jul 12 06:43:31 PM PDT 24
Peak memory	263680 kb
Host	smart-6a3e1acd-8f38-4803-9985-962e88211b0b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912981163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.3 912981163
Directory	/workspace/3.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3889112332
Short name	T329
Test name
Test status
Simulation time	729385300 ps
CPU time	459.61 seconds
Started	Jul 12 06:43:22 PM PDT 24
Finished	Jul 12 06:51:02 PM PDT 24
Peak memory	263688 kb
Host	smart-6bef7d4d-cddd-4b08-95ac-8a9423e2976c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889112332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _tl_intg_err.3889112332
Directory	/workspace/3.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2303989344
Short name	T1147
Test name
Test status
Simulation time	16406300 ps
CPU time	14.12 seconds
Started	Jul 12 06:43:33 PM PDT 24
Finished	Jul 12 06:43:49 PM PDT 24
Peak memory	261064 kb
Host	smart-2d30286e-b23f-4048-a088-53a636322644
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303989344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test. 2303989344
Directory	/workspace/30.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1760863375
Short name	T1176
Test name
Test status
Simulation time	77213100 ps
CPU time	13.89 seconds
Started	Jul 12 06:43:43 PM PDT 24
Finished	Jul 12 06:44:04 PM PDT 24
Peak memory	261200 kb
Host	smart-209f379f-7166-479a-9a35-b00139ca91f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760863375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test. 1760863375
Directory	/workspace/31.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1241295431
Short name	T1209
Test name
Test status
Simulation time	14764300 ps
CPU time	14.25 seconds
Started	Jul 12 06:43:37 PM PDT 24
Finished	Jul 12 06:43:54 PM PDT 24
Peak memory	261244 kb
Host	smart-d1a15cd4-8394-48b1-9aee-18d51d676b26
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241295431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test. 1241295431
Directory	/workspace/32.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3455727292
Short name	T1142
Test name
Test status
Simulation time	54815900 ps
CPU time	13.51 seconds
Started	Jul 12 06:43:48 PM PDT 24
Finished	Jul 12 06:44:09 PM PDT 24
Peak memory	261172 kb
Host	smart-98d66315-9aa4-4339-b922-e8d435f7f224
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455727292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test. 3455727292
Directory	/workspace/33.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3190846291
Short name	T1155
Test name
Test status
Simulation time	54150100 ps
CPU time	13.58 seconds
Started	Jul 12 06:43:48 PM PDT 24
Finished	Jul 12 06:44:09 PM PDT 24
Peak memory	261172 kb
Host	smart-5237d547-2a9b-40c8-917a-8d35074b0abc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190846291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test. 3190846291
Directory	/workspace/34.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2977489333
Short name	T247
Test name
Test status
Simulation time	39539400 ps
CPU time	13.61 seconds
Started	Jul 12 06:43:32 PM PDT 24
Finished	Jul 12 06:43:48 PM PDT 24
Peak memory	261100 kb
Host	smart-a93cdd87-0071-4e66-a71b-f10ec3ca9e45
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977489333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test. 2977489333
Directory	/workspace/35.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1907770602
Short name	T308
Test name
Test status
Simulation time	43258700 ps
CPU time	13.42 seconds
Started	Jul 12 06:43:38 PM PDT 24
Finished	Jul 12 06:43:57 PM PDT 24
Peak memory	261112 kb
Host	smart-7a408247-2d95-44a0-80a2-7db75f849a22
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907770602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test. 1907770602
Directory	/workspace/36.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3593452356
Short name	T1156
Test name
Test status
Simulation time	17342700 ps
CPU time	14.25 seconds
Started	Jul 12 06:43:43 PM PDT 24
Finished	Jul 12 06:44:05 PM PDT 24
Peak memory	260940 kb
Host	smart-2b7e31d6-b4bb-4b7c-90af-15eb109d0af8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593452356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test. 3593452356
Directory	/workspace/37.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2538314475
Short name	T1121
Test name
Test status
Simulation time	21223700 ps
CPU time	13.27 seconds
Started	Jul 12 06:43:38 PM PDT 24
Finished	Jul 12 06:43:57 PM PDT 24
Peak memory	261248 kb
Host	smart-4406dd83-c175-44b8-86db-0887adc1435c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538314475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test. 2538314475
Directory	/workspace/38.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.640780674
Short name	T1173
Test name
Test status
Simulation time	18002800 ps
CPU time	13.93 seconds
Started	Jul 12 06:43:47 PM PDT 24
Finished	Jul 12 06:44:08 PM PDT 24
Peak memory	261104 kb
Host	smart-c864fc63-05ca-4788-80c4-810dac8310c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640780674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.640780674
Directory	/workspace/39.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3605950465
Short name	T1214
Test name
Test status
Simulation time	440658400 ps
CPU time	33.6 seconds
Started	Jul 12 06:43:25 PM PDT 24
Finished	Jul 12 06:44:00 PM PDT 24
Peak memory	261192 kb
Host	smart-93539a8b-80e8-4d23-a547-7e5dc8b59ba3
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605950465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_aliasing.3605950465
Directory	/workspace/4.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1581727880
Short name	T67
Test name
Test status
Simulation time	1197863600 ps
CPU time	47.74 seconds
Started	Jul 12 06:43:22 PM PDT 24
Finished	Jul 12 06:44:10 PM PDT 24
Peak memory	261212 kb
Host	smart-a7582bf7-9bd8-4b79-89dc-16f7b3c8fce6
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581727880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_bit_bash.1581727880
Directory	/workspace/4.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1697019267
Short name	T1137
Test name
Test status
Simulation time	259097100 ps
CPU time	45.32 seconds
Started	Jul 12 06:43:44 PM PDT 24
Finished	Jul 12 06:44:37 PM PDT 24
Peak memory	261304 kb
Host	smart-925d346e-3b5c-46c9-8c74-43b029e2892f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697019267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_hw_reset.1697019267
Directory	/workspace/4.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4190908188
Short name	T1203
Test name
Test status
Simulation time	84343100 ps
CPU time	14.51 seconds
Started	Jul 12 06:43:20 PM PDT 24
Finished	Jul 12 06:43:35 PM PDT 24
Peak memory	263472 kb
Host	smart-81e2e577-6c51-41a7-89e2-a5e0661d45af
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190908188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 4.flash_ctrl_csr_rw.4190908188
Directory	/workspace/4.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1349798770
Short name	T1252
Test name
Test status
Simulation time	16928900 ps
CPU time	13.79 seconds
Started	Jul 12 06:43:21 PM PDT 24
Finished	Jul 12 06:43:36 PM PDT 24
Peak memory	261124 kb
Host	smart-c4eb8ce0-c232-4849-b759-24bbae04fb30
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349798770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.1 349798770
Directory	/workspace/4.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2311916142
Short name	T221
Test name
Test status
Simulation time	18792800 ps
CPU time	13.62 seconds
Started	Jul 12 06:43:25 PM PDT 24
Finished	Jul 12 06:43:40 PM PDT 24
Peak memory	262712 kb
Host	smart-ce668265-7a5f-4a9b-b58d-c2207b64b379
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311916142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_mem_partial_access.2311916142
Directory	/workspace/4.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3021520907
Short name	T1205
Test name
Test status
Simulation time	16045800 ps
CPU time	13.52 seconds
Started	Jul 12 06:43:19 PM PDT 24
Finished	Jul 12 06:43:33 PM PDT 24
Peak memory	260980 kb
Host	smart-e53ff704-a6db-42ea-98b2-0e6c0c6d7986
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021520907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me m_walk.3021520907
Directory	/workspace/4.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.73568807
Short name	T1165
Test name
Test status
Simulation time	178237900 ps
CPU time	36.42 seconds
Started	Jul 12 06:43:26 PM PDT 24
Finished	Jul 12 06:44:04 PM PDT 24
Peak memory	261264 kb
Host	smart-18d47306-b8b9-4cb9-8fb1-a346b8c32e67
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73568807 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.73568807
Directory	/workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.583561122
Short name	T1223
Test name
Test status
Simulation time	14500000 ps
CPU time	16.47 seconds
Started	Jul 12 06:43:25 PM PDT 24
Finished	Jul 12 06:43:43 PM PDT 24
Peak memory	253032 kb
Host	smart-d095f29f-f68f-41f8-816b-8f7678bef8df
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583561122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.583561122
Directory	/workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1187009429
Short name	T1110
Test name
Test status
Simulation time	36178200 ps
CPU time	16.28 seconds
Started	Jul 12 06:43:25 PM PDT 24
Finished	Jul 12 06:43:43 PM PDT 24
Peak memory	252912 kb
Host	smart-4f85be41-eef4-4d1b-8c37-c39b25e5b667
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187009429 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.1187009429
Directory	/workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3440853752
Short name	T328
Test name
Test status
Simulation time	648141700 ps
CPU time	383.57 seconds
Started	Jul 12 06:43:11 PM PDT 24
Finished	Jul 12 06:49:38 PM PDT 24
Peak memory	263664 kb
Host	smart-c1ce6d01-e169-4f0e-87f3-a53deb419861
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440853752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl _tl_intg_err.3440853752
Directory	/workspace/4.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2010436748
Short name	T1237
Test name
Test status
Simulation time	15256700 ps
CPU time	13.89 seconds
Started	Jul 12 06:43:44 PM PDT 24
Finished	Jul 12 06:44:06 PM PDT 24
Peak memory	261068 kb
Host	smart-c191ab9b-2bdc-474d-801a-fa643f4c474d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010436748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test. 2010436748
Directory	/workspace/40.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2781430457
Short name	T1184
Test name
Test status
Simulation time	22997300 ps
CPU time	13.53 seconds
Started	Jul 12 06:43:46 PM PDT 24
Finished	Jul 12 06:44:07 PM PDT 24
Peak memory	261156 kb
Host	smart-bbd2929d-6723-4efa-9777-589168b32f78
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781430457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test. 2781430457
Directory	/workspace/41.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.4014680036
Short name	T1138
Test name
Test status
Simulation time	23009900 ps
CPU time	13.77 seconds
Started	Jul 12 06:43:47 PM PDT 24
Finished	Jul 12 06:44:08 PM PDT 24
Peak memory	261096 kb
Host	smart-f7979bcb-fb1c-4f63-95ee-86e4a0c31d9f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014680036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test. 4014680036
Directory	/workspace/42.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1596097215
Short name	T1219
Test name
Test status
Simulation time	30227200 ps
CPU time	14.05 seconds
Started	Jul 12 06:43:38 PM PDT 24
Finished	Jul 12 06:43:57 PM PDT 24
Peak memory	261084 kb
Host	smart-2dc56a77-7c93-4465-b6e0-4a722c4e6496
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596097215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test. 1596097215
Directory	/workspace/43.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2780591370
Short name	T1132
Test name
Test status
Simulation time	161969800 ps
CPU time	13.56 seconds
Started	Jul 12 06:43:52 PM PDT 24
Finished	Jul 12 06:44:11 PM PDT 24
Peak memory	261108 kb
Host	smart-ed8cb63e-c910-4f27-bbe6-307263a71e11
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780591370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test. 2780591370
Directory	/workspace/44.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.455120794
Short name	T1222
Test name
Test status
Simulation time	17208000 ps
CPU time	13.53 seconds
Started	Jul 12 06:43:37 PM PDT 24
Finished	Jul 12 06:43:55 PM PDT 24
Peak memory	261116 kb
Host	smart-9f587904-6158-4197-8f10-6b8c97c85e2f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455120794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.455120794
Directory	/workspace/45.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2805823084
Short name	T1183
Test name
Test status
Simulation time	97901600 ps
CPU time	13.43 seconds
Started	Jul 12 06:43:43 PM PDT 24
Finished	Jul 12 06:44:03 PM PDT 24
Peak memory	261232 kb
Host	smart-1d5523f9-ac85-4d56-a9f8-652b25878d29
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805823084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test. 2805823084
Directory	/workspace/46.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2976518618
Short name	T1221
Test name
Test status
Simulation time	61225200 ps
CPU time	13.63 seconds
Started	Jul 12 06:43:54 PM PDT 24
Finished	Jul 12 06:44:14 PM PDT 24
Peak memory	261208 kb
Host	smart-f7c277aa-034a-493f-97d7-9b980b48b0ef
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976518618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test. 2976518618
Directory	/workspace/47.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.989765434
Short name	T1253
Test name
Test status
Simulation time	17255900 ps
CPU time	14.14 seconds
Started	Jul 12 06:43:39 PM PDT 24
Finished	Jul 12 06:43:58 PM PDT 24
Peak memory	261108 kb
Host	smart-fffc0dde-6697-41a9-bc59-3297130919c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989765434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.989765434
Directory	/workspace/49.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1192302870
Short name	T254
Test name
Test status
Simulation time	105988800 ps
CPU time	17.12 seconds
Started	Jul 12 06:43:26 PM PDT 24
Finished	Jul 12 06:43:44 PM PDT 24
Peak memory	270480 kb
Host	smart-4159e5d7-26e3-4b39-aac2-acd7c2980d2f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192302870 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.1192302870
Directory	/workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4250264807
Short name	T1168
Test name
Test status
Simulation time	200818000 ps
CPU time	17.19 seconds
Started	Jul 12 06:43:15 PM PDT 24
Finished	Jul 12 06:43:34 PM PDT 24
Peak memory	261308 kb
Host	smart-037c08ce-6ac7-4b23-8f67-b512b678cba1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250264807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.flash_ctrl_csr_rw.4250264807
Directory	/workspace/5.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2334034068
Short name	T1134
Test name
Test status
Simulation time	16454400 ps
CPU time	14.13 seconds
Started	Jul 12 06:43:23 PM PDT 24
Finished	Jul 12 06:43:38 PM PDT 24
Peak memory	261136 kb
Host	smart-9062c527-bcd3-403f-9a75-b710652014f7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334034068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2 334034068
Directory	/workspace/5.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1131827727
Short name	T1195
Test name
Test status
Simulation time	225150100 ps
CPU time	17.3 seconds
Started	Jul 12 06:43:23 PM PDT 24
Finished	Jul 12 06:43:42 PM PDT 24
Peak memory	261204 kb
Host	smart-c3f5551b-9855-4fa5-aeb7-8d9ea242949c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131827727 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1131827727
Directory	/workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3551167831
Short name	T1181
Test name
Test status
Simulation time	32301800 ps
CPU time	13.16 seconds
Started	Jul 12 06:43:29 PM PDT 24
Finished	Jul 12 06:43:45 PM PDT 24
Peak memory	252844 kb
Host	smart-ef03042c-c03f-4f1f-beb5-ca24e0d6f662
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551167831 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.3551167831
Directory	/workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.13056343
Short name	T1115
Test name
Test status
Simulation time	16786300 ps
CPU time	13.41 seconds
Started	Jul 12 06:43:25 PM PDT 24
Finished	Jul 12 06:43:40 PM PDT 24
Peak memory	252928 kb
Host	smart-97b1a35e-a532-49fc-96fa-b024eea7d73f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13056343 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.13056343
Directory	/workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2122893642
Short name	T1238
Test name
Test status
Simulation time	46612000 ps
CPU time	15.69 seconds
Started	Jul 12 06:43:18 PM PDT 24
Finished	Jul 12 06:43:34 PM PDT 24
Peak memory	263780 kb
Host	smart-83b6a752-f018-4e9b-ba05-f679bd7677a4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122893642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2 122893642
Directory	/workspace/5.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1205377826
Short name	T326
Test name
Test status
Simulation time	1322847700 ps
CPU time	913.86 seconds
Started	Jul 12 06:43:20 PM PDT 24
Finished	Jul 12 06:58:35 PM PDT 24
Peak memory	263688 kb
Host	smart-399b0145-7c32-4147-96c0-ec363da1ba8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205377826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl _tl_intg_err.1205377826
Directory	/workspace/5.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3127644747
Short name	T287
Test name
Test status
Simulation time	96442400 ps
CPU time	17.21 seconds
Started	Jul 12 06:43:14 PM PDT 24
Finished	Jul 12 06:43:34 PM PDT 24
Peak memory	263764 kb
Host	smart-cd6cb6ff-6fd8-40e3-8872-d315074948ab
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127644747 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.3127644747
Directory	/workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.4079675204
Short name	T1229
Test name
Test status
Simulation time	37884600 ps
CPU time	14.54 seconds
Started	Jul 12 06:43:13 PM PDT 24
Finished	Jul 12 06:43:30 PM PDT 24
Peak memory	263768 kb
Host	smart-dbb8ccb5-92fd-4c07-bc7b-41f36f099f34
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079675204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 6.flash_ctrl_csr_rw.4079675204
Directory	/workspace/6.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.284981401
Short name	T1194
Test name
Test status
Simulation time	114314200 ps
CPU time	14.3 seconds
Started	Jul 12 06:43:23 PM PDT 24
Finished	Jul 12 06:43:38 PM PDT 24
Peak memory	261064 kb
Host	smart-d16a5225-6061-4ecb-bcc5-c671a8cf36db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284981401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.284981401
Directory	/workspace/6.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3251942777
Short name	T1124
Test name
Test status
Simulation time	127981300 ps
CPU time	17.72 seconds
Started	Jul 12 06:43:22 PM PDT 24
Finished	Jul 12 06:43:41 PM PDT 24
Peak memory	263700 kb
Host	smart-6fd12b6d-a2b9-4239-9cdd-7aabfe48b8b1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251942777 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.3251942777
Directory	/workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2941018762
Short name	T1161
Test name
Test status
Simulation time	14581600 ps
CPU time	15.86 seconds
Started	Jul 12 06:43:19 PM PDT 24
Finished	Jul 12 06:43:36 PM PDT 24
Peak memory	252940 kb
Host	smart-25b93ae2-201f-46b5-b100-c05bb8274817
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941018762 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.2941018762
Directory	/workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.287870972
Short name	T1109
Test name
Test status
Simulation time	12038300 ps
CPU time	13.99 seconds
Started	Jul 12 06:43:24 PM PDT 24
Finished	Jul 12 06:43:40 PM PDT 24
Peak memory	253000 kb
Host	smart-e4e00ccc-59ce-40b2-ad97-0b609391cbda
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287870972 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.287870972
Directory	/workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3422610547
Short name	T217
Test name
Test status
Simulation time	430597800 ps
CPU time	19.88 seconds
Started	Jul 12 06:43:21 PM PDT 24
Finished	Jul 12 06:43:41 PM PDT 24
Peak memory	263740 kb
Host	smart-dbd07934-ad70-40c5-bb17-5687630edf24
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422610547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.3 422610547
Directory	/workspace/6.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3067758999
Short name	T324
Test name
Test status
Simulation time	1230214100 ps
CPU time	909.25 seconds
Started	Jul 12 06:43:09 PM PDT 24
Finished	Jul 12 06:58:23 PM PDT 24
Peak memory	263916 kb
Host	smart-d34f151f-265c-4c89-84f6-f139815d68d4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067758999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl _tl_intg_err.3067758999
Directory	/workspace/6.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2043959443
Short name	T1136
Test name
Test status
Simulation time	51116300 ps
CPU time	14.97 seconds
Started	Jul 12 06:43:15 PM PDT 24
Finished	Jul 12 06:43:32 PM PDT 24
Peak memory	270340 kb
Host	smart-4862215f-c5b0-498a-9e65-c64c8dd9d8ea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043959443 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.2043959443
Directory	/workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2359247472
Short name	T1201
Test name
Test status
Simulation time	69552200 ps
CPU time	14.11 seconds
Started	Jul 12 06:43:21 PM PDT 24
Finished	Jul 12 06:43:36 PM PDT 24
Peak memory	263648 kb
Host	smart-48c32554-717e-4a54-bd8c-c7f4ff5c73ef
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359247472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_csr_rw.2359247472
Directory	/workspace/7.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1785589231
Short name	T305
Test name
Test status
Simulation time	54176400 ps
CPU time	13.56 seconds
Started	Jul 12 06:43:25 PM PDT 24
Finished	Jul 12 06:43:40 PM PDT 24
Peak memory	261220 kb
Host	smart-e0c72e12-c413-4156-a968-ddd4305767c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785589231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.1 785589231
Directory	/workspace/7.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2584301483
Short name	T1117
Test name
Test status
Simulation time	675857500 ps
CPU time	34.14 seconds
Started	Jul 12 06:43:24 PM PDT 24
Finished	Jul 12 06:44:00 PM PDT 24
Peak memory	261120 kb
Host	smart-cf1a3036-5f22-4331-9075-d2df6f308958
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584301483 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.2584301483
Directory	/workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2578633331
Short name	T1111
Test name
Test status
Simulation time	21551800 ps
CPU time	15.67 seconds
Started	Jul 12 06:43:14 PM PDT 24
Finished	Jul 12 06:43:32 PM PDT 24
Peak memory	253088 kb
Host	smart-10e49a33-51ea-4c71-b19e-a24989880a83
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578633331 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2578633331
Directory	/workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1650613518
Short name	T1231
Test name
Test status
Simulation time	22978100 ps
CPU time	15.59 seconds
Started	Jul 12 06:43:11 PM PDT 24
Finished	Jul 12 06:43:30 PM PDT 24
Peak memory	253076 kb
Host	smart-691fad2b-f514-4af3-acf2-a1bec9437f73
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650613518 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.1650613518
Directory	/workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.77017247
Short name	T216
Test name
Test status
Simulation time	31646900 ps
CPU time	16.46 seconds
Started	Jul 12 06:43:24 PM PDT 24
Finished	Jul 12 06:43:42 PM PDT 24
Peak memory	263700 kb
Host	smart-b78f5d27-94b7-4526-a117-6b249c3ef5c8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77017247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.77017247
Directory	/workspace/7.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3562177
Short name	T1228
Test name
Test status
Simulation time	63223500 ps
CPU time	20.42 seconds
Started	Jul 12 06:43:27 PM PDT 24
Finished	Jul 12 06:43:50 PM PDT 24
Peak memory	271904 kb
Host	smart-46478185-0c90-472c-9d9b-b7302e1464ef
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.3562177
Directory	/workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3637122400
Short name	T1189
Test name
Test status
Simulation time	193625100 ps
CPU time	14.94 seconds
Started	Jul 12 06:43:28 PM PDT 24
Finished	Jul 12 06:43:45 PM PDT 24
Peak memory	261188 kb
Host	smart-31bb9a18-0d39-44dd-8be9-096b0dbbfc92
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637122400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_csr_rw.3637122400
Directory	/workspace/8.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.233566391
Short name	T1151
Test name
Test status
Simulation time	29162500 ps
CPU time	13.47 seconds
Started	Jul 12 06:43:25 PM PDT 24
Finished	Jul 12 06:43:39 PM PDT 24
Peak memory	261244 kb
Host	smart-504fe84c-ee70-4006-bdce-d9f609c6c84c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233566391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.233566391
Directory	/workspace/8.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1463329168
Short name	T1218
Test name
Test status
Simulation time	886409300 ps
CPU time	34.86 seconds
Started	Jul 12 06:43:27 PM PDT 24
Finished	Jul 12 06:44:03 PM PDT 24
Peak memory	263728 kb
Host	smart-56db6379-e39c-40cc-8801-05659a2c2825
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463329168 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.1463329168
Directory	/workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2524125877
Short name	T1208
Test name
Test status
Simulation time	13747700 ps
CPU time	16.26 seconds
Started	Jul 12 06:43:16 PM PDT 24
Finished	Jul 12 06:43:34 PM PDT 24
Peak memory	253000 kb
Host	smart-cb1d8989-c7d1-4913-8e9f-69f6d4a08acb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524125877 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.2524125877
Directory	/workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.452871146
Short name	T1112
Test name
Test status
Simulation time	22681800 ps
CPU time	13.36 seconds
Started	Jul 12 06:43:23 PM PDT 24
Finished	Jul 12 06:43:37 PM PDT 24
Peak memory	253000 kb
Host	smart-f6c292fd-4d7f-4613-826b-95972ad898d1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452871146 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.452871146
Directory	/workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3781116267
Short name	T1149
Test name
Test status
Simulation time	61256300 ps
CPU time	16.47 seconds
Started	Jul 12 06:43:30 PM PDT 24
Finished	Jul 12 06:43:49 PM PDT 24
Peak memory	263708 kb
Host	smart-5cccb348-3d0a-4539-9905-8083ef6f926e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781116267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3 781116267
Directory	/workspace/8.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3674600365
Short name	T250
Test name
Test status
Simulation time	669687100 ps
CPU time	748.43 seconds
Started	Jul 12 06:43:19 PM PDT 24
Finished	Jul 12 06:55:49 PM PDT 24
Peak memory	263756 kb
Host	smart-57e87854-d509-4b2c-a3ec-b882521c91ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674600365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl _tl_intg_err.3674600365
Directory	/workspace/8.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1434026124
Short name	T1220
Test name
Test status
Simulation time	100622800 ps
CPU time	19.56 seconds
Started	Jul 12 06:43:26 PM PDT 24
Finished	Jul 12 06:43:47 PM PDT 24
Peak memory	271528 kb
Host	smart-cc33518a-63e2-43a1-b410-ce03a3bc04ca
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434026124 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.1434026124
Directory	/workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2338841638
Short name	T1256
Test name
Test status
Simulation time	174306300 ps
CPU time	17.07 seconds
Started	Jul 12 06:43:26 PM PDT 24
Finished	Jul 12 06:43:45 PM PDT 24
Peak memory	261352 kb
Host	smart-92825459-bb37-4235-a2b2-275273f183eb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338841638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.flash_ctrl_csr_rw.2338841638
Directory	/workspace/9.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2949623492
Short name	T1249
Test name
Test status
Simulation time	963196000 ps
CPU time	20.04 seconds
Started	Jul 12 06:43:33 PM PDT 24
Finished	Jul 12 06:43:55 PM PDT 24
Peak memory	263696 kb
Host	smart-ee49db1f-7f4c-45b5-90ac-fc0ce4e12f83
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949623492 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.2949623492
Directory	/workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2934068959
Short name	T1227
Test name
Test status
Simulation time	30846300 ps
CPU time	15.93 seconds
Started	Jul 12 06:43:20 PM PDT 24
Finished	Jul 12 06:43:37 PM PDT 24
Peak memory	253072 kb
Host	smart-d29c891e-132b-4b71-9237-2ffd6875c96a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934068959 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.2934068959
Directory	/workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3979684972
Short name	T1113
Test name
Test status
Simulation time	46886900 ps
CPU time	15.73 seconds
Started	Jul 12 06:43:34 PM PDT 24
Finished	Jul 12 06:43:52 PM PDT 24
Peak memory	252980 kb
Host	smart-78d2be7c-067b-4cdd-84db-c81eef787459
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979684972 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.3979684972
Directory	/workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3187735002
Short name	T1241
Test name
Test status
Simulation time	130825000 ps
CPU time	20.79 seconds
Started	Jul 12 06:43:16 PM PDT 24
Finished	Jul 12 06:43:38 PM PDT 24
Peak memory	263588 kb
Host	smart-fd24ea9c-1cf5-4631-a29c-a0f2f3e1836f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187735002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.3 187735002
Directory	/workspace/9.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.484913040
Short name	T331
Test name
Test status
Simulation time	497972600 ps
CPU time	461.01 seconds
Started	Jul 12 06:43:17 PM PDT 24
Finished	Jul 12 06:50:59 PM PDT 24
Peak memory	263724 kb
Host	smart-8b70097c-3922-429c-b411-095dcb88f6cc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484913040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ tl_intg_err.484913040
Directory	/workspace/9.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_config_regwen.1013786415
Short name	T1047
Test name
Test status
Simulation time	65382600 ps
CPU time	13.88 seconds
Started	Jul 12 07:08:50 PM PDT 24
Finished	Jul 12 07:09:15 PM PDT 24
Peak memory	261616 kb
Host	smart-afa19840-1cc5-4285-a5bd-2aba00e6c285
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013786415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .flash_ctrl_config_regwen.1013786415
Directory	/workspace/0.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/0.flash_ctrl_connect.1987829953
Short name	T1065
Test name
Test status
Simulation time	24876800 ps
CPU time	13.82 seconds
Started	Jul 12 07:08:49 PM PDT 24
Finished	Jul 12 07:09:12 PM PDT 24
Peak memory	274852 kb
Host	smart-414c8345-9e8a-4eb7-b704-653b2afe6fb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987829953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.1987829953
Directory	/workspace/0.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/0.flash_ctrl_disable.4294798977
Short name	T633
Test name
Test status
Simulation time	18131900 ps
CPU time	22 seconds
Started	Jul 12 07:08:53 PM PDT 24
Finished	Jul 12 07:09:25 PM PDT 24
Peak memory	265628 kb
Host	smart-1ba956ae-00b5-4d79-a917-b3a00a83f2f2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294798977 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_disable.4294798977
Directory	/workspace/0.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_erase_suspend.3838365494
Short name	T181
Test name
Test status
Simulation time	2901625600 ps
CPU time	363.75 seconds
Started	Jul 12 07:08:33 PM PDT 24
Finished	Jul 12 07:14:42 PM PDT 24
Peak memory	263476 kb
Host	smart-7748830c-95ae-4249-a019-ec68b960bd5d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3838365494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3838365494
Directory	/workspace/0.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fetch_code.848722240
Short name	T851
Test name
Test status
Simulation time	1781166200 ps
CPU time	21.55 seconds
Started	Jul 12 07:08:33 PM PDT 24
Finished	Jul 12 07:08:59 PM PDT 24
Peak memory	263524 kb
Host	smart-8f792ece-69e2-44ef-827b-ceddb623508b
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848722240 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.848722240
Directory	/workspace/0.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fs_sup.1897393977
Short name	T259
Test name
Test status
Simulation time	701520500 ps
CPU time	41.95 seconds
Started	Jul 12 07:08:56 PM PDT 24
Finished	Jul 12 07:09:47 PM PDT 24
Peak memory	265288 kb
Host	smart-00d40854-5a2c-47aa-8867-e0bc5c1b7759
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897393977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.flash_ctrl_fs_sup.1897393977
Directory	/workspace/0.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/0.flash_ctrl_full_mem_access.2124705369
Short name	T121
Test name
Test status
Simulation time	163369244400 ps
CPU time	4641.1 seconds
Started	Jul 12 07:08:34 PM PDT 24
Finished	Jul 12 08:26:01 PM PDT 24
Peak memory	265036 kb
Host	smart-a599b608-9f93-4741-ab07-98e6f02535d4
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124705369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_full_mem_access.2124705369
Directory	/workspace/0.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_addr_infection.3595067118
Short name	T522
Test name
Test status
Simulation time	66008900 ps
CPU time	27.09 seconds
Started	Jul 12 07:08:53 PM PDT 24
Finished	Jul 12 07:09:31 PM PDT 24
Peak memory	268476 kb
Host	smart-cacf43a4-fdd9-4f90-803c-ffd840bc5249
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595067118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_host_addr_infection.3595067118
Directory	/workspace/0.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_dir_rd.2624913359
Short name	T669
Test name
Test status
Simulation time	198072700 ps
CPU time	88.42 seconds
Started	Jul 12 07:08:33 PM PDT 24
Finished	Jul 12 07:10:06 PM PDT 24
Peak memory	262532 kb
Host	smart-3143239f-5088-4d5c-b1a4-fcd5cab7a38f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2624913359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2624913359
Directory	/workspace/0.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1050483754
Short name	T1015
Test name
Test status
Simulation time	10012156100 ps
CPU time	326.27 seconds
Started	Jul 12 07:08:53 PM PDT 24
Finished	Jul 12 07:14:30 PM PDT 24
Peak memory	317276 kb
Host	smart-24744416-9c97-447e-bba3-67fad990983b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050483754 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.1050483754
Directory	/workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma.3396058733
Short name	T672
Test name
Test status
Simulation time	120746543000 ps
CPU time	2191.72 seconds
Started	Jul 12 07:08:34 PM PDT 24
Finished	Jul 12 07:45:11 PM PDT 24
Peak memory	260652 kb
Host	smart-fdaaf297-5cb0-4eec-afa2-fd1fdc045e8a
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396058733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.flash_ctrl_hw_rma.3396058733
Directory	/workspace/0.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3977401882
Short name	T702
Test name
Test status
Simulation time	80133419900 ps
CPU time	833.61 seconds
Started	Jul 12 07:08:35 PM PDT 24
Finished	Jul 12 07:22:34 PM PDT 24
Peak memory	264464 kb
Host	smart-5b20ed76-8db1-4bdc-b27c-3295f3c19f8e
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977401882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.flash_ctrl_hw_rma_reset.3977401882
Directory	/workspace/0.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_sec_otp.3305719273
Short name	T918
Test name
Test status
Simulation time	2817602100 ps
CPU time	86.62 seconds
Started	Jul 12 07:08:34 PM PDT 24
Finished	Jul 12 07:10:06 PM PDT 24
Peak memory	260404 kb
Host	smart-cf65937d-33da-43e4-9115-56bf05ddcd97
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305719273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h w_sec_otp.3305719273
Directory	/workspace/0.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_integrity.1458438126
Short name	T997
Test name
Test status
Simulation time	21722957900 ps
CPU time	536.59 seconds
Started	Jul 12 07:08:43 PM PDT 24
Finished	Jul 12 07:17:49 PM PDT 24
Peak memory	332460 kb
Host	smart-d52718c1-23e1-4607-98f6-0c4e77e5edab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458438126 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_integrity.1458438126
Directory	/workspace/0.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd.1686154401
Short name	T1058
Test name
Test status
Simulation time	689302600 ps
CPU time	153.74 seconds
Started	Jul 12 07:08:43 PM PDT 24
Finished	Jul 12 07:11:26 PM PDT 24
Peak memory	293992 kb
Host	smart-05bdf012-579e-4fd8-a77d-2c4c227b173a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686154401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_intr_rd.1686154401
Directory	/workspace/0.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.341321998
Short name	T28
Test name
Test status
Simulation time	45400527000 ps
CPU time	188.62 seconds
Started	Jul 12 07:08:43 PM PDT 24
Finished	Jul 12 07:12:00 PM PDT 24
Peak memory	265252 kb
Host	smart-a15fcfda-2170-44d5-907c-b92d6207cf17
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341 321998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.341321998
Directory	/workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_invalid_op.3758169131
Short name	T555
Test name
Test status
Simulation time	8695129600 ps
CPU time	73.64 seconds
Started	Jul 12 07:08:39 PM PDT 24
Finished	Jul 12 07:09:59 PM PDT 24
Peak memory	263192 kb
Host	smart-e1fb58dc-1f15-4392-865c-d40a8bc6d142
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758169131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.3758169131
Directory	/workspace/0.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1813658310
Short name	T921
Test name
Test status
Simulation time	22918100 ps
CPU time	13.8 seconds
Started	Jul 12 07:08:53 PM PDT 24
Finished	Jul 12 07:09:17 PM PDT 24
Peak memory	259964 kb
Host	smart-6c137132-c863-45a9-9268-8e17330dcee8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813658310 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1813658310
Directory	/workspace/0.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mid_op_rst.3744448716
Short name	T80
Test name
Test status
Simulation time	3965740500 ps
CPU time	75.62 seconds
Started	Jul 12 07:08:39 PM PDT 24
Finished	Jul 12 07:10:01 PM PDT 24
Peak memory	260668 kb
Host	smart-3ebba0a6-9aaf-44e0-a1ed-f8ae97d708d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744448716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.3744448716
Directory	/workspace/0.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mp_regions.3203176449
Short name	T141
Test name
Test status
Simulation time	43389410100 ps
CPU time	231.81 seconds
Started	Jul 12 07:08:34 PM PDT 24
Finished	Jul 12 07:12:31 PM PDT 24
Peak memory	274700 kb
Host	smart-2f99ebf5-5538-47b4-ba38-d9ac200687a6
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203176449 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.3203176449
Directory	/workspace/0.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/0.flash_ctrl_otp_reset.1289168178
Short name	T990
Test name
Test status
Simulation time	36425000 ps
CPU time	135.2 seconds
Started	Jul 12 07:08:36 PM PDT 24
Finished	Jul 12 07:10:57 PM PDT 24
Peak memory	265064 kb
Host	smart-11863d97-7771-43f9-8b0d-77b2b964d975
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289168178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot p_reset.1289168178
Directory	/workspace/0.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb.1774908727
Short name	T913
Test name
Test status
Simulation time	57905600 ps
CPU time	239.49 seconds
Started	Jul 12 07:08:35 PM PDT 24
Finished	Jul 12 07:12:40 PM PDT 24
Peak memory	263152 kb
Host	smart-b83788fe-93ff-41f3-a3c9-d06f4603fbd6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1774908727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.1774908727
Directory	/workspace/0.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.2709163896
Short name	T13
Test name
Test status
Simulation time	14805100 ps
CPU time	13.93 seconds
Started	Jul 12 07:08:50 PM PDT 24
Finished	Jul 12 07:09:15 PM PDT 24
Peak memory	265504 kb
Host	smart-0216548f-ef22-4ac7-a8ef-4391b07c5f4d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709163896 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2709163896
Directory	/workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_prog_reset.1500708319
Short name	T1100
Test name
Test status
Simulation time	20968600 ps
CPU time	13.69 seconds
Started	Jul 12 07:08:48 PM PDT 24
Finished	Jul 12 07:09:11 PM PDT 24
Peak memory	265176 kb
Host	smart-2974082e-3b33-4151-85fb-fcd06619e501
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500708319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.flash_ctrl_prog_reset.1500708319
Directory	/workspace/0.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rand_ops.1532539805
Short name	T657
Test name
Test status
Simulation time	41910600 ps
CPU time	150.91 seconds
Started	Jul 12 07:08:35 PM PDT 24
Finished	Jul 12 07:11:12 PM PDT 24
Peak memory	270612 kb
Host	smart-1f46e003-cf10-4f5f-997a-936cdf2150ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532539805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.1532539805
Directory	/workspace/0.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.2143834784
Short name	T386
Test name
Test status
Simulation time	52777100 ps
CPU time	101.67 seconds
Started	Jul 12 07:08:39 PM PDT 24
Finished	Jul 12 07:10:27 PM PDT 24
Peak memory	262820 kb
Host	smart-02255cc3-efad-4af3-8cad-2b56821baf94
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2143834784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.2143834784
Directory	/workspace/0.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_intg.2151958507
Short name	T319
Test name
Test status
Simulation time	63163300 ps
CPU time	31.07 seconds
Started	Jul 12 07:08:50 PM PDT 24
Finished	Jul 12 07:09:31 PM PDT 24
Peak memory	275952 kb
Host	smart-ca700960-20e1-40d0-a446-944fcf2a810b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151958507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.flash_ctrl_rd_intg.2151958507
Directory	/workspace/0.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_ooo.2990438936
Short name	T885
Test name
Test status
Simulation time	59887300 ps
CPU time	43.82 seconds
Started	Jul 12 07:08:51 PM PDT 24
Finished	Jul 12 07:09:45 PM PDT 24
Peak memory	276724 kb
Host	smart-2a15ce24-634e-42f5-9f6a-793efa0ead74
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990438936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_rd_ooo.2990438936
Directory	/workspace/0.flash_ctrl_rd_ooo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_re_evict.3146376607
Short name	T264
Test name
Test status
Simulation time	69019900 ps
CPU time	33.99 seconds
Started	Jul 12 07:08:51 PM PDT 24
Finished	Jul 12 07:09:35 PM PDT 24
Peak memory	275668 kb
Host	smart-19bfda48-1080-4bc2-97aa-73b1c5ed5589
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146376607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_re_evict.3146376607
Directory	/workspace/0.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep.3122477311
Short name	T557
Test name
Test status
Simulation time	106751500 ps
CPU time	14.22 seconds
Started	Jul 12 07:08:47 PM PDT 24
Finished	Jul 12 07:09:10 PM PDT 24
Peak memory	258884 kb
Host	smart-b6460d95-e604-4f9e-ae95-b3e43408e1b4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3122477311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep .3122477311
Directory	/workspace/0.flash_ctrl_read_word_sweep/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.2404825281
Short name	T193
Test name
Test status
Simulation time	19359000 ps
CPU time	21.9 seconds
Started	Jul 12 07:08:43 PM PDT 24
Finished	Jul 12 07:09:14 PM PDT 24
Peak memory	265400 kb
Host	smart-944345ed-d85d-47bb-835e-a618a6b7c566
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404825281 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.2404825281
Directory	/workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.2637928493
Short name	T35
Test name
Test status
Simulation time	46279000 ps
CPU time	23.08 seconds
Started	Jul 12 07:08:44 PM PDT 24
Finished	Jul 12 07:09:16 PM PDT 24
Peak memory	265192 kb
Host	smart-06a492fc-d2da-44f3-95d4-01008a5a7f56
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637928493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl ash_ctrl_read_word_sweep_serr.2637928493
Directory	/workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rma_err.2087427893
Short name	T164
Test name
Test status
Simulation time	80590478900 ps
CPU time	991.03 seconds
Started	Jul 12 07:08:51 PM PDT 24
Finished	Jul 12 07:25:32 PM PDT 24
Peak memory	263632 kb
Host	smart-70b7c8fc-3ffb-491b-8d29-5b242fafdd81
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087427893 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2087427893
Directory	/workspace/0.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro.3964339637
Short name	T908
Test name
Test status
Simulation time	897757100 ps
CPU time	104.3 seconds
Started	Jul 12 07:08:49 PM PDT 24
Finished	Jul 12 07:10:43 PM PDT 24
Peak memory	280944 kb
Host	smart-c5c6c45c-e7e9-4bf8-8191-72e2e693e125
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964339637 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_ro.3964339637
Directory	/workspace/0.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_derr.4162925308
Short name	T233
Test name
Test status
Simulation time	567412200 ps
CPU time	143.05 seconds
Started	Jul 12 07:08:42 PM PDT 24
Finished	Jul 12 07:11:13 PM PDT 24
Peak memory	281784 kb
Host	smart-ee05012f-d603-488c-8505-2e0fdf4c0f17
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4162925308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.4162925308
Directory	/workspace/0.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_serr.3616010080
Short name	T198
Test name
Test status
Simulation time	3634411600 ps
CPU time	169.51 seconds
Started	Jul 12 07:08:43 PM PDT 24
Finished	Jul 12 07:11:42 PM PDT 24
Peak memory	281804 kb
Host	smart-517e4d83-86b2-4ef0-b85a-3ddc71a95781
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616010080 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.3616010080
Directory	/workspace/0.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw.1243546138
Short name	T796
Test name
Test status
Simulation time	4206953200 ps
CPU time	630.78 seconds
Started	Jul 12 07:08:48 PM PDT 24
Finished	Jul 12 07:19:28 PM PDT 24
Peak memory	310776 kb
Host	smart-bc74d9a1-e796-4dd4-b1b4-b9ebeb112f1a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243546138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.flash_ctrl_rw.1243546138
Directory	/workspace/0.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict.2822998902
Short name	T1022
Test name
Test status
Simulation time	28667000 ps
CPU time	30.9 seconds
Started	Jul 12 07:08:43 PM PDT 24
Finished	Jul 12 07:09:23 PM PDT 24
Peak memory	275624 kb
Host	smart-9795e20e-ebf5-4511-b22f-6469179a6da7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822998902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_rw_evict.2822998902
Directory	/workspace/0.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.1411185853
Short name	T681
Test name
Test status
Simulation time	42132200 ps
CPU time	31.23 seconds
Started	Jul 12 07:08:52 PM PDT 24
Finished	Jul 12 07:09:34 PM PDT 24
Peak memory	268464 kb
Host	smart-582ac43d-dccc-4900-b06e-8cc4efd86446
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411185853 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.1411185853
Directory	/workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_address.4075259458
Short name	T134
Test name
Test status
Simulation time	837884700 ps
CPU time	93.14 seconds
Started	Jul 12 07:08:48 PM PDT 24
Finished	Jul 12 07:10:31 PM PDT 24
Peak memory	265444 kb
Host	smart-5254d967-34e0-4464-bac0-bab7fa90407d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075259458 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_serr_address.4075259458
Directory	/workspace/0.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_counter.4137692352
Short name	T869
Test name
Test status
Simulation time	4407103700 ps
CPU time	87.29 seconds
Started	Jul 12 07:08:43 PM PDT 24
Finished	Jul 12 07:10:19 PM PDT 24
Peak memory	276672 kb
Host	smart-10b3a9a8-418f-4873-9ad0-bd1b4c2066ae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137692352 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_serr_counter.4137692352
Directory	/workspace/0.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke.1366966010
Short name	T104
Test name
Test status
Simulation time	51909300 ps
CPU time	122.45 seconds
Started	Jul 12 07:08:38 PM PDT 24
Finished	Jul 12 07:10:47 PM PDT 24
Peak memory	268736 kb
Host	smart-f7e236e4-c43c-4b85-8a2c-83ed884d0197
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1366966010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.1366966010
Directory	/workspace/0.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke_hw.1654391000
Short name	T1097
Test name
Test status
Simulation time	20370500 ps
CPU time	23.44 seconds
Started	Jul 12 07:08:38 PM PDT 24
Finished	Jul 12 07:09:08 PM PDT 24
Peak memory	259684 kb
Host	smart-b7d24535-8bdf-4948-ba10-f2e9367baf4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654391000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1654391000
Directory	/workspace/0.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_stress_all.156649453
Short name	T494
Test name
Test status
Simulation time	147287100 ps
CPU time	815.93 seconds
Started	Jul 12 07:08:51 PM PDT 24
Finished	Jul 12 07:22:37 PM PDT 24
Peak memory	285944 kb
Host	smart-db74a9bf-e4cf-495a-a701-160b02cee7be
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156649453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress _all.156649453
Directory	/workspace/0.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sw_op.2534171915
Short name	T968
Test name
Test status
Simulation time	90585900 ps
CPU time	24.26 seconds
Started	Jul 12 07:08:39 PM PDT 24
Finished	Jul 12 07:09:11 PM PDT 24
Peak memory	262432 kb
Host	smart-0b72a740-13e7-47db-a250-a26ad9623165
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534171915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.2534171915
Directory	/workspace/0.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wo.4173499792
Short name	T661
Test name
Test status
Simulation time	3958812000 ps
CPU time	266.25 seconds
Started	Jul 12 07:08:34 PM PDT 24
Finished	Jul 12 07:13:06 PM PDT 24
Peak memory	260120 kb
Host	smart-7fc4ea1a-f32b-45f3-8bef-9d4327703aa4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173499792 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.flash_ctrl_wo.4173499792
Directory	/workspace/0.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wr_intg.1836316823
Short name	T7
Test name
Test status
Simulation time	66607600 ps
CPU time	15.87 seconds
Started	Jul 12 07:08:48 PM PDT 24
Finished	Jul 12 07:09:14 PM PDT 24
Peak memory	265008 kb
Host	smart-425d160b-442d-42eb-8f77-07c400137a0e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836316823 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.1836316823
Directory	/workspace/0.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_write_word_sweep.420762064
Short name	T922
Test name
Test status
Simulation time	39628400 ps
CPU time	15.39 seconds
Started	Jul 12 07:08:35 PM PDT 24
Finished	Jul 12 07:08:57 PM PDT 24
Peak memory	258860 kb
Host	smart-4df11c2c-572a-464b-9225-534140473701
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=420762064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swee p.420762064
Directory	/workspace/0.flash_ctrl_write_word_sweep/latest

Test location	/workspace/coverage/default/1.flash_ctrl_access_after_disable.3925417805
Short name	T9
Test name
Test status
Simulation time	42477600 ps
CPU time	13.57 seconds
Started	Jul 12 07:09:14 PM PDT 24
Finished	Jul 12 07:09:33 PM PDT 24
Peak memory	265340 kb
Host	smart-e3d4d465-2532-427b-b4e5-6dded4f5b708
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925417805 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3925417805
Directory	/workspace/1.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_alert_test.938885594
Short name	T973
Test name
Test status
Simulation time	194015600 ps
CPU time	13.72 seconds
Started	Jul 12 07:09:25 PM PDT 24
Finished	Jul 12 07:09:47 PM PDT 24
Peak memory	258324 kb
Host	smart-82ae233b-697b-4913-8c36-233f12746e16
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938885594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.938885594
Directory	/workspace/1.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.flash_ctrl_config_regwen.2583223468
Short name	T765
Test name
Test status
Simulation time	66383900 ps
CPU time	13.9 seconds
Started	Jul 12 07:09:27 PM PDT 24
Finished	Jul 12 07:09:48 PM PDT 24
Peak memory	265020 kb
Host	smart-e9096842-ba26-4bd4-9cba-776d4b5c13d5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583223468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .flash_ctrl_config_regwen.2583223468
Directory	/workspace/1.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/1.flash_ctrl_connect.950199338
Short name	T630
Test name
Test status
Simulation time	44664300 ps
CPU time	13.29 seconds
Started	Jul 12 07:09:15 PM PDT 24
Finished	Jul 12 07:09:35 PM PDT 24
Peak memory	274920 kb
Host	smart-b7257870-4c40-48ee-8e9f-0b71b9f80c53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=950199338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.950199338
Directory	/workspace/1.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/1.flash_ctrl_disable.2732764633
Short name	T44
Test name
Test status
Simulation time	10446600 ps
CPU time	20.82 seconds
Started	Jul 12 07:09:14 PM PDT 24
Finished	Jul 12 07:09:40 PM PDT 24
Peak memory	273596 kb
Host	smart-8bb10b76-80ec-4901-9506-33bc4ae224cf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732764633 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_disable.2732764633
Directory	/workspace/1.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_erase_suspend.1865422385
Short name	T758
Test name
Test status
Simulation time	5677862100 ps
CPU time	294.42 seconds
Started	Jul 12 07:08:52 PM PDT 24
Finished	Jul 12 07:13:57 PM PDT 24
Peak memory	263472 kb
Host	smart-f1b0fac4-0656-4897-afdd-a9c906126e52
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1865422385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.1865422385
Directory	/workspace/1.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_mp.136227805
Short name	T237
Test name
Test status
Simulation time	35313791200 ps
CPU time	2240.95 seconds
Started	Jul 12 07:09:01 PM PDT 24
Finished	Jul 12 07:46:28 PM PDT 24
Peak memory	262844 kb
Host	smart-8492b0d1-1ec1-4291-9ba5-dc2aaa608f60
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=136227805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.136227805
Directory	/workspace/1.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_type.647119356
Short name	T74
Test name
Test status
Simulation time	391757900 ps
CPU time	2070.39 seconds
Started	Jul 12 07:09:01 PM PDT 24
Finished	Jul 12 07:43:38 PM PDT 24
Peak memory	265204 kb
Host	smart-4cc8faea-1f10-4978-a3af-f721edb17417
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647119356 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.flash_ctrl_error_prog_type.647119356
Directory	/workspace/1.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_win.787209216
Short name	T1029
Test name
Test status
Simulation time	790443200 ps
CPU time	1091.46 seconds
Started	Jul 12 07:08:58 PM PDT 24
Finished	Jul 12 07:27:17 PM PDT 24
Peak memory	272904 kb
Host	smart-87fbb33a-f575-40de-a865-1e64441fee7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=787209216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.787209216
Directory	/workspace/1.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fs_sup.3437246875
Short name	T768
Test name
Test status
Simulation time	1656272800 ps
CPU time	45.2 seconds
Started	Jul 12 07:09:15 PM PDT 24
Finished	Jul 12 07:10:06 PM PDT 24
Peak memory	263208 kb
Host	smart-9b86b8b4-b704-4c31-8c6e-6a81fec3a516
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437246875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.flash_ctrl_fs_sup.3437246875
Directory	/workspace/1.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/1.flash_ctrl_full_mem_access.3662715085
Short name	T122
Test name
Test status
Simulation time	81387504900 ps
CPU time	2561.25 seconds
Started	Jul 12 07:08:58 PM PDT 24
Finished	Jul 12 07:51:47 PM PDT 24
Peak memory	265076 kb
Host	smart-9d245c33-c702-475d-b627-260f04d5ba9c
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662715085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c trl_full_mem_access.3662715085
Directory	/workspace/1.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_addr_infection.2993087485
Short name	T700
Test name
Test status
Simulation time	153859300 ps
CPU time	30.3 seconds
Started	Jul 12 07:09:26 PM PDT 24
Finished	Jul 12 07:10:04 PM PDT 24
Peak memory	275656 kb
Host	smart-20879c61-ff8b-445c-95f8-d99bc5bbe048
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993087485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_host_addr_infection.2993087485
Directory	/workspace/1.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_dir_rd.3523523009
Short name	T866
Test name
Test status
Simulation time	330336200 ps
CPU time	70.29 seconds
Started	Jul 12 07:08:52 PM PDT 24
Finished	Jul 12 07:10:13 PM PDT 24
Peak memory	265252 kb
Host	smart-d6bdf042-562d-438a-b41f-5fd13be3b3c5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3523523009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3523523009
Directory	/workspace/1.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.1209177672
Short name	T202
Test name
Test status
Simulation time	50473400 ps
CPU time	13.46 seconds
Started	Jul 12 07:09:28 PM PDT 24
Finished	Jul 12 07:09:48 PM PDT 24
Peak memory	260384 kb
Host	smart-c5352fa5-774b-4780-8d60-1cc8e9fc8798
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209177672 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.1209177672
Directory	/workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma.2897265809
Short name	T30
Test name
Test status
Simulation time	167290203800 ps
CPU time	2065.39 seconds
Started	Jul 12 07:08:50 PM PDT 24
Finished	Jul 12 07:43:26 PM PDT 24
Peak memory	260648 kb
Host	smart-13e56641-b649-4609-8175-8c9c84db4b88
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897265809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.flash_ctrl_hw_rma.2897265809
Directory	/workspace/1.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2199692378
Short name	T507
Test name
Test status
Simulation time	40124715100 ps
CPU time	845.37 seconds
Started	Jul 12 07:08:56 PM PDT 24
Finished	Jul 12 07:23:10 PM PDT 24
Peak memory	260784 kb
Host	smart-88a2e0c5-0564-4805-bc48-25068b108045
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199692378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.flash_ctrl_hw_rma_reset.2199692378
Directory	/workspace/1.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_integrity.3797717277
Short name	T774
Test name
Test status
Simulation time	7925064300 ps
CPU time	682.02 seconds
Started	Jul 12 07:09:14 PM PDT 24
Finished	Jul 12 07:20:42 PM PDT 24
Peak memory	332580 kb
Host	smart-7ead8379-df5b-4d3a-91f1-25ba3555b5ae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797717277 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_integrity.3797717277
Directory	/workspace/1.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd.1994757014
Short name	T792
Test name
Test status
Simulation time	3403902600 ps
CPU time	220.22 seconds
Started	Jul 12 07:09:17 PM PDT 24
Finished	Jul 12 07:13:06 PM PDT 24
Peak memory	291408 kb
Host	smart-8764689b-9c4d-4267-836f-dda19f9df3e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994757014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_intr_rd.1994757014
Directory	/workspace/1.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.13717470
Short name	T818
Test name
Test status
Simulation time	13130378500 ps
CPU time	299.61 seconds
Started	Jul 12 07:09:15 PM PDT 24
Finished	Jul 12 07:14:22 PM PDT 24
Peak memory	284912 kb
Host	smart-6029113c-41a0-4b08-b318-1e9f8d299caf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13717470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.13717470
Directory	/workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr.1462811125
Short name	T1096
Test name
Test status
Simulation time	2279698000 ps
CPU time	69.83 seconds
Started	Jul 12 07:09:14 PM PDT 24
Finished	Jul 12 07:10:29 PM PDT 24
Peak memory	265192 kb
Host	smart-8bd8dbc8-62db-4667-b93d-29b9357d6aae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462811125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_intr_wr.1462811125
Directory	/workspace/1.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3043575988
Short name	T1070
Test name
Test status
Simulation time	41262585800 ps
CPU time	173.51 seconds
Started	Jul 12 07:09:14 PM PDT 24
Finished	Jul 12 07:12:14 PM PDT 24
Peak memory	265192 kb
Host	smart-53b98548-ea54-4b11-954c-a0fdd5d09de4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304 3575988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.3043575988
Directory	/workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_invalid_op.113711333
Short name	T988
Test name
Test status
Simulation time	1625024000 ps
CPU time	66.31 seconds
Started	Jul 12 07:09:00 PM PDT 24
Finished	Jul 12 07:10:13 PM PDT 24
Peak memory	262652 kb
Host	smart-7c3be6b2-f37f-4da2-a56b-8cb9973ba8c4
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113711333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.113711333
Directory	/workspace/1.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_lcmgr_intg.355854324
Short name	T472
Test name
Test status
Simulation time	26044700 ps
CPU time	13.35 seconds
Started	Jul 12 07:09:23 PM PDT 24
Finished	Jul 12 07:09:45 PM PDT 24
Peak memory	264992 kb
Host	smart-23be7ca3-04cf-4691-a62b-f9a3ed5160e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355854324 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.355854324
Directory	/workspace/1.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mid_op_rst.3595438190
Short name	T173
Test name
Test status
Simulation time	3207923800 ps
CPU time	74.86 seconds
Started	Jul 12 07:09:00 PM PDT 24
Finished	Jul 12 07:10:21 PM PDT 24
Peak memory	260492 kb
Host	smart-c3bda8a2-3782-4931-b7cc-b0fa4f7f6b99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595438190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.3595438190
Directory	/workspace/1.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mp_regions.2566267704
Short name	T518
Test name
Test status
Simulation time	21196801300 ps
CPU time	134.55 seconds
Started	Jul 12 07:08:52 PM PDT 24
Finished	Jul 12 07:11:17 PM PDT 24
Peak memory	265104 kb
Host	smart-411943cb-386e-4698-b71e-a7e778653ba6
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566267704 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.2566267704
Directory	/workspace/1.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/1.flash_ctrl_oversize_error.570988616
Short name	T566
Test name
Test status
Simulation time	6056846400 ps
CPU time	225.26 seconds
Started	Jul 12 07:09:10 PM PDT 24
Finished	Jul 12 07:12:57 PM PDT 24
Peak memory	294932 kb
Host	smart-3fb32c36-b0e7-4b2a-aaa7-1d6b20fa096c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570988616 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.570988616
Directory	/workspace/1.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.3763085683
Short name	T215
Test name
Test status
Simulation time	44604100 ps
CPU time	13.59 seconds
Started	Jul 12 07:09:22 PM PDT 24
Finished	Jul 12 07:09:45 PM PDT 24
Peak memory	261092 kb
Host	smart-1afcaa4a-7b5b-42d6-863d-531b4b736da3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3763085683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.3763085683
Directory	/workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb.1280215596
Short name	T850
Test name
Test status
Simulation time	345750300 ps
CPU time	358.74 seconds
Started	Jul 12 07:08:51 PM PDT 24
Finished	Jul 12 07:15:00 PM PDT 24
Peak memory	263200 kb
Host	smart-47f0a2c8-6ce1-41ae-95b3-93d363dbbc3d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1280215596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.1280215596
Directory	/workspace/1.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_prog_reset.2535050228
Short name	T971
Test name
Test status
Simulation time	242571000 ps
CPU time	20.63 seconds
Started	Jul 12 07:09:16 PM PDT 24
Finished	Jul 12 07:09:43 PM PDT 24
Peak memory	259648 kb
Host	smart-7d657bbe-1512-4ea6-83bf-8772e3aa7072
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535050228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.flash_ctrl_prog_reset.2535050228
Directory	/workspace/1.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rand_ops.269933075
Short name	T979
Test name
Test status
Simulation time	103859700 ps
CPU time	426.55 seconds
Started	Jul 12 07:08:51 PM PDT 24
Finished	Jul 12 07:16:07 PM PDT 24
Peak memory	282976 kb
Host	smart-49672f8c-e5bd-4436-a5da-12c6697b1bb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=269933075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.269933075
Directory	/workspace/1.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_intg.4230751075
Short name	T898
Test name
Test status
Simulation time	218739400 ps
CPU time	31.98 seconds
Started	Jul 12 07:09:15 PM PDT 24
Finished	Jul 12 07:09:54 PM PDT 24
Peak memory	275740 kb
Host	smart-1534815d-aba4-4a1d-a85a-d06457fca78c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230751075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_rd_intg.4230751075
Directory	/workspace/1.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_re_evict.1228080186
Short name	T761
Test name
Test status
Simulation time	220114300 ps
CPU time	33.84 seconds
Started	Jul 12 07:09:14 PM PDT 24
Finished	Jul 12 07:09:54 PM PDT 24
Peak memory	277604 kb
Host	smart-f18a9a4b-7e77-4bd7-9c13-3367dc099c72
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228080186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_re_evict.1228080186
Directory	/workspace/1.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.1340080371
Short name	T189
Test name
Test status
Simulation time	18682200 ps
CPU time	23.37 seconds
Started	Jul 12 07:09:07 PM PDT 24
Finished	Jul 12 07:09:33 PM PDT 24
Peak memory	265396 kb
Host	smart-0d7fcf29-6140-42c3-95a5-236ce4ce4be1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340080371 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.1340080371
Directory	/workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1358820539
Short name	T727
Test name
Test status
Simulation time	29731900 ps
CPU time	22.64 seconds
Started	Jul 12 07:09:06 PM PDT 24
Finished	Jul 12 07:09:32 PM PDT 24
Peak memory	265412 kb
Host	smart-24c50bc2-a9fc-4a15-bbaf-0d8dfe3eb222
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358820539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_read_word_sweep_serr.1358820539
Directory	/workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro.462283176
Short name	T677
Test name
Test status
Simulation time	2268077300 ps
CPU time	145.77 seconds
Started	Jul 12 07:09:00 PM PDT 24
Finished	Jul 12 07:11:32 PM PDT 24
Peak memory	281688 kb
Host	smart-bd63a4bd-3474-443a-9660-32236b32ed07
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462283176 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.flash_ctrl_ro.462283176
Directory	/workspace/1.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_derr.4271833709
Short name	T199
Test name
Test status
Simulation time	880816300 ps
CPU time	161.3 seconds
Started	Jul 12 07:09:07 PM PDT 24
Finished	Jul 12 07:11:51 PM PDT 24
Peak memory	281832 kb
Host	smart-b9bf3388-3f3d-4978-9c45-15e374adb7d6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4271833709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.4271833709
Directory	/workspace/1.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_serr.3602361917
Short name	T1064
Test name
Test status
Simulation time	1878098400 ps
CPU time	122.94 seconds
Started	Jul 12 07:09:08 PM PDT 24
Finished	Jul 12 07:11:13 PM PDT 24
Peak memory	281816 kb
Host	smart-50763cca-adc9-4a97-85ec-2f7ecce69ecb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602361917 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.3602361917
Directory	/workspace/1.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw.3426017543
Short name	T205
Test name
Test status
Simulation time	8033760300 ps
CPU time	564.46 seconds
Started	Jul 12 07:09:02 PM PDT 24
Finished	Jul 12 07:18:32 PM PDT 24
Peak memory	309592 kb
Host	smart-c88d5e80-433a-437c-826e-cb869058580f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426017543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.flash_ctrl_rw.3426017543
Directory	/workspace/1.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_derr.893790481
Short name	T736
Test name
Test status
Simulation time	11026406600 ps
CPU time	759.56 seconds
Started	Jul 12 07:09:06 PM PDT 24
Finished	Jul 12 07:21:49 PM PDT 24
Peak memory	334496 kb
Host	smart-b1734bf9-d6c1-48d8-a014-7e86fffebabc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893790481 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.flash_ctrl_rw_derr.893790481
Directory	/workspace/1.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict.4003096015
Short name	T877
Test name
Test status
Simulation time	47551400 ps
CPU time	30.74 seconds
Started	Jul 12 07:09:14 PM PDT 24
Finished	Jul 12 07:09:50 PM PDT 24
Peak memory	268488 kb
Host	smart-1239e637-8843-418e-9f65-45a383b50642
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003096015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_rw_evict.4003096015
Directory	/workspace/1.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.4177913856
Short name	T106
Test name
Test status
Simulation time	74646900 ps
CPU time	28.5 seconds
Started	Jul 12 07:09:15 PM PDT 24
Finished	Jul 12 07:09:51 PM PDT 24
Peak memory	275636 kb
Host	smart-b9842ce0-8cf2-47e4-9ca7-4954709e228f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177913856 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.4177913856
Directory	/workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_info_access.1464009727
Short name	T900
Test name
Test status
Simulation time	3131990200 ps
CPU time	80.52 seconds
Started	Jul 12 07:09:15 PM PDT 24
Finished	Jul 12 07:10:42 PM PDT 24
Peak memory	259580 kb
Host	smart-292c9356-51b5-4558-a73b-cb1c00958626
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1464009727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1464009727
Directory	/workspace/1.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_address.4278592203
Short name	T544
Test name
Test status
Simulation time	3036122300 ps
CPU time	79.72 seconds
Started	Jul 12 07:09:08 PM PDT 24
Finished	Jul 12 07:10:30 PM PDT 24
Peak memory	273608 kb
Host	smart-8983063c-f60a-455d-846b-2e78a3a14f0d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278592203 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_serr_address.4278592203
Directory	/workspace/1.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_counter.4268016126
Short name	T759
Test name
Test status
Simulation time	1457678500 ps
CPU time	73.81 seconds
Started	Jul 12 07:09:07 PM PDT 24
Finished	Jul 12 07:10:23 PM PDT 24
Peak memory	273480 kb
Host	smart-71ec629b-21d0-4595-8dea-e118b1763949
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268016126 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_serr_counter.4268016126
Directory	/workspace/1.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke.2611804381
Short name	T803
Test name
Test status
Simulation time	29657900 ps
CPU time	100.41 seconds
Started	Jul 12 07:08:52 PM PDT 24
Finished	Jul 12 07:10:43 PM PDT 24
Peak memory	276048 kb
Host	smart-41618367-fdff-430e-8690-fbe2f4a9346c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2611804381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.2611804381
Directory	/workspace/1.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke_hw.1946394434
Short name	T230
Test name
Test status
Simulation time	51295600 ps
CPU time	24.38 seconds
Started	Jul 12 07:08:51 PM PDT 24
Finished	Jul 12 07:09:26 PM PDT 24
Peak memory	259592 kb
Host	smart-9617c558-4637-44c3-a7c6-4a1b49deefa4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946394434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.1946394434
Directory	/workspace/1.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_stress_all.915388416
Short name	T627
Test name
Test status
Simulation time	1652208900 ps
CPU time	873.23 seconds
Started	Jul 12 07:09:16 PM PDT 24
Finished	Jul 12 07:23:59 PM PDT 24
Peak memory	285724 kb
Host	smart-8246f4e0-e1e4-4dd0-89b4-e6c19649ba1a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915388416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress _all.915388416
Directory	/workspace/1.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sw_op.2111360171
Short name	T891
Test name
Test status
Simulation time	40570700 ps
CPU time	26.48 seconds
Started	Jul 12 07:08:52 PM PDT 24
Finished	Jul 12 07:09:29 PM PDT 24
Peak memory	262424 kb
Host	smart-67e3de97-1eac-4eca-bb91-7d55913bbc51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2111360171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2111360171
Directory	/workspace/1.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wo.3805473539
Short name	T1049
Test name
Test status
Simulation time	22914927100 ps
CPU time	149.3 seconds
Started	Jul 12 07:09:02 PM PDT 24
Finished	Jul 12 07:11:37 PM PDT 24
Peak memory	265272 kb
Host	smart-db660215-7e25-4e16-a4c5-82e35244b194
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805473539 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_wo.3805473539
Directory	/workspace/1.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/10.flash_ctrl_alert_test.489098182
Short name	T1052
Test name
Test status
Simulation time	167964900 ps
CPU time	13.52 seconds
Started	Jul 12 07:15:54 PM PDT 24
Finished	Jul 12 07:16:51 PM PDT 24
Peak memory	265168 kb
Host	smart-d3bd4341-1411-455f-9bc1-cbda5346785c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489098182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.489098182
Directory	/workspace/10.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.flash_ctrl_connect.449882663
Short name	T791
Test name
Test status
Simulation time	60261700 ps
CPU time	15.91 seconds
Started	Jul 12 07:15:52 PM PDT 24
Finished	Jul 12 07:16:49 PM PDT 24
Peak memory	284296 kb
Host	smart-4b6f4961-d527-44c6-a51a-d4e2cce9ae75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=449882663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.449882663
Directory	/workspace/10.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1821831765
Short name	T269
Test name
Test status
Simulation time	10024191900 ps
CPU time	75.14 seconds
Started	Jul 12 07:15:55 PM PDT 24
Finished	Jul 12 07:17:52 PM PDT 24
Peak memory	313884 kb
Host	smart-12e8de2c-6639-4a7c-8e64-25db5457afaf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821831765 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.1821831765
Directory	/workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.3010523795
Short name	T771
Test name
Test status
Simulation time	47510600 ps
CPU time	13.54 seconds
Started	Jul 12 07:15:51 PM PDT 24
Finished	Jul 12 07:16:47 PM PDT 24
Peak memory	260228 kb
Host	smart-3791fe4f-42a3-4e8a-aaae-8de5f3cd4ab1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010523795 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.3010523795
Directory	/workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_rma_reset.2941340598
Short name	T690
Test name
Test status
Simulation time	160209015000 ps
CPU time	836.83 seconds
Started	Jul 12 07:15:40 PM PDT 24
Finished	Jul 12 07:30:23 PM PDT 24
Peak memory	264400 kb
Host	smart-d85ffaf7-8d2e-4c0d-95e5-4897818ca9f7
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941340598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.flash_ctrl_hw_rma_reset.2941340598
Directory	/workspace/10.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.537610291
Short name	T826
Test name
Test status
Simulation time	7533141200 ps
CPU time	172.21 seconds
Started	Jul 12 07:15:42 PM PDT 24
Finished	Jul 12 07:19:18 PM PDT 24
Peak memory	263184 kb
Host	smart-5fd51a2a-a397-4192-929a-aed99a9d0cfa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537610291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_h w_sec_otp.537610291
Directory	/workspace/10.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.4007297520
Short name	T317
Test name
Test status
Simulation time	11436993500 ps
CPU time	149.9 seconds
Started	Jul 12 07:15:52 PM PDT 24
Finished	Jul 12 07:19:04 PM PDT 24
Peak memory	294364 kb
Host	smart-5545e53b-4dd6-4538-9f73-639c5caf3e51
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007297520 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.4007297520
Directory	/workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/10.flash_ctrl_invalid_op.376844798
Short name	T228
Test name
Test status
Simulation time	9757338000 ps
CPU time	84.49 seconds
Started	Jul 12 07:15:51 PM PDT 24
Finished	Jul 12 07:17:58 PM PDT 24
Peak memory	263124 kb
Host	smart-80ef39d2-b3b3-47ac-948e-8c5b293f4acc
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376844798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.376844798
Directory	/workspace/10.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/10.flash_ctrl_mp_regions.2840273659
Short name	T239
Test name
Test status
Simulation time	16278093900 ps
CPU time	159.85 seconds
Started	Jul 12 07:15:51 PM PDT 24
Finished	Jul 12 07:19:12 PM PDT 24
Peak memory	265176 kb
Host	smart-7417092e-4f3d-44a4-9109-d4683aca07a9
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840273659 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.2840273659
Directory	/workspace/10.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/10.flash_ctrl_otp_reset.4133392954
Short name	T575
Test name
Test status
Simulation time	39394900 ps
CPU time	133.75 seconds
Started	Jul 12 07:15:54 PM PDT 24
Finished	Jul 12 07:18:50 PM PDT 24
Peak memory	260996 kb
Host	smart-f9209e71-e469-41cb-a25b-0369d0f1fe6a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133392954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o tp_reset.4133392954
Directory	/workspace/10.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_phy_arb.3967011766
Short name	T952
Test name
Test status
Simulation time	2435080500 ps
CPU time	173.41 seconds
Started	Jul 12 07:15:42 PM PDT 24
Finished	Jul 12 07:19:19 PM PDT 24
Peak memory	263224 kb
Host	smart-b777eaa9-e681-486c-8e77-ec5d0ae4fde0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3967011766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3967011766
Directory	/workspace/10.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/10.flash_ctrl_prog_reset.194847502
Short name	T592
Test name
Test status
Simulation time	83676800 ps
CPU time	13.67 seconds
Started	Jul 12 07:15:51 PM PDT 24
Finished	Jul 12 07:16:47 PM PDT 24
Peak memory	259076 kb
Host	smart-e7fb902b-398b-408b-a25e-f494ddaf7bd5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194847502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.flash_ctrl_prog_reset.194847502
Directory	/workspace/10.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rand_ops.2247065663
Short name	T131
Test name
Test status
Simulation time	213600500 ps
CPU time	870.42 seconds
Started	Jul 12 07:15:42 PM PDT 24
Finished	Jul 12 07:30:56 PM PDT 24
Peak memory	284828 kb
Host	smart-c3d271c4-61d9-4b26-92e8-362aed3c6a1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2247065663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2247065663
Directory	/workspace/10.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/10.flash_ctrl_re_evict.2860172363
Short name	T385
Test name
Test status
Simulation time	130600800 ps
CPU time	32.08 seconds
Started	Jul 12 07:15:50 PM PDT 24
Finished	Jul 12 07:17:04 PM PDT 24
Peak memory	275628 kb
Host	smart-f9e54f83-19ea-4111-8856-9a7ac9749fde
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860172363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_re_evict.2860172363
Directory	/workspace/10.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_ro.2867137326
Short name	T930
Test name
Test status
Simulation time	3007889500 ps
CPU time	106.79 seconds
Started	Jul 12 07:15:54 PM PDT 24
Finished	Jul 12 07:18:24 PM PDT 24
Peak memory	281756 kb
Host	smart-3ec6dc7c-016c-4792-8594-106635e4ed2f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867137326 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 10.flash_ctrl_ro.2867137326
Directory	/workspace/10.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw.4048103412
Short name	T538
Test name
Test status
Simulation time	15570181500 ps
CPU time	674.71 seconds
Started	Jul 12 07:15:52 PM PDT 24
Finished	Jul 12 07:27:48 PM PDT 24
Peak memory	309500 kb
Host	smart-807a966a-dca4-415c-b150-f1356dadfa68
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048103412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.flash_ctrl_rw.4048103412
Directory	/workspace/10.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.2935214719
Short name	T549
Test name
Test status
Simulation time	34988900 ps
CPU time	30.86 seconds
Started	Jul 12 07:15:52 PM PDT 24
Finished	Jul 12 07:17:05 PM PDT 24
Peak memory	275664 kb
Host	smart-084c6580-6d88-4eec-8592-fd1f1c9886c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935214719 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.2935214719
Directory	/workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/10.flash_ctrl_sec_info_access.2183478503
Short name	T671
Test name
Test status
Simulation time	1339287300 ps
CPU time	73.8 seconds
Started	Jul 12 07:15:54 PM PDT 24
Finished	Jul 12 07:17:51 PM PDT 24
Peak memory	264648 kb
Host	smart-e64b1136-2068-4f7a-9855-0e2c5c8f3d0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183478503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2183478503
Directory	/workspace/10.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/10.flash_ctrl_smoke.2343457066
Short name	T453
Test name
Test status
Simulation time	43367200 ps
CPU time	75.53 seconds
Started	Jul 12 07:15:40 PM PDT 24
Finished	Jul 12 07:17:42 PM PDT 24
Peak memory	275668 kb
Host	smart-4fe6952c-9aad-43dc-b9f9-f0a1909ed78b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2343457066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.2343457066
Directory	/workspace/10.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.flash_ctrl_wo.2426415713
Short name	T927
Test name
Test status
Simulation time	15477846300 ps
CPU time	172.61 seconds
Started	Jul 12 07:15:51 PM PDT 24
Finished	Jul 12 07:19:26 PM PDT 24
Peak memory	265212 kb
Host	smart-d33dbe9f-af04-4893-bcc6-c06f5e8bf926
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426415713 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.flash_ctrl_wo.2426415713
Directory	/workspace/10.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/11.flash_ctrl_alert_test.1424285402
Short name	T1084
Test name
Test status
Simulation time	44818800 ps
CPU time	13.7 seconds
Started	Jul 12 07:16:28 PM PDT 24
Finished	Jul 12 07:17:18 PM PDT 24
Peak memory	265192 kb
Host	smart-89e680a7-82e8-4573-bd21-d41f983eaae9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424285402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test. 1424285402
Directory	/workspace/11.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.flash_ctrl_connect.3806546420
Short name	T737
Test name
Test status
Simulation time	13900600 ps
CPU time	13.55 seconds
Started	Jul 12 07:16:19 PM PDT 24
Finished	Jul 12 07:17:10 PM PDT 24
Peak memory	274944 kb
Host	smart-5528bca1-b555-4032-b818-7f5982a4104a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806546420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.3806546420
Directory	/workspace/11.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/11.flash_ctrl_disable.1783550438
Short name	T70
Test name
Test status
Simulation time	28877600 ps
CPU time	22.12 seconds
Started	Jul 12 07:16:20 PM PDT 24
Finished	Jul 12 07:17:21 PM PDT 24
Peak memory	273620 kb
Host	smart-9229b714-b9c6-48ff-aeaf-08eb09f03192
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783550438 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_disable.1783550438
Directory	/workspace/11.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3915531797
Short name	T537
Test name
Test status
Simulation time	10018889900 ps
CPU time	70.69 seconds
Started	Jul 12 07:16:32 PM PDT 24
Finished	Jul 12 07:18:20 PM PDT 24
Peak memory	280956 kb
Host	smart-82f07501-9fe4-4ec1-8d34-3e99284a7b9e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915531797 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.3915531797
Directory	/workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.77224226
Short name	T1005
Test name
Test status
Simulation time	33008100 ps
CPU time	13.38 seconds
Started	Jul 12 07:16:19 PM PDT 24
Finished	Jul 12 07:17:10 PM PDT 24
Peak memory	258508 kb
Host	smart-2a0a900e-7230-4c8d-81e1-b6059498d99f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77224226 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.77224226
Directory	/workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_rma_reset.1664639181
Short name	T748
Test name
Test status
Simulation time	380265519500 ps
CPU time	912.78 seconds
Started	Jul 12 07:16:01 PM PDT 24
Finished	Jul 12 07:31:52 PM PDT 24
Peak memory	264512 kb
Host	smart-3f58c9fc-d590-4b29-b5bd-f10b21968a22
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664639181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.flash_ctrl_hw_rma_reset.1664639181
Directory	/workspace/11.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_sec_otp.3651626582
Short name	T902
Test name
Test status
Simulation time	20211310600 ps
CPU time	250.95 seconds
Started	Jul 12 07:15:58 PM PDT 24
Finished	Jul 12 07:20:48 PM PDT 24
Peak memory	263100 kb
Host	smart-e3a6cbbb-d1ff-4756-a9fa-073d41901be5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651626582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ hw_sec_otp.3651626582
Directory	/workspace/11.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd.848691062
Short name	T321
Test name
Test status
Simulation time	2541873500 ps
CPU time	135.33 seconds
Started	Jul 12 07:16:19 PM PDT 24
Finished	Jul 12 07:19:11 PM PDT 24
Peak memory	290988 kb
Host	smart-d86c897e-e9d8-4266-a345-69f2eff0d5df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848691062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas h_ctrl_intr_rd.848691062
Directory	/workspace/11.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.4046483210
Short name	T656
Test name
Test status
Simulation time	24649068500 ps
CPU time	310.73 seconds
Started	Jul 12 07:16:18 PM PDT 24
Finished	Jul 12 07:22:07 PM PDT 24
Peak memory	289992 kb
Host	smart-b4bc7be2-935a-4688-9f14-3ebbb1233431
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046483210 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.4046483210
Directory	/workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/11.flash_ctrl_invalid_op.4145128824
Short name	T823
Test name
Test status
Simulation time	14801099600 ps
CPU time	76.64 seconds
Started	Jul 12 07:16:09 PM PDT 24
Finished	Jul 12 07:18:04 PM PDT 24
Peak memory	262676 kb
Host	smart-99af0421-0385-4d3d-bf8d-5e741d089abc
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145128824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.4 145128824
Directory	/workspace/11.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/11.flash_ctrl_mp_regions.3175281158
Short name	T829
Test name
Test status
Simulation time	136740834000 ps
CPU time	417.53 seconds
Started	Jul 12 07:16:09 PM PDT 24
Finished	Jul 12 07:23:46 PM PDT 24
Peak memory	274508 kb
Host	smart-d8ad38f8-36eb-45ff-875b-12e4f79ea441
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175281158 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.3175281158
Directory	/workspace/11.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/11.flash_ctrl_otp_reset.905692238
Short name	T641
Test name
Test status
Simulation time	39805100 ps
CPU time	110.6 seconds
Started	Jul 12 07:16:11 PM PDT 24
Finished	Jul 12 07:18:40 PM PDT 24
Peak memory	259876 kb
Host	smart-e6b8d047-894e-41ae-809b-0622a6156f49
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905692238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ot p_reset.905692238
Directory	/workspace/11.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_phy_arb.4177061838
Short name	T500
Test name
Test status
Simulation time	328244800 ps
CPU time	274.29 seconds
Started	Jul 12 07:15:59 PM PDT 24
Finished	Jul 12 07:21:12 PM PDT 24
Peak memory	263168 kb
Host	smart-a2b30234-b9d8-4c2a-86b0-6811966ebf65
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4177061838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.4177061838
Directory	/workspace/11.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/11.flash_ctrl_prog_reset.3151158334
Short name	T586
Test name
Test status
Simulation time	143022600 ps
CPU time	13.89 seconds
Started	Jul 12 07:16:15 PM PDT 24
Finished	Jul 12 07:17:07 PM PDT 24
Peak memory	259484 kb
Host	smart-5168ff35-41f9-420a-838f-7b4e050a4390
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151158334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.flash_ctrl_prog_reset.3151158334
Directory	/workspace/11.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rand_ops.2224102011
Short name	T1048
Test name
Test status
Simulation time	1484060400 ps
CPU time	668.44 seconds
Started	Jul 12 07:16:01 PM PDT 24
Finished	Jul 12 07:27:48 PM PDT 24
Peak memory	284612 kb
Host	smart-ccd7e6f5-93a0-4b12-8cb3-552fe452ceeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224102011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.2224102011
Directory	/workspace/11.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/11.flash_ctrl_re_evict.153910690
Short name	T685
Test name
Test status
Simulation time	78577000 ps
CPU time	35.37 seconds
Started	Jul 12 07:16:22 PM PDT 24
Finished	Jul 12 07:17:35 PM PDT 24
Peak memory	275736 kb
Host	smart-4f5c9f7e-fe8d-493b-8419-48d81b79b505
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153910690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla sh_ctrl_re_evict.153910690
Directory	/workspace/11.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_ro.3372844630
Short name	T197
Test name
Test status
Simulation time	1136358400 ps
CPU time	120.79 seconds
Started	Jul 12 07:16:10 PM PDT 24
Finished	Jul 12 07:18:49 PM PDT 24
Peak memory	281820 kb
Host	smart-da4efe91-6df6-41d1-a938-bbf34b93e5f5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372844630 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 11.flash_ctrl_ro.3372844630
Directory	/workspace/11.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw.2295426161
Short name	T688
Test name
Test status
Simulation time	22991457300 ps
CPU time	512.88 seconds
Started	Jul 12 07:16:18 PM PDT 24
Finished	Jul 12 07:25:29 PM PDT 24
Peak memory	317668 kb
Host	smart-e4dfe0fa-30d4-4c78-9ee7-5f7e9be8523f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295426161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.flash_ctrl_rw.2295426161
Directory	/workspace/11.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict.1153262395
Short name	T989
Test name
Test status
Simulation time	79329800 ps
CPU time	27.82 seconds
Started	Jul 12 07:16:22 PM PDT 24
Finished	Jul 12 07:17:27 PM PDT 24
Peak memory	268536 kb
Host	smart-474e3dc4-6af5-43aa-8953-95e32d937104
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153262395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_rw_evict.1153262395
Directory	/workspace/11.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.2443709923
Short name	T20
Test name
Test status
Simulation time	71410100 ps
CPU time	27.86 seconds
Started	Jul 12 07:16:22 PM PDT 24
Finished	Jul 12 07:17:28 PM PDT 24
Peak memory	275700 kb
Host	smart-f92945e3-ce8f-4e48-80b3-791443dced4f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443709923 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.2443709923
Directory	/workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/11.flash_ctrl_sec_info_access.2241280207
Short name	T806
Test name
Test status
Simulation time	8366728400 ps
CPU time	91.37 seconds
Started	Jul 12 07:16:18 PM PDT 24
Finished	Jul 12 07:18:27 PM PDT 24
Peak memory	263680 kb
Host	smart-1bc648c5-7838-4534-aa76-85d9488841ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241280207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2241280207
Directory	/workspace/11.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/11.flash_ctrl_smoke.629959894
Short name	T234
Test name
Test status
Simulation time	3562096400 ps
CPU time	130.03 seconds
Started	Jul 12 07:15:52 PM PDT 24
Finished	Jul 12 07:18:44 PM PDT 24
Peak memory	280668 kb
Host	smart-144d4a67-2513-4252-a429-b19a12009efe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629959894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.629959894
Directory	/workspace/11.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.flash_ctrl_wo.4005314128
Short name	T931
Test name
Test status
Simulation time	9014870000 ps
CPU time	197.46 seconds
Started	Jul 12 07:16:19 PM PDT 24
Finished	Jul 12 07:20:16 PM PDT 24
Peak memory	265248 kb
Host	smart-06055159-5894-447b-9e47-2d444a0b79d3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005314128 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.flash_ctrl_wo.4005314128
Directory	/workspace/11.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/12.flash_ctrl_alert_test.4252296318
Short name	T984
Test name
Test status
Simulation time	100165700 ps
CPU time	13.89 seconds
Started	Jul 12 07:16:52 PM PDT 24
Finished	Jul 12 07:17:44 PM PDT 24
Peak memory	258268 kb
Host	smart-2d88d9fd-f9b4-4ede-a9ca-1db72402792b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252296318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test. 4252296318
Directory	/workspace/12.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.flash_ctrl_connect.4187488249
Short name	T455
Test name
Test status
Simulation time	39901500 ps
CPU time	16.55 seconds
Started	Jul 12 07:16:53 PM PDT 24
Finished	Jul 12 07:17:47 PM PDT 24
Peak memory	284256 kb
Host	smart-76a92a97-ce9a-4a73-9d9b-ca186c582ce5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187488249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.4187488249
Directory	/workspace/12.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/12.flash_ctrl_disable.1951074955
Short name	T822
Test name
Test status
Simulation time	26877400 ps
CPU time	21.5 seconds
Started	Jul 12 07:16:53 PM PDT 24
Finished	Jul 12 07:17:52 PM PDT 24
Peak memory	265528 kb
Host	smart-80cd4617-2243-41b1-9499-61cb8e7a5b2c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951074955 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_disable.1951074955
Directory	/workspace/12.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.4081118333
Short name	T576
Test name
Test status
Simulation time	10011797400 ps
CPU time	135.35 seconds
Started	Jul 12 07:16:59 PM PDT 24
Finished	Jul 12 07:19:52 PM PDT 24
Peak memory	362328 kb
Host	smart-2aeeed71-139a-478c-88f8-c6677efa38ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081118333 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.4081118333
Directory	/workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1403046165
Short name	T320
Test name
Test status
Simulation time	56572300 ps
CPU time	13.53 seconds
Started	Jul 12 07:16:53 PM PDT 24
Finished	Jul 12 07:17:44 PM PDT 24
Peak memory	260428 kb
Host	smart-d8e2766d-7c61-40bc-b3e2-004272c213d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403046165 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1403046165
Directory	/workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.3275409758
Short name	T647
Test name
Test status
Simulation time	290244049100 ps
CPU time	929.75 seconds
Started	Jul 12 07:16:29 PM PDT 24
Finished	Jul 12 07:32:35 PM PDT 24
Peak memory	262388 kb
Host	smart-d7a1990e-de67-4bb8-b721-e99880b46954
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275409758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.flash_ctrl_hw_rma_reset.3275409758
Directory	/workspace/12.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_sec_otp.2579126172
Short name	T478
Test name
Test status
Simulation time	3426864600 ps
CPU time	105.62 seconds
Started	Jul 12 07:16:29 PM PDT 24
Finished	Jul 12 07:18:54 PM PDT 24
Peak memory	263380 kb
Host	smart-b136f712-72c5-4baa-a7a6-f11a4f178dbc
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579126172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ hw_sec_otp.2579126172
Directory	/workspace/12.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd.2713548588
Short name	T617
Test name
Test status
Simulation time	1021133000 ps
CPU time	116.61 seconds
Started	Jul 12 07:16:45 PM PDT 24
Finished	Jul 12 07:19:20 PM PDT 24
Peak memory	293872 kb
Host	smart-4b685cd4-2bfa-4157-b446-b96fac1bf539
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713548588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_intr_rd.2713548588
Directory	/workspace/12.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3720858666
Short name	T722
Test name
Test status
Simulation time	44513403100 ps
CPU time	369.19 seconds
Started	Jul 12 07:16:53 PM PDT 24
Finished	Jul 12 07:23:40 PM PDT 24
Peak memory	284868 kb
Host	smart-362af504-4e55-4ab0-ad65-b9bc96ac8796
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720858666 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.3720858666
Directory	/workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/12.flash_ctrl_invalid_op.3820710052
Short name	T1009
Test name
Test status
Simulation time	2091758900 ps
CPU time	71.9 seconds
Started	Jul 12 07:16:45 PM PDT 24
Finished	Jul 12 07:18:36 PM PDT 24
Peak memory	262772 kb
Host	smart-155a4f3a-762a-41cc-8d85-bf7e48042a26
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820710052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.3 820710052
Directory	/workspace/12.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1095261958
Short name	T1053
Test name
Test status
Simulation time	25869200 ps
CPU time	13.38 seconds
Started	Jul 12 07:16:52 PM PDT 24
Finished	Jul 12 07:17:44 PM PDT 24
Peak memory	260020 kb
Host	smart-1e8d8968-aabc-4b9c-b1fd-d3ef152651a2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095261958 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.1095261958
Directory	/workspace/12.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/12.flash_ctrl_mp_regions.3921317631
Short name	T347
Test name
Test status
Simulation time	42210821300 ps
CPU time	145.14 seconds
Started	Jul 12 07:16:30 PM PDT 24
Finished	Jul 12 07:19:34 PM PDT 24
Peak memory	265176 kb
Host	smart-551439e5-e857-4c63-8411-69f0a8f48485
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921317631 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.3921317631
Directory	/workspace/12.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/12.flash_ctrl_otp_reset.1632226401
Short name	T302
Test name
Test status
Simulation time	94491800 ps
CPU time	109.19 seconds
Started	Jul 12 07:16:29 PM PDT 24
Finished	Jul 12 07:18:54 PM PDT 24
Peak memory	260132 kb
Host	smart-7e39fe15-a8d4-4c24-834d-47d510f1e321
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632226401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o tp_reset.1632226401
Directory	/workspace/12.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_phy_arb.3679791323
Short name	T735
Test name
Test status
Simulation time	1383767500 ps
CPU time	434.84 seconds
Started	Jul 12 07:16:29 PM PDT 24
Finished	Jul 12 07:24:20 PM PDT 24
Peak memory	263268 kb
Host	smart-6762ec9b-e602-4f3e-aeb2-38883ba8bfd5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3679791323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.3679791323
Directory	/workspace/12.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/12.flash_ctrl_prog_reset.2669674856
Short name	T470
Test name
Test status
Simulation time	57625900 ps
CPU time	13.87 seconds
Started	Jul 12 07:16:57 PM PDT 24
Finished	Jul 12 07:17:50 PM PDT 24
Peak memory	265148 kb
Host	smart-efac5df5-2c5f-48a4-81b5-56c4120b8670
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669674856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.flash_ctrl_prog_reset.2669674856
Directory	/workspace/12.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rand_ops.3247516311
Short name	T802
Test name
Test status
Simulation time	83320100 ps
CPU time	248.29 seconds
Started	Jul 12 07:16:28 PM PDT 24
Finished	Jul 12 07:21:13 PM PDT 24
Peak memory	280968 kb
Host	smart-2b651ea1-d790-430e-bd5b-3d599fa3000e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3247516311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.3247516311
Directory	/workspace/12.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/12.flash_ctrl_ro.102434121
Short name	T709
Test name
Test status
Simulation time	2048561400 ps
CPU time	139.01 seconds
Started	Jul 12 07:16:44 PM PDT 24
Finished	Jul 12 07:19:42 PM PDT 24
Peak memory	281736 kb
Host	smart-7f5e4c9e-e8d7-4164-b618-47c47ac5df71
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102434121 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.flash_ctrl_ro.102434121
Directory	/workspace/12.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw.387399645
Short name	T514
Test name
Test status
Simulation time	3954988400 ps
CPU time	587.03 seconds
Started	Jul 12 07:16:43 PM PDT 24
Finished	Jul 12 07:27:10 PM PDT 24
Peak memory	309756 kb
Host	smart-e17a7a31-f889-4abf-bf86-b1081678f1d8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387399645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.387399645
Directory	/workspace/12.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict.3500525146
Short name	T934
Test name
Test status
Simulation time	45611600 ps
CPU time	31.64 seconds
Started	Jul 12 07:16:54 PM PDT 24
Finished	Jul 12 07:18:04 PM PDT 24
Peak memory	275668 kb
Host	smart-13f52522-2b92-4202-8c1a-8fb273f4271c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500525146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_rw_evict.3500525146
Directory	/workspace/12.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_smoke.1861677068
Short name	T543
Test name
Test status
Simulation time	59677500 ps
CPU time	143.93 seconds
Started	Jul 12 07:16:30 PM PDT 24
Finished	Jul 12 07:19:31 PM PDT 24
Peak memory	277164 kb
Host	smart-04d88bfb-9447-42f3-8ff1-c3130526f13e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1861677068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1861677068
Directory	/workspace/12.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.flash_ctrl_wo.3537434675
Short name	T129
Test name
Test status
Simulation time	3283799800 ps
CPU time	178.91 seconds
Started	Jul 12 07:16:44 PM PDT 24
Finished	Jul 12 07:20:22 PM PDT 24
Peak memory	260548 kb
Host	smart-b90c4d04-adbc-411c-8430-316f5a60300e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537434675 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.flash_ctrl_wo.3537434675
Directory	/workspace/12.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/13.flash_ctrl_alert_test.3072788584
Short name	T501
Test name
Test status
Simulation time	410465200 ps
CPU time	13.9 seconds
Started	Jul 12 07:17:19 PM PDT 24
Finished	Jul 12 07:18:11 PM PDT 24
Peak memory	265216 kb
Host	smart-914b6424-95b4-4478-8ede-c14cf1134e91
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072788584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test. 3072788584
Directory	/workspace/13.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.flash_ctrl_connect.1037075905
Short name	T411
Test name
Test status
Simulation time	31027300 ps
CPU time	16.22 seconds
Started	Jul 12 07:17:22 PM PDT 24
Finished	Jul 12 07:18:14 PM PDT 24
Peak memory	284460 kb
Host	smart-30833396-bbaf-40ef-89b1-79767e0633ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037075905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1037075905
Directory	/workspace/13.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1908127674
Short name	T156
Test name
Test status
Simulation time	10018074400 ps
CPU time	79.16 seconds
Started	Jul 12 07:17:20 PM PDT 24
Finished	Jul 12 07:19:16 PM PDT 24
Peak memory	290868 kb
Host	smart-1eb3cff7-ce65-4de4-8794-efec4223072b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908127674 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.1908127674
Directory	/workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.1083074195
Short name	T770
Test name
Test status
Simulation time	52227600 ps
CPU time	13.46 seconds
Started	Jul 12 07:17:20 PM PDT 24
Finished	Jul 12 07:18:11 PM PDT 24
Peak memory	264968 kb
Host	smart-8b26c041-0cbb-4896-95a4-ecd3da8bc0eb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083074195 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.1083074195
Directory	/workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_rma_reset.3099847237
Short name	T169
Test name
Test status
Simulation time	140170670200 ps
CPU time	891.26 seconds
Started	Jul 12 07:17:01 PM PDT 24
Finished	Jul 12 07:32:31 PM PDT 24
Peak memory	261060 kb
Host	smart-55f72083-dec6-45bc-86f7-ee19709eff58
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099847237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.flash_ctrl_hw_rma_reset.3099847237
Directory	/workspace/13.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.4278735006
Short name	T517
Test name
Test status
Simulation time	2761407600 ps
CPU time	91.6 seconds
Started	Jul 12 07:17:00 PM PDT 24
Finished	Jul 12 07:19:11 PM PDT 24
Peak memory	263200 kb
Host	smart-300d8c03-9052-4264-af7c-8429ccc79830
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278735006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ hw_sec_otp.4278735006
Directory	/workspace/13.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd.2973704395
Short name	T312
Test name
Test status
Simulation time	1428818700 ps
CPU time	248.95 seconds
Started	Jul 12 07:17:12 PM PDT 24
Finished	Jul 12 07:22:00 PM PDT 24
Peak memory	291400 kb
Host	smart-f90b13cd-af56-40ac-aa19-fda607488bce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973704395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_intr_rd.2973704395
Directory	/workspace/13.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/13.flash_ctrl_invalid_op.2953502432
Short name	T137
Test name
Test status
Simulation time	4423301600 ps
CPU time	85.38 seconds
Started	Jul 12 07:17:05 PM PDT 24
Finished	Jul 12 07:19:09 PM PDT 24
Peak memory	260584 kb
Host	smart-80d4f41f-5e4c-46e6-8710-3b5c43e6c740
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953502432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.2 953502432
Directory	/workspace/13.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2837715820
Short name	T272
Test name
Test status
Simulation time	30763300 ps
CPU time	13.85 seconds
Started	Jul 12 07:17:20 PM PDT 24
Finished	Jul 12 07:18:11 PM PDT 24
Peak memory	260872 kb
Host	smart-37e1637d-fecc-4b9d-b421-4f9cbc45f37f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837715820 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2837715820
Directory	/workspace/13.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/13.flash_ctrl_mp_regions.970607973
Short name	T124
Test name
Test status
Simulation time	30818875800 ps
CPU time	493.8 seconds
Started	Jul 12 07:17:02 PM PDT 24
Finished	Jul 12 07:25:53 PM PDT 24
Peak memory	274872 kb
Host	smart-23be94c5-a859-4343-b709-9edb117ed487
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970607973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.970607973
Directory	/workspace/13.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/13.flash_ctrl_otp_reset.2404163842
Short name	T469
Test name
Test status
Simulation time	38529000 ps
CPU time	134.03 seconds
Started	Jul 12 07:17:04 PM PDT 24
Finished	Jul 12 07:19:57 PM PDT 24
Peak memory	260128 kb
Host	smart-7273f504-4b33-451d-930b-59dc76d19ce2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404163842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o tp_reset.2404163842
Directory	/workspace/13.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_phy_arb.2058206881
Short name	T622
Test name
Test status
Simulation time	36367200 ps
CPU time	110.64 seconds
Started	Jul 12 07:17:05 PM PDT 24
Finished	Jul 12 07:19:33 PM PDT 24
Peak memory	263192 kb
Host	smart-da352e93-58ae-4943-a1d1-2e31ebe634aa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2058206881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.2058206881
Directory	/workspace/13.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/13.flash_ctrl_prog_reset.3089125862
Short name	T1066
Test name
Test status
Simulation time	47934400 ps
CPU time	14.05 seconds
Started	Jul 12 07:17:13 PM PDT 24
Finished	Jul 12 07:18:07 PM PDT 24
Peak memory	259412 kb
Host	smart-51ea1af2-14d6-4cf0-b56c-65cb48edd00e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089125862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.flash_ctrl_prog_reset.3089125862
Directory	/workspace/13.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rand_ops.2314644698
Short name	T559
Test name
Test status
Simulation time	188153500 ps
CPU time	586.32 seconds
Started	Jul 12 07:16:52 PM PDT 24
Finished	Jul 12 07:27:17 PM PDT 24
Peak memory	283948 kb
Host	smart-5a1f8b5e-0b12-4050-bae8-3bb7e5a1643d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314644698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.2314644698
Directory	/workspace/13.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/13.flash_ctrl_re_evict.3044907913
Short name	T383
Test name
Test status
Simulation time	195366300 ps
CPU time	33.98 seconds
Started	Jul 12 07:17:11 PM PDT 24
Finished	Jul 12 07:18:25 PM PDT 24
Peak memory	275652 kb
Host	smart-181a6197-00dd-43a4-a4ac-d9b519cdc8f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044907913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_re_evict.3044907913
Directory	/workspace/13.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_ro.3345557538
Short name	T1038
Test name
Test status
Simulation time	2352923300 ps
CPU time	99.6 seconds
Started	Jul 12 07:17:02 PM PDT 24
Finished	Jul 12 07:19:21 PM PDT 24
Peak memory	281676 kb
Host	smart-5988e105-0767-42ad-8792-b22f1c20166e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345557538 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 13.flash_ctrl_ro.3345557538
Directory	/workspace/13.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw.3961271602
Short name	T209
Test name
Test status
Simulation time	3891546300 ps
CPU time	583.87 seconds
Started	Jul 12 07:17:13 PM PDT 24
Finished	Jul 12 07:27:37 PM PDT 24
Peak memory	309952 kb
Host	smart-37cf105f-8a55-44a9-8f89-56be7de1480b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961271602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.flash_ctrl_rw.3961271602
Directory	/workspace/13.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict.1380031034
Short name	T467
Test name
Test status
Simulation time	144482300 ps
CPU time	30.95 seconds
Started	Jul 12 07:17:13 PM PDT 24
Finished	Jul 12 07:18:25 PM PDT 24
Peak memory	275716 kb
Host	smart-dadbff72-6929-4753-9be5-f1b8bb6fb31e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380031034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_rw_evict.1380031034
Directory	/workspace/13.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.1098260123
Short name	T261
Test name
Test status
Simulation time	39466200 ps
CPU time	28.56 seconds
Started	Jul 12 07:17:12 PM PDT 24
Finished	Jul 12 07:18:20 PM PDT 24
Peak memory	275648 kb
Host	smart-6534f86b-9566-4074-860a-13159561af15
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098260123 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.1098260123
Directory	/workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/13.flash_ctrl_sec_info_access.210089743
Short name	T1043
Test name
Test status
Simulation time	557323500 ps
CPU time	65.66 seconds
Started	Jul 12 07:17:10 PM PDT 24
Finished	Jul 12 07:18:54 PM PDT 24
Peak memory	264628 kb
Host	smart-44051e14-9fe5-4857-bca6-25e521209d15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=210089743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.210089743
Directory	/workspace/13.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/13.flash_ctrl_smoke.3158037737
Short name	T548
Test name
Test status
Simulation time	79479500 ps
CPU time	73.17 seconds
Started	Jul 12 07:16:54 PM PDT 24
Finished	Jul 12 07:18:46 PM PDT 24
Peak memory	276720 kb
Host	smart-890ce600-cc1e-48e5-850a-0ce032140d66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158037737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.3158037737
Directory	/workspace/13.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.flash_ctrl_wo.965519436
Short name	T560
Test name
Test status
Simulation time	8361507500 ps
CPU time	159.56 seconds
Started	Jul 12 07:17:02 PM PDT 24
Finished	Jul 12 07:20:19 PM PDT 24
Peak memory	265300 kb
Host	smart-df737d25-6482-4498-b4fe-f791438f84d7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965519436 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 13.flash_ctrl_wo.965519436
Directory	/workspace/13.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/14.flash_ctrl_alert_test.3005190746
Short name	T569
Test name
Test status
Simulation time	41376900 ps
CPU time	13.82 seconds
Started	Jul 12 07:17:28 PM PDT 24
Finished	Jul 12 07:18:20 PM PDT 24
Peak memory	258264 kb
Host	smart-607ace15-62d1-4591-9604-c89ab518bfbe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005190746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test. 3005190746
Directory	/workspace/14.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.flash_ctrl_connect.860550024
Short name	T795
Test name
Test status
Simulation time	24077700 ps
CPU time	15.99 seconds
Started	Jul 12 07:17:30 PM PDT 24
Finished	Jul 12 07:18:21 PM PDT 24
Peak memory	274916 kb
Host	smart-f82e3bb9-e06e-4130-923b-33d54c77365c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860550024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.860550024
Directory	/workspace/14.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/14.flash_ctrl_disable.2981046439
Short name	T183
Test name
Test status
Simulation time	23260200 ps
CPU time	21.72 seconds
Started	Jul 12 07:17:28 PM PDT 24
Finished	Jul 12 07:18:27 PM PDT 24
Peak memory	273568 kb
Host	smart-3210ab2d-42c8-462d-a31b-7c6f97260c6e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981046439 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_disable.2981046439
Directory	/workspace/14.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.3817608626
Short name	T721
Test name
Test status
Simulation time	66349300 ps
CPU time	13.63 seconds
Started	Jul 12 07:17:28 PM PDT 24
Finished	Jul 12 07:18:19 PM PDT 24
Peak memory	265324 kb
Host	smart-9ba7a5c3-f940-4b36-b6ee-46c479ddba8a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817608626 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.3817608626
Directory	/workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_rma_reset.1578932005
Short name	T170
Test name
Test status
Simulation time	80151674800 ps
CPU time	848.16 seconds
Started	Jul 12 07:17:28 PM PDT 24
Finished	Jul 12 07:32:14 PM PDT 24
Peak memory	264412 kb
Host	smart-8888b89f-4930-4b15-93c4-473685da3815
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578932005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.flash_ctrl_hw_rma_reset.1578932005
Directory	/workspace/14.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.1517740985
Short name	T226
Test name
Test status
Simulation time	6330038200 ps
CPU time	100.64 seconds
Started	Jul 12 07:17:22 PM PDT 24
Finished	Jul 12 07:19:41 PM PDT 24
Peak memory	260888 kb
Host	smart-645e2ab1-0f01-4198-afa1-e8540433bf86
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517740985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ hw_sec_otp.1517740985
Directory	/workspace/14.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd.1624897437
Short name	T746
Test name
Test status
Simulation time	4465186200 ps
CPU time	141.81 seconds
Started	Jul 12 07:17:29 PM PDT 24
Finished	Jul 12 07:20:27 PM PDT 24
Peak memory	291556 kb
Host	smart-924931b6-5fa4-4f66-94d7-2f06b31d5eb7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624897437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla sh_ctrl_intr_rd.1624897437
Directory	/workspace/14.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1084259173
Short name	T1056
Test name
Test status
Simulation time	6059516400 ps
CPU time	141.92 seconds
Started	Jul 12 07:17:29 PM PDT 24
Finished	Jul 12 07:20:27 PM PDT 24
Peak memory	293124 kb
Host	smart-9068843d-03d8-4c29-b0f6-ad0cc7ed9797
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084259173 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1084259173
Directory	/workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/14.flash_ctrl_invalid_op.2840109141
Short name	T731
Test name
Test status
Simulation time	1659133100 ps
CPU time	64.72 seconds
Started	Jul 12 07:17:27 PM PDT 24
Finished	Jul 12 07:19:07 PM PDT 24
Peak memory	263436 kb
Host	smart-bc8e0035-7470-41f3-9acf-bc0cb0eb1daf
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840109141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.2 840109141
Directory	/workspace/14.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2072336156
Short name	T903
Test name
Test status
Simulation time	48926000 ps
CPU time	13.39 seconds
Started	Jul 12 07:17:30 PM PDT 24
Finished	Jul 12 07:18:22 PM PDT 24
Peak memory	264960 kb
Host	smart-425a1d4f-9c1a-499d-843c-fdd6ec587587
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072336156 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2072336156
Directory	/workspace/14.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/14.flash_ctrl_mp_regions.2472927615
Short name	T120
Test name
Test status
Simulation time	50161897200 ps
CPU time	956.39 seconds
Started	Jul 12 07:17:26 PM PDT 24
Finished	Jul 12 07:33:59 PM PDT 24
Peak memory	274324 kb
Host	smart-0ceeb118-f7fc-48e2-97f8-68234a4c89e1
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472927615 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.2472927615
Directory	/workspace/14.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/14.flash_ctrl_otp_reset.3944603452
Short name	T525
Test name
Test status
Simulation time	42134700 ps
CPU time	131.56 seconds
Started	Jul 12 07:17:27 PM PDT 24
Finished	Jul 12 07:20:14 PM PDT 24
Peak memory	260296 kb
Host	smart-0c1efc61-b51e-429c-812c-5e696366875e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944603452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o tp_reset.3944603452
Directory	/workspace/14.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_phy_arb.1938249264
Short name	T695
Test name
Test status
Simulation time	61760000 ps
CPU time	282.41 seconds
Started	Jul 12 07:17:21 PM PDT 24
Finished	Jul 12 07:22:40 PM PDT 24
Peak memory	263060 kb
Host	smart-1922644b-2175-4d3f-9de7-7b492d7ed13e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1938249264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.1938249264
Directory	/workspace/14.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/14.flash_ctrl_prog_reset.4252139148
Short name	T439
Test name
Test status
Simulation time	19939100 ps
CPU time	13.53 seconds
Started	Jul 12 07:17:30 PM PDT 24
Finished	Jul 12 07:18:19 PM PDT 24
Peak memory	265248 kb
Host	smart-1fd29d6b-8b81-4722-8ba3-37ddc52df994
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252139148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.flash_ctrl_prog_reset.4252139148
Directory	/workspace/14.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rand_ops.3856266128
Short name	T515
Test name
Test status
Simulation time	1416831700 ps
CPU time	696.58 seconds
Started	Jul 12 07:17:19 PM PDT 24
Finished	Jul 12 07:29:34 PM PDT 24
Peak memory	285852 kb
Host	smart-429977af-88bb-4a79-a65e-2fcb51ac2204
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856266128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3856266128
Directory	/workspace/14.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/14.flash_ctrl_re_evict.2327570313
Short name	T780
Test name
Test status
Simulation time	274350700 ps
CPU time	34.49 seconds
Started	Jul 12 07:17:29 PM PDT 24
Finished	Jul 12 07:18:40 PM PDT 24
Peak memory	275616 kb
Host	smart-579b8ad9-ba70-451a-911b-fc29ecce4519
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327570313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_re_evict.2327570313
Directory	/workspace/14.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_ro.4029076373
Short name	T783
Test name
Test status
Simulation time	496716100 ps
CPU time	126.71 seconds
Started	Jul 12 07:17:28 PM PDT 24
Finished	Jul 12 07:20:12 PM PDT 24
Peak memory	281756 kb
Host	smart-9489fbe4-7a3e-46be-a2f0-9d8e666e98a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029076373 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 14.flash_ctrl_ro.4029076373
Directory	/workspace/14.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw.867300763
Short name	T506
Test name
Test status
Simulation time	5999445000 ps
CPU time	512.38 seconds
Started	Jul 12 07:17:27 PM PDT 24
Finished	Jul 12 07:26:35 PM PDT 24
Peak memory	309828 kb
Host	smart-cd163611-9418-4c9d-b73c-9d6e1643917e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867300763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.867300763
Directory	/workspace/14.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict.3050095101
Short name	T474
Test name
Test status
Simulation time	42970600 ps
CPU time	30.91 seconds
Started	Jul 12 07:17:28 PM PDT 24
Finished	Jul 12 07:18:36 PM PDT 24
Peak memory	275612 kb
Host	smart-41ccb0af-156f-45aa-b2ea-32a12dcde529
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050095101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_rw_evict.3050095101
Directory	/workspace/14.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_sec_info_access.1850791444
Short name	T618
Test name
Test status
Simulation time	4574041400 ps
CPU time	61.44 seconds
Started	Jul 12 07:17:27 PM PDT 24
Finished	Jul 12 07:19:04 PM PDT 24
Peak memory	263720 kb
Host	smart-1e56a09f-81c4-4428-9d6b-5e279cce2f27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850791444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1850791444
Directory	/workspace/14.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/14.flash_ctrl_smoke.480930751
Short name	T976
Test name
Test status
Simulation time	35235000 ps
CPU time	124.25 seconds
Started	Jul 12 07:17:19 PM PDT 24
Finished	Jul 12 07:20:00 PM PDT 24
Peak memory	276672 kb
Host	smart-43c1b856-34c2-46c7-992e-157ecbbdc4cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480930751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.480930751
Directory	/workspace/14.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.flash_ctrl_wo.3325596089
Short name	T967
Test name
Test status
Simulation time	7419727200 ps
CPU time	170.82 seconds
Started	Jul 12 07:17:28 PM PDT 24
Finished	Jul 12 07:20:56 PM PDT 24
Peak memory	259988 kb
Host	smart-a0b53f6a-bcc5-4e37-bc02-d5efc58fce89
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325596089 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.flash_ctrl_wo.3325596089
Directory	/workspace/14.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/15.flash_ctrl_alert_test.3035313784
Short name	T938
Test name
Test status
Simulation time	179221400 ps
CPU time	14.38 seconds
Started	Jul 12 07:17:59 PM PDT 24
Finished	Jul 12 07:18:49 PM PDT 24
Peak memory	265184 kb
Host	smart-5baa1b9e-f66c-40e1-90bc-786901e95959
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035313784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test. 3035313784
Directory	/workspace/15.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.flash_ctrl_connect.1048633218
Short name	T673
Test name
Test status
Simulation time	39788900 ps
CPU time	13.57 seconds
Started	Jul 12 07:17:52 PM PDT 24
Finished	Jul 12 07:18:40 PM PDT 24
Peak memory	284192 kb
Host	smart-3341d840-4992-445b-904f-8bb1d4614d4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1048633218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1048633218
Directory	/workspace/15.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3583601868
Short name	T1087
Test name
Test status
Simulation time	10018811600 ps
CPU time	82.46 seconds
Started	Jul 12 07:17:57 PM PDT 24
Finished	Jul 12 07:19:54 PM PDT 24
Peak memory	314920 kb
Host	smart-be2c8049-01c1-4d72-9c66-cec6a0e952a4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583601868 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3583601868
Directory	/workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1139709651
Short name	T536
Test name
Test status
Simulation time	107554800 ps
CPU time	13.35 seconds
Started	Jul 12 07:17:56 PM PDT 24
Finished	Jul 12 07:18:45 PM PDT 24
Peak memory	258524 kb
Host	smart-0607dc74-b6e5-430f-8871-2bd7061b2a7f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139709651 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.1139709651
Directory	/workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_rma_reset.2116744867
Short name	T651
Test name
Test status
Simulation time	80151236900 ps
CPU time	945.37 seconds
Started	Jul 12 07:17:39 PM PDT 24
Finished	Jul 12 07:33:59 PM PDT 24
Peak memory	264188 kb
Host	smart-38cf3323-64fb-4fce-a448-4b29a7270854
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116744867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 15.flash_ctrl_hw_rma_reset.2116744867
Directory	/workspace/15.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_sec_otp.558333060
Short name	T697
Test name
Test status
Simulation time	15981010800 ps
CPU time	139.79 seconds
Started	Jul 12 07:17:36 PM PDT 24
Finished	Jul 12 07:20:32 PM PDT 24
Peak memory	263344 kb
Host	smart-9b54eafb-3836-494b-b5b8-dad5c8ed128d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558333060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_h w_sec_otp.558333060
Directory	/workspace/15.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd.794871913
Short name	T516
Test name
Test status
Simulation time	6428551500 ps
CPU time	228.94 seconds
Started	Jul 12 07:17:52 PM PDT 24
Finished	Jul 12 07:22:14 PM PDT 24
Peak memory	285004 kb
Host	smart-445b5b41-3f25-4e72-a09d-94afe608b32f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794871913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flas h_ctrl_intr_rd.794871913
Directory	/workspace/15.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.820846681
Short name	T680
Test name
Test status
Simulation time	11981735300 ps
CPU time	152.71 seconds
Started	Jul 12 07:17:50 PM PDT 24
Finished	Jul 12 07:20:58 PM PDT 24
Peak memory	293056 kb
Host	smart-b376b88d-2550-4420-b486-187a6691da43
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820846681 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.820846681
Directory	/workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/15.flash_ctrl_invalid_op.1437612550
Short name	T208
Test name
Test status
Simulation time	3238003700 ps
CPU time	71.97 seconds
Started	Jul 12 07:17:38 PM PDT 24
Finished	Jul 12 07:19:26 PM PDT 24
Peak memory	262732 kb
Host	smart-158bc3a2-81f5-41a5-b082-ac115d7a09e5
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437612550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1 437612550
Directory	/workspace/15.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.1814910471
Short name	T148
Test name
Test status
Simulation time	84857200 ps
CPU time	13.64 seconds
Started	Jul 12 07:17:59 PM PDT 24
Finished	Jul 12 07:18:48 PM PDT 24
Peak memory	260908 kb
Host	smart-14dc0634-6922-42fa-8b68-132218f43df9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814910471 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.1814910471
Directory	/workspace/15.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/15.flash_ctrl_otp_reset.3118881194
Short name	T493
Test name
Test status
Simulation time	37008600 ps
CPU time	130.79 seconds
Started	Jul 12 07:17:37 PM PDT 24
Finished	Jul 12 07:20:24 PM PDT 24
Peak memory	261132 kb
Host	smart-451b3904-e4b9-404f-a7a9-bd77a132fad7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118881194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o tp_reset.3118881194
Directory	/workspace/15.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_phy_arb.71541123
Short name	T772
Test name
Test status
Simulation time	709278000 ps
CPU time	340.53 seconds
Started	Jul 12 07:17:37 PM PDT 24
Finished	Jul 12 07:23:54 PM PDT 24
Peak memory	263220 kb
Host	smart-fa6348b5-920e-4d7c-9cb1-2a11d79bfd72
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=71541123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.71541123
Directory	/workspace/15.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/15.flash_ctrl_prog_reset.816886029
Short name	T916
Test name
Test status
Simulation time	74516200 ps
CPU time	14.02 seconds
Started	Jul 12 07:17:52 PM PDT 24
Finished	Jul 12 07:18:40 PM PDT 24
Peak memory	265136 kb
Host	smart-010ceda9-7740-4d7a-8394-461e7b031ae0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816886029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.flash_ctrl_prog_reset.816886029
Directory	/workspace/15.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rand_ops.4150121494
Short name	T145
Test name
Test status
Simulation time	556077500 ps
CPU time	668.95 seconds
Started	Jul 12 07:17:29 PM PDT 24
Finished	Jul 12 07:29:14 PM PDT 24
Peak memory	283496 kb
Host	smart-2c6ccd35-5616-47f5-b3b8-ae411e815e89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4150121494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.4150121494
Directory	/workspace/15.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/15.flash_ctrl_re_evict.1866551963
Short name	T260
Test name
Test status
Simulation time	269098500 ps
CPU time	35.5 seconds
Started	Jul 12 07:17:51 PM PDT 24
Finished	Jul 12 07:19:01 PM PDT 24
Peak memory	270276 kb
Host	smart-7dd72e68-b63a-4ec9-b149-d4f9d9c515f6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866551963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_re_evict.1866551963
Directory	/workspace/15.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_ro.228408641
Short name	T490
Test name
Test status
Simulation time	544195200 ps
CPU time	120.6 seconds
Started	Jul 12 07:17:37 PM PDT 24
Finished	Jul 12 07:20:14 PM PDT 24
Peak memory	289896 kb
Host	smart-61e8ac66-5913-4f47-afe6-21e0585c65df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228408641 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.flash_ctrl_ro.228408641
Directory	/workspace/15.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw.3047096446
Short name	T512
Test name
Test status
Simulation time	6496209900 ps
CPU time	600.32 seconds
Started	Jul 12 07:17:37 PM PDT 24
Finished	Jul 12 07:28:13 PM PDT 24
Peak memory	314572 kb
Host	smart-1bdebadd-5089-4d97-88e7-64e95fdd08ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047096446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.flash_ctrl_rw.3047096446
Directory	/workspace/15.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict.1334598883
Short name	T391
Test name
Test status
Simulation time	33264100 ps
CPU time	31.57 seconds
Started	Jul 12 07:17:51 PM PDT 24
Finished	Jul 12 07:18:57 PM PDT 24
Peak memory	275668 kb
Host	smart-ddacd07e-fbef-47b2-b8eb-1655d0f1d883
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334598883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_rw_evict.1334598883
Directory	/workspace/15.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.4194629279
Short name	T1102
Test name
Test status
Simulation time	27887700 ps
CPU time	31.19 seconds
Started	Jul 12 07:17:51 PM PDT 24
Finished	Jul 12 07:18:57 PM PDT 24
Peak memory	268484 kb
Host	smart-f9fb417c-0fc6-4a3d-8daf-d7954737db70
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194629279 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.4194629279
Directory	/workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/15.flash_ctrl_smoke.1310848031
Short name	T446
Test name
Test status
Simulation time	24850400 ps
CPU time	50.92 seconds
Started	Jul 12 07:17:29 PM PDT 24
Finished	Jul 12 07:18:56 PM PDT 24
Peak memory	271360 kb
Host	smart-8d607696-a685-4807-9439-4b5ef436ba99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310848031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1310848031
Directory	/workspace/15.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.flash_ctrl_wo.2279481637
Short name	T995
Test name
Test status
Simulation time	13614935300 ps
CPU time	184.59 seconds
Started	Jul 12 07:17:37 PM PDT 24
Finished	Jul 12 07:21:18 PM PDT 24
Peak memory	265320 kb
Host	smart-181f0978-6636-4e75-8cdd-9db1083442c8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279481637 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.flash_ctrl_wo.2279481637
Directory	/workspace/15.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/16.flash_ctrl_alert_test.83674685
Short name	T408
Test name
Test status
Simulation time	76387200 ps
CPU time	13.88 seconds
Started	Jul 12 07:18:25 PM PDT 24
Finished	Jul 12 07:19:08 PM PDT 24
Peak memory	258212 kb
Host	smart-68a7a28e-301a-4121-bf29-5350c9786749
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83674685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.83674685
Directory	/workspace/16.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.flash_ctrl_connect.606627894
Short name	T414
Test name
Test status
Simulation time	15135200 ps
CPU time	13.91 seconds
Started	Jul 12 07:18:14 PM PDT 24
Finished	Jul 12 07:19:00 PM PDT 24
Peak memory	284212 kb
Host	smart-1204e80c-bcf6-4ca6-8cdf-b76b2be1a8eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=606627894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.606627894
Directory	/workspace/16.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/16.flash_ctrl_disable.60316165
Short name	T899
Test name
Test status
Simulation time	20107000 ps
CPU time	21.74 seconds
Started	Jul 12 07:18:16 PM PDT 24
Finished	Jul 12 07:19:09 PM PDT 24
Peak memory	273644 kb
Host	smart-a31aaaf9-c899-4f84-82f0-db6b3ee96d85
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60316165 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 16.flash_ctrl_disable.60316165
Directory	/workspace/16.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.229713040
Short name	T972
Test name
Test status
Simulation time	15294300 ps
CPU time	13.65 seconds
Started	Jul 12 07:18:16 PM PDT 24
Finished	Jul 12 07:19:01 PM PDT 24
Peak memory	265020 kb
Host	smart-50d70783-d3fb-40b0-a22b-b58d25b1f9ec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229713040 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.229713040
Directory	/workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_rma_reset.2240875277
Short name	T698
Test name
Test status
Simulation time	100147923700 ps
CPU time	951.48 seconds
Started	Jul 12 07:17:57 PM PDT 24
Finished	Jul 12 07:34:23 PM PDT 24
Peak memory	264932 kb
Host	smart-79d6cca1-238d-48e3-a247-036868f89018
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240875277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 16.flash_ctrl_hw_rma_reset.2240875277
Directory	/workspace/16.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3289522309
Short name	T475
Test name
Test status
Simulation time	7578996000 ps
CPU time	148.96 seconds
Started	Jul 12 07:17:58 PM PDT 24
Finished	Jul 12 07:21:03 PM PDT 24
Peak memory	262740 kb
Host	smart-702552b1-44a9-4f30-ba0b-4b99c5307ffb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289522309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ hw_sec_otp.3289522309
Directory	/workspace/16.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.1444209435
Short name	T426
Test name
Test status
Simulation time	14715392600 ps
CPU time	142.9 seconds
Started	Jul 12 07:18:05 PM PDT 24
Finished	Jul 12 07:20:59 PM PDT 24
Peak memory	293032 kb
Host	smart-8339b5f7-3f55-4914-8a9e-0abb978140a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444209435 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.1444209435
Directory	/workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/16.flash_ctrl_lcmgr_intg.4051714733
Short name	T983
Test name
Test status
Simulation time	45951000 ps
CPU time	13.8 seconds
Started	Jul 12 07:18:15 PM PDT 24
Finished	Jul 12 07:19:00 PM PDT 24
Peak memory	265052 kb
Host	smart-8e98b221-b3ec-41a6-80df-4d230a74631c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051714733 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.4051714733
Directory	/workspace/16.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/16.flash_ctrl_mp_regions.667643284
Short name	T387
Test name
Test status
Simulation time	4734183000 ps
CPU time	147.43 seconds
Started	Jul 12 07:18:04 PM PDT 24
Finished	Jul 12 07:21:04 PM PDT 24
Peak memory	265116 kb
Host	smart-d146ab1b-6e60-474e-a91b-575b1fd6a629
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667643284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.667643284
Directory	/workspace/16.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/16.flash_ctrl_otp_reset.1197486639
Short name	T441
Test name
Test status
Simulation time	139690600 ps
CPU time	132.52 seconds
Started	Jul 12 07:17:57 PM PDT 24
Finished	Jul 12 07:20:44 PM PDT 24
Peak memory	260940 kb
Host	smart-0ad26e98-dc6e-4f9b-8e26-8dc7982d53e5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197486639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o tp_reset.1197486639
Directory	/workspace/16.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_phy_arb.4241201699
Short name	T861
Test name
Test status
Simulation time	147915700 ps
CPU time	145.95 seconds
Started	Jul 12 07:17:56 PM PDT 24
Finished	Jul 12 07:20:55 PM PDT 24
Peak memory	263260 kb
Host	smart-9c62d267-a75e-4b04-9426-ba3729c5e25b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4241201699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.4241201699
Directory	/workspace/16.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/16.flash_ctrl_prog_reset.1820516919
Short name	T926
Test name
Test status
Simulation time	26231325400 ps
CPU time	183.58 seconds
Started	Jul 12 07:18:16 PM PDT 24
Finished	Jul 12 07:21:49 PM PDT 24
Peak memory	265316 kb
Host	smart-d06567d7-2617-4d7e-b0c8-dcf507c65fa3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820516919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.flash_ctrl_prog_reset.1820516919
Directory	/workspace/16.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rand_ops.920443622
Short name	T948
Test name
Test status
Simulation time	3515902300 ps
CPU time	969.19 seconds
Started	Jul 12 07:17:57 PM PDT 24
Finished	Jul 12 07:34:41 PM PDT 24
Peak memory	288264 kb
Host	smart-789039b7-2567-4a64-a641-7815d62ca90f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920443622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.920443622
Directory	/workspace/16.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/16.flash_ctrl_re_evict.2022158162
Short name	T25
Test name
Test status
Simulation time	176525900 ps
CPU time	35.02 seconds
Started	Jul 12 07:18:15 PM PDT 24
Finished	Jul 12 07:19:21 PM PDT 24
Peak memory	275640 kb
Host	smart-d680147f-5c02-4c8c-b303-eba6c77c88f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022158162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl ash_ctrl_re_evict.2022158162
Directory	/workspace/16.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_ro.1877906748
Short name	T196
Test name
Test status
Simulation time	584272800 ps
CPU time	117.49 seconds
Started	Jul 12 07:18:03 PM PDT 24
Finished	Jul 12 07:20:34 PM PDT 24
Peak memory	281788 kb
Host	smart-f2b4d9e0-29bf-4a30-a90b-afea6a68190f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877906748 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 16.flash_ctrl_ro.1877906748
Directory	/workspace/16.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw.3831225720
Short name	T892
Test name
Test status
Simulation time	12552698500 ps
CPU time	554.48 seconds
Started	Jul 12 07:18:06 PM PDT 24
Finished	Jul 12 07:27:53 PM PDT 24
Peak memory	309728 kb
Host	smart-03c6fa5c-80b9-4bb2-a0c8-4e4b9c428b78
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831225720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.flash_ctrl_rw.3831225720
Directory	/workspace/16.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict.3312351264
Short name	T603
Test name
Test status
Simulation time	82415500 ps
CPU time	30.58 seconds
Started	Jul 12 07:18:15 PM PDT 24
Finished	Jul 12 07:19:16 PM PDT 24
Peak memory	275576 kb
Host	smart-beea7204-b624-44b0-8fbf-5c72f204c733
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312351264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl ash_ctrl_rw_evict.3312351264
Directory	/workspace/16.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2656560029
Short name	T807
Test name
Test status
Simulation time	28745100 ps
CPU time	30.81 seconds
Started	Jul 12 07:18:15 PM PDT 24
Finished	Jul 12 07:19:17 PM PDT 24
Peak memory	267456 kb
Host	smart-4375cbd6-d341-4b23-9ceb-8baa7f94a650
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656560029 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.2656560029
Directory	/workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/16.flash_ctrl_sec_info_access.1526632522
Short name	T370
Test name
Test status
Simulation time	11017166900 ps
CPU time	78.8 seconds
Started	Jul 12 07:18:15 PM PDT 24
Finished	Jul 12 07:20:04 PM PDT 24
Peak memory	263620 kb
Host	smart-1ab74972-9d2b-422e-aec9-8c5648fc8fee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1526632522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.1526632522
Directory	/workspace/16.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/16.flash_ctrl_smoke.3222370841
Short name	T485
Test name
Test status
Simulation time	29389700 ps
CPU time	52.69 seconds
Started	Jul 12 07:17:57 PM PDT 24
Finished	Jul 12 07:19:24 PM PDT 24
Peak memory	271284 kb
Host	smart-8888dbf8-2c40-44c4-816f-7a9104e8eb84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3222370841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3222370841
Directory	/workspace/16.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.flash_ctrl_wo.2035026742
Short name	T732
Test name
Test status
Simulation time	1747177100 ps
CPU time	144.39 seconds
Started	Jul 12 07:18:05 PM PDT 24
Finished	Jul 12 07:21:01 PM PDT 24
Peak memory	265324 kb
Host	smart-94aeecd1-df5e-47ee-88f7-65a6e1f324f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035026742 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.flash_ctrl_wo.2035026742
Directory	/workspace/16.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/17.flash_ctrl_alert_test.3566730398
Short name	T888
Test name
Test status
Simulation time	36428400 ps
CPU time	13.92 seconds
Started	Jul 12 07:18:31 PM PDT 24
Finished	Jul 12 07:19:12 PM PDT 24
Peak memory	265272 kb
Host	smart-8710282a-9c54-421c-894e-00bb1579e726
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566730398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test. 3566730398
Directory	/workspace/17.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.flash_ctrl_connect.2577605126
Short name	T294
Test name
Test status
Simulation time	25711700 ps
CPU time	16.18 seconds
Started	Jul 12 07:18:31 PM PDT 24
Finished	Jul 12 07:19:15 PM PDT 24
Peak memory	284392 kb
Host	smart-bb09905b-9bdc-4b35-aa02-8d1b5d6e7fd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2577605126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2577605126
Directory	/workspace/17.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/17.flash_ctrl_disable.3640786049
Short name	T1000
Test name
Test status
Simulation time	14309100 ps
CPU time	22.39 seconds
Started	Jul 12 07:18:32 PM PDT 24
Finished	Jul 12 07:19:22 PM PDT 24
Peak memory	273580 kb
Host	smart-5f1eddb3-5d00-4435-9d11-0d87b2cd9005
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640786049 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_disable.3640786049
Directory	/workspace/17.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.206812151
Short name	T19
Test name
Test status
Simulation time	10012070600 ps
CPU time	111.96 seconds
Started	Jul 12 07:18:31 PM PDT 24
Finished	Jul 12 07:20:51 PM PDT 24
Peak memory	306736 kb
Host	smart-1283c440-99e6-4379-b596-d85a45b59b71
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206812151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.206812151
Directory	/workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.260613027
Short name	T568
Test name
Test status
Simulation time	80073200 ps
CPU time	13.37 seconds
Started	Jul 12 07:18:32 PM PDT 24
Finished	Jul 12 07:19:12 PM PDT 24
Peak memory	265464 kb
Host	smart-2fc0f966-024f-4188-af31-84c7a379025a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260613027 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.260613027
Directory	/workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2503198506
Short name	T98
Test name
Test status
Simulation time	80140057200 ps
CPU time	813.69 seconds
Started	Jul 12 07:18:25 PM PDT 24
Finished	Jul 12 07:32:29 PM PDT 24
Peak memory	261048 kb
Host	smart-d9db4093-f401-4d79-84ce-e9196efeec6d
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503198506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 17.flash_ctrl_hw_rma_reset.2503198506
Directory	/workspace/17.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.4054859516
Short name	T953
Test name
Test status
Simulation time	8222379400 ps
CPU time	77.5 seconds
Started	Jul 12 07:18:25 PM PDT 24
Finished	Jul 12 07:20:11 PM PDT 24
Peak memory	263288 kb
Host	smart-cee712fc-bba7-4f1c-8321-83c32b798d6a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054859516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ hw_sec_otp.4054859516
Directory	/workspace/17.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd.2817837419
Short name	T996
Test name
Test status
Simulation time	1541997400 ps
CPU time	147.92 seconds
Started	Jul 12 07:18:32 PM PDT 24
Finished	Jul 12 07:21:27 PM PDT 24
Peak memory	293916 kb
Host	smart-7906e6ca-90d6-415b-849e-7b49ec6bca0a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817837419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_intr_rd.2817837419
Directory	/workspace/17.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2031689759
Short name	T943
Test name
Test status
Simulation time	12576233700 ps
CPU time	291.6 seconds
Started	Jul 12 07:18:32 PM PDT 24
Finished	Jul 12 07:23:51 PM PDT 24
Peak memory	290924 kb
Host	smart-d447b66b-b86f-4d76-a841-b8b2662f685c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031689759 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.2031689759
Directory	/workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/17.flash_ctrl_invalid_op.2947963870
Short name	T532
Test name
Test status
Simulation time	1034395300 ps
CPU time	78.31 seconds
Started	Jul 12 07:18:28 PM PDT 24
Finished	Jul 12 07:20:15 PM PDT 24
Peak memory	263584 kb
Host	smart-39f1a60c-9adc-425a-ba61-17d115912769
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947963870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.2 947963870
Directory	/workspace/17.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.2797974564
Short name	T757
Test name
Test status
Simulation time	38321500 ps
CPU time	13.49 seconds
Started	Jul 12 07:18:31 PM PDT 24
Finished	Jul 12 07:19:12 PM PDT 24
Peak memory	260076 kb
Host	smart-558a006a-8a28-4c7d-b81e-6217a1f57cf1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797974564 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.2797974564
Directory	/workspace/17.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/17.flash_ctrl_mp_regions.2239200854
Short name	T119
Test name
Test status
Simulation time	16639361400 ps
CPU time	315.4 seconds
Started	Jul 12 07:18:22 PM PDT 24
Finished	Jul 12 07:24:07 PM PDT 24
Peak memory	275380 kb
Host	smart-7e7c5f48-ef6d-4088-91c9-25de34cf1cec
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239200854 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.2239200854
Directory	/workspace/17.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/17.flash_ctrl_otp_reset.4977935
Short name	T852
Test name
Test status
Simulation time	33983900 ps
CPU time	132.12 seconds
Started	Jul 12 07:18:24 PM PDT 24
Finished	Jul 12 07:21:06 PM PDT 24
Peak memory	264076 kb
Host	smart-14849663-365c-4cdc-b0c4-a81cddc852f8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4977935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_ reset.4977935
Directory	/workspace/17.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_phy_arb.2407056980
Short name	T880
Test name
Test status
Simulation time	75635400 ps
CPU time	359.46 seconds
Started	Jul 12 07:18:25 PM PDT 24
Finished	Jul 12 07:24:54 PM PDT 24
Peak memory	263292 kb
Host	smart-c30edbbb-b558-41bd-806d-905cf508e91e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2407056980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.2407056980
Directory	/workspace/17.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/17.flash_ctrl_prog_reset.4230038148
Short name	T949
Test name
Test status
Simulation time	82397400 ps
CPU time	14.17 seconds
Started	Jul 12 07:18:32 PM PDT 24
Finished	Jul 12 07:19:13 PM PDT 24
Peak memory	259828 kb
Host	smart-01cc5f8c-f684-4311-b5d8-f95a0f94cc9b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230038148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.flash_ctrl_prog_reset.4230038148
Directory	/workspace/17.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rand_ops.2626393041
Short name	T38
Test name
Test status
Simulation time	800113100 ps
CPU time	453.83 seconds
Started	Jul 12 07:18:22 PM PDT 24
Finished	Jul 12 07:26:25 PM PDT 24
Peak memory	283488 kb
Host	smart-88f93bae-764f-49db-8733-4a4d2b9ff444
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626393041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2626393041
Directory	/workspace/17.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/17.flash_ctrl_re_evict.2827268933
Short name	T1103
Test name
Test status
Simulation time	74480400 ps
CPU time	35.73 seconds
Started	Jul 12 07:18:32 PM PDT 24
Finished	Jul 12 07:19:35 PM PDT 24
Peak memory	275612 kb
Host	smart-a34aa308-4b47-4af6-85f5-eb792020479c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827268933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl ash_ctrl_re_evict.2827268933
Directory	/workspace/17.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_ro.3195871800
Short name	T632
Test name
Test status
Simulation time	490166200 ps
CPU time	132.72 seconds
Started	Jul 12 07:18:23 PM PDT 24
Finished	Jul 12 07:21:06 PM PDT 24
Peak memory	280972 kb
Host	smart-877c2e19-aec9-474e-9d84-396b2f36bb27
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195871800 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 17.flash_ctrl_ro.3195871800
Directory	/workspace/17.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw.28823487
Short name	T773
Test name
Test status
Simulation time	3777537100 ps
CPU time	616.23 seconds
Started	Jul 12 07:18:24 PM PDT 24
Finished	Jul 12 07:29:10 PM PDT 24
Peak memory	309696 kb
Host	smart-e6ebc089-4f50-44c9-a45b-773d67d9fc4a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28823487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.28823487
Directory	/workspace/17.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict.868235706
Short name	T993
Test name
Test status
Simulation time	108763600 ps
CPU time	28.72 seconds
Started	Jul 12 07:18:33 PM PDT 24
Finished	Jul 12 07:19:28 PM PDT 24
Peak memory	267528 kb
Host	smart-e6f81fc0-9ed7-4e8c-a267-89e2b7610ac6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868235706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_rw_evict.868235706
Directory	/workspace/17.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.492251221
Short name	T706
Test name
Test status
Simulation time	28197500 ps
CPU time	27.94 seconds
Started	Jul 12 07:18:30 PM PDT 24
Finished	Jul 12 07:19:26 PM PDT 24
Peak memory	275640 kb
Host	smart-008e14a1-fd00-4bc5-aebd-ac345e7762e0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492251221 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.492251221
Directory	/workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/17.flash_ctrl_smoke.218976984
Short name	T505
Test name
Test status
Simulation time	65886000 ps
CPU time	76.7 seconds
Started	Jul 12 07:18:23 PM PDT 24
Finished	Jul 12 07:20:10 PM PDT 24
Peak memory	277060 kb
Host	smart-b79ca307-27b4-43a0-ad7e-ac8e4e5e775c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=218976984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.218976984
Directory	/workspace/17.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.flash_ctrl_wo.3026123139
Short name	T465
Test name
Test status
Simulation time	19620242600 ps
CPU time	200.02 seconds
Started	Jul 12 07:18:22 PM PDT 24
Finished	Jul 12 07:22:13 PM PDT 24
Peak memory	265244 kb
Host	smart-fe4900c7-0c25-4f9d-ade5-4128433c8dbd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026123139 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.flash_ctrl_wo.3026123139
Directory	/workspace/17.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/18.flash_ctrl_alert_test.4208143642
Short name	T461
Test name
Test status
Simulation time	59304200 ps
CPU time	14.1 seconds
Started	Jul 12 07:19:08 PM PDT 24
Finished	Jul 12 07:19:31 PM PDT 24
Peak memory	258304 kb
Host	smart-ed9adca0-ddcc-4f88-8d8b-6958e8cbe7a2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208143642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test. 4208143642
Directory	/workspace/18.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.flash_ctrl_connect.3651294632
Short name	T752
Test name
Test status
Simulation time	30074600 ps
CPU time	16.46 seconds
Started	Jul 12 07:18:54 PM PDT 24
Finished	Jul 12 07:19:26 PM PDT 24
Peak memory	274880 kb
Host	smart-360d0338-81d9-4404-ad05-75a31cfbc36b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651294632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3651294632
Directory	/workspace/18.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/18.flash_ctrl_disable.1519326009
Short name	T844
Test name
Test status
Simulation time	10946100 ps
CPU time	21.28 seconds
Started	Jul 12 07:18:55 PM PDT 24
Finished	Jul 12 07:19:31 PM PDT 24
Peak memory	265600 kb
Host	smart-f64ae00b-5644-49ec-bd9e-9d7604865f57
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519326009 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_disable.1519326009
Directory	/workspace/18.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2238235235
Short name	T73
Test name
Test status
Simulation time	10012723900 ps
CPU time	309.07 seconds
Started	Jul 12 07:19:07 PM PDT 24
Finished	Jul 12 07:24:25 PM PDT 24
Peak memory	301584 kb
Host	smart-61248039-63be-49c9-b9e5-5d083ccf27cd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238235235 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.2238235235
Directory	/workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.2111003365
Short name	T865
Test name
Test status
Simulation time	50588200 ps
CPU time	13.51 seconds
Started	Jul 12 07:18:54 PM PDT 24
Finished	Jul 12 07:19:23 PM PDT 24
Peak memory	258788 kb
Host	smart-40952035-6e3c-420d-9948-b348131f8d2d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111003365 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.2111003365
Directory	/workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_rma_reset.3537448426
Short name	T703
Test name
Test status
Simulation time	40123269700 ps
CPU time	864.92 seconds
Started	Jul 12 07:18:40 PM PDT 24
Finished	Jul 12 07:33:28 PM PDT 24
Peak memory	260004 kb
Host	smart-015b62c4-d8d7-4347-9e06-ecd80350f543
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537448426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 18.flash_ctrl_hw_rma_reset.3537448426
Directory	/workspace/18.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.756576745
Short name	T526
Test name
Test status
Simulation time	2596517600 ps
CPU time	77.43 seconds
Started	Jul 12 07:18:39 PM PDT 24
Finished	Jul 12 07:20:20 PM PDT 24
Peak memory	262072 kb
Host	smart-d33beb75-7d31-4774-8067-c78eb119cdb5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756576745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_h w_sec_otp.756576745
Directory	/workspace/18.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd.1345774149
Short name	T1017
Test name
Test status
Simulation time	1689726800 ps
CPU time	137.75 seconds
Started	Jul 12 07:18:55 PM PDT 24
Finished	Jul 12 07:21:27 PM PDT 24
Peak memory	293836 kb
Host	smart-96327578-9847-4aa7-b66b-9b05a10ebeb9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345774149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla sh_ctrl_intr_rd.1345774149
Directory	/workspace/18.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.814086104
Short name	T628
Test name
Test status
Simulation time	7703437700 ps
CPU time	197.04 seconds
Started	Jul 12 07:18:53 PM PDT 24
Finished	Jul 12 07:22:26 PM PDT 24
Peak memory	293280 kb
Host	smart-0e988869-0fcb-4ca0-a46d-58439d80ce58
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814086104 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.814086104
Directory	/workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/18.flash_ctrl_invalid_op.771159327
Short name	T531
Test name
Test status
Simulation time	6104603900 ps
CPU time	68.21 seconds
Started	Jul 12 07:18:40 PM PDT 24
Finished	Jul 12 07:20:11 PM PDT 24
Peak memory	262784 kb
Host	smart-b7a2017b-4732-499b-81cc-65985c94ec0d
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771159327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.771159327
Directory	/workspace/18.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/18.flash_ctrl_lcmgr_intg.3925866268
Short name	T611
Test name
Test status
Simulation time	26872500 ps
CPU time	13.49 seconds
Started	Jul 12 07:18:55 PM PDT 24
Finished	Jul 12 07:19:23 PM PDT 24
Peak memory	260016 kb
Host	smart-899df79d-52de-4666-b884-2402477e7c74
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925866268 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.3925866268
Directory	/workspace/18.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/18.flash_ctrl_mp_regions.1757205400
Short name	T1083
Test name
Test status
Simulation time	10875173000 ps
CPU time	350.45 seconds
Started	Jul 12 07:18:43 PM PDT 24
Finished	Jul 12 07:24:54 PM PDT 24
Peak memory	273764 kb
Host	smart-989ed7d3-c336-4f52-9906-77266c0a329f
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757205400 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.1757205400
Directory	/workspace/18.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/18.flash_ctrl_otp_reset.4203695559
Short name	T434
Test name
Test status
Simulation time	43184900 ps
CPU time	108.92 seconds
Started	Jul 12 07:18:39 PM PDT 24
Finished	Jul 12 07:20:52 PM PDT 24
Peak memory	260940 kb
Host	smart-5b17f59e-ae36-4330-9922-32da06bdd963
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203695559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o tp_reset.4203695559
Directory	/workspace/18.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_phy_arb.4027066648
Short name	T810
Test name
Test status
Simulation time	7958968800 ps
CPU time	319.17 seconds
Started	Jul 12 07:18:39 PM PDT 24
Finished	Jul 12 07:24:22 PM PDT 24
Peak memory	263200 kb
Host	smart-ea2e4ad1-f5d7-4419-9d16-f324aabaf8dc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4027066648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.4027066648
Directory	/workspace/18.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/18.flash_ctrl_prog_reset.1237889977
Short name	T1051
Test name
Test status
Simulation time	44003500 ps
CPU time	14.23 seconds
Started	Jul 12 07:18:56 PM PDT 24
Finished	Jul 12 07:19:24 PM PDT 24
Peak memory	265360 kb
Host	smart-9ac4d7fb-77d8-4e9b-aa88-a07227f9c55e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237889977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.flash_ctrl_prog_reset.1237889977
Directory	/workspace/18.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rand_ops.3307324257
Short name	T573
Test name
Test status
Simulation time	164838900 ps
CPU time	1173.87 seconds
Started	Jul 12 07:18:41 PM PDT 24
Finished	Jul 12 07:38:37 PM PDT 24
Peak memory	287424 kb
Host	smart-aa4fba7f-0c49-4c06-8661-d30349f37257
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3307324257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3307324257
Directory	/workspace/18.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/18.flash_ctrl_re_evict.3069706758
Short name	T262
Test name
Test status
Simulation time	1093065200 ps
CPU time	35.23 seconds
Started	Jul 12 07:18:53 PM PDT 24
Finished	Jul 12 07:19:44 PM PDT 24
Peak memory	275688 kb
Host	smart-6c3cd6fb-1f80-4b33-a846-7f8b53818775
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069706758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_re_evict.3069706758
Directory	/workspace/18.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_ro.3281337211
Short name	T530
Test name
Test status
Simulation time	2668626100 ps
CPU time	139.2 seconds
Started	Jul 12 07:18:40 PM PDT 24
Finished	Jul 12 07:21:22 PM PDT 24
Peak memory	291428 kb
Host	smart-f3649ba2-d360-472c-a82a-5f2a316dc0ea
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281337211 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 18.flash_ctrl_ro.3281337211
Directory	/workspace/18.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw.3013380216
Short name	T625
Test name
Test status
Simulation time	3597505500 ps
CPU time	684.05 seconds
Started	Jul 12 07:18:39 PM PDT 24
Finished	Jul 12 07:30:27 PM PDT 24
Peak memory	314492 kb
Host	smart-19c098b4-c33a-49ec-b002-7ebc4b28b3fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013380216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.flash_ctrl_rw.3013380216
Directory	/workspace/18.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict.2477253225
Short name	T1067
Test name
Test status
Simulation time	75736600 ps
CPU time	30.68 seconds
Started	Jul 12 07:18:56 PM PDT 24
Finished	Jul 12 07:19:41 PM PDT 24
Peak memory	275616 kb
Host	smart-319df747-9580-4e95-ae5c-da0d5871ff26
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477253225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_rw_evict.2477253225
Directory	/workspace/18.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.1533936044
Short name	T626
Test name
Test status
Simulation time	33103200 ps
CPU time	30.22 seconds
Started	Jul 12 07:18:54 PM PDT 24
Finished	Jul 12 07:19:39 PM PDT 24
Peak memory	268484 kb
Host	smart-9709379e-075a-4b4f-bd6a-56a162cdba73
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533936044 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.1533936044
Directory	/workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/18.flash_ctrl_sec_info_access.1987366545
Short name	T833
Test name
Test status
Simulation time	1854716400 ps
CPU time	72.14 seconds
Started	Jul 12 07:18:56 PM PDT 24
Finished	Jul 12 07:20:22 PM PDT 24
Peak memory	263712 kb
Host	smart-bbf379b2-bac5-4157-a6cf-2296f7923256
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987366545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1987366545
Directory	/workspace/18.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/18.flash_ctrl_smoke.1120140052
Short name	T601
Test name
Test status
Simulation time	189817000 ps
CPU time	99.17 seconds
Started	Jul 12 07:18:38 PM PDT 24
Finished	Jul 12 07:20:41 PM PDT 24
Peak memory	275968 kb
Host	smart-89f440e4-b54b-4f42-b114-ff83a138a15a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1120140052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1120140052
Directory	/workspace/18.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.flash_ctrl_wo.713474926
Short name	T133
Test name
Test status
Simulation time	2682332300 ps
CPU time	216.3 seconds
Started	Jul 12 07:18:42 PM PDT 24
Finished	Jul 12 07:22:40 PM PDT 24
Peak memory	264956 kb
Host	smart-0ac0579e-8bc1-4e58-9883-5a3234ce6d08
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713474926 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 18.flash_ctrl_wo.713474926
Directory	/workspace/18.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/19.flash_ctrl_alert_test.3091198217
Short name	T427
Test name
Test status
Simulation time	49460000 ps
CPU time	14.06 seconds
Started	Jul 12 07:19:23 PM PDT 24
Finished	Jul 12 07:19:46 PM PDT 24
Peak memory	265272 kb
Host	smart-6fb673f9-46c9-4403-b667-00939ab63109
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091198217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test. 3091198217
Directory	/workspace/19.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.flash_ctrl_connect.642437982
Short name	T464
Test name
Test status
Simulation time	46800700 ps
CPU time	16.27 seconds
Started	Jul 12 07:19:25 PM PDT 24
Finished	Jul 12 07:19:53 PM PDT 24
Peak memory	284328 kb
Host	smart-6d78522d-a4da-4488-8ecb-1ebc17253130
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=642437982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.642437982
Directory	/workspace/19.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/19.flash_ctrl_disable.2262996668
Short name	T352
Test name
Test status
Simulation time	45761700 ps
CPU time	22.16 seconds
Started	Jul 12 07:19:23 PM PDT 24
Finished	Jul 12 07:19:54 PM PDT 24
Peak memory	273568 kb
Host	smart-c2233b13-a4c4-4ca2-a745-0a248c2c8a9e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262996668 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_disable.2262996668
Directory	/workspace/19.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.272289274
Short name	T184
Test name
Test status
Simulation time	10026829300 ps
CPU time	66.38 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:20:42 PM PDT 24
Peak memory	300080 kb
Host	smart-c68de029-1a2c-490e-a535-118848d909bf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272289274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.272289274
Directory	/workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.326884935
Short name	T920
Test name
Test status
Simulation time	15791900 ps
CPU time	13.4 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:19:49 PM PDT 24
Peak memory	265032 kb
Host	smart-600a9f4c-2a97-4614-b370-5b55aed44b1b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326884935 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.326884935
Directory	/workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_rma_reset.251185721
Short name	T659
Test name
Test status
Simulation time	40128967400 ps
CPU time	892.68 seconds
Started	Jul 12 07:19:06 PM PDT 24
Finished	Jul 12 07:34:08 PM PDT 24
Peak memory	260944 kb
Host	smart-f25df849-1bf9-4e76-a875-4bc1c1002503
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251185721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.flash_ctrl_hw_rma_reset.251185721
Directory	/workspace/19.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.4280761146
Short name	T443
Test name
Test status
Simulation time	12429110700 ps
CPU time	102.93 seconds
Started	Jul 12 07:19:07 PM PDT 24
Finished	Jul 12 07:20:59 PM PDT 24
Peak memory	260888 kb
Host	smart-252c94a9-78fc-4991-b1b2-19d28cdca61e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280761146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ hw_sec_otp.4280761146
Directory	/workspace/19.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd.1039753878
Short name	T1044
Test name
Test status
Simulation time	1152380200 ps
CPU time	129.7 seconds
Started	Jul 12 07:19:07 PM PDT 24
Finished	Jul 12 07:21:25 PM PDT 24
Peak memory	294084 kb
Host	smart-a583eda1-a0be-4abc-894f-ddd6b38030a4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039753878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_intr_rd.1039753878
Directory	/workspace/19.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3748984288
Short name	T405
Test name
Test status
Simulation time	19253068200 ps
CPU time	233.09 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:23:29 PM PDT 24
Peak memory	290012 kb
Host	smart-f47ae9d5-40c2-47a9-a7e3-59ef85d04020
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748984288 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.3748984288
Directory	/workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/19.flash_ctrl_invalid_op.651351879
Short name	T1101
Test name
Test status
Simulation time	8763740500 ps
CPU time	71.5 seconds
Started	Jul 12 07:19:07 PM PDT 24
Finished	Jul 12 07:20:27 PM PDT 24
Peak memory	260568 kb
Host	smart-380aa948-419c-438b-b3ba-b04bd0845b06
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651351879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.651351879
Directory	/workspace/19.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.3340018446
Short name	T662
Test name
Test status
Simulation time	58918400 ps
CPU time	13.51 seconds
Started	Jul 12 07:19:23 PM PDT 24
Finished	Jul 12 07:19:46 PM PDT 24
Peak memory	265020 kb
Host	smart-1917f286-0a8d-4fe4-9cb6-168f1f788196
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340018446 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.3340018446
Directory	/workspace/19.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/19.flash_ctrl_mp_regions.2648862530
Short name	T1037
Test name
Test status
Simulation time	6021158900 ps
CPU time	161.9 seconds
Started	Jul 12 07:19:07 PM PDT 24
Finished	Jul 12 07:21:57 PM PDT 24
Peak memory	265112 kb
Host	smart-6e099a03-973d-47d4-8f15-ed9621fa4878
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648862530 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.2648862530
Directory	/workspace/19.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/19.flash_ctrl_otp_reset.3092874180
Short name	T157
Test name
Test status
Simulation time	44051500 ps
CPU time	132.21 seconds
Started	Jul 12 07:19:08 PM PDT 24
Finished	Jul 12 07:21:29 PM PDT 24
Peak memory	261200 kb
Host	smart-59ba16fe-bca4-4a7d-a6cd-35bb2d415767
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092874180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o tp_reset.3092874180
Directory	/workspace/19.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_phy_arb.956268735
Short name	T874
Test name
Test status
Simulation time	182062800 ps
CPU time	315.81 seconds
Started	Jul 12 07:19:08 PM PDT 24
Finished	Jul 12 07:24:32 PM PDT 24
Peak memory	263268 kb
Host	smart-ef4c5d79-2057-47f7-b5a5-304412459a97
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=956268735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.956268735
Directory	/workspace/19.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/19.flash_ctrl_prog_reset.4111677528
Short name	T755
Test name
Test status
Simulation time	25972800 ps
CPU time	13.76 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:19:48 PM PDT 24
Peak memory	259036 kb
Host	smart-e2285ecf-df8d-4617-affa-943ece6043fe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111677528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.flash_ctrl_prog_reset.4111677528
Directory	/workspace/19.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rand_ops.2028556847
Short name	T616
Test name
Test status
Simulation time	373739700 ps
CPU time	228.63 seconds
Started	Jul 12 07:19:07 PM PDT 24
Finished	Jul 12 07:23:04 PM PDT 24
Peak memory	281604 kb
Host	smart-ec8099fb-d33d-491c-b767-35b9b0802c8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028556847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.2028556847
Directory	/workspace/19.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/19.flash_ctrl_ro.3750392624
Short name	T404
Test name
Test status
Simulation time	563255200 ps
CPU time	110.64 seconds
Started	Jul 12 07:19:06 PM PDT 24
Finished	Jul 12 07:21:06 PM PDT 24
Peak memory	289912 kb
Host	smart-c2e14289-6f21-4411-9fd1-a544e9d12e89
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750392624 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 19.flash_ctrl_ro.3750392624
Directory	/workspace/19.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw.1142924864
Short name	T105
Test name
Test status
Simulation time	4578421800 ps
CPU time	752.53 seconds
Started	Jul 12 07:19:07 PM PDT 24
Finished	Jul 12 07:31:48 PM PDT 24
Peak memory	309532 kb
Host	smart-1c32aac2-c1f5-475d-9585-9c49b655abdd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142924864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.flash_ctrl_rw.1142924864
Directory	/workspace/19.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict.2501992135
Short name	T297
Test name
Test status
Simulation time	69200300 ps
CPU time	30.82 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:20:05 PM PDT 24
Peak memory	275652 kb
Host	smart-2393d022-4ba3-471d-b68a-6a3abd2d8bb2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501992135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_rw_evict.2501992135
Directory	/workspace/19.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.892834374
Short name	T914
Test name
Test status
Simulation time	41918300 ps
CPU time	32.56 seconds
Started	Jul 12 07:19:26 PM PDT 24
Finished	Jul 12 07:20:10 PM PDT 24
Peak memory	275884 kb
Host	smart-366086df-2fc4-4af7-b4dc-2779801528b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892834374 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.892834374
Directory	/workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/19.flash_ctrl_sec_info_access.3095355681
Short name	T360
Test name
Test status
Simulation time	11393959500 ps
CPU time	74.47 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:20:50 PM PDT 24
Peak memory	263600 kb
Host	smart-6e6dad58-a8ce-4e79-a7a3-9124808df86f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3095355681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3095355681
Directory	/workspace/19.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/19.flash_ctrl_smoke.1185297121
Short name	T564
Test name
Test status
Simulation time	63436000 ps
CPU time	218.42 seconds
Started	Jul 12 07:19:08 PM PDT 24
Finished	Jul 12 07:22:55 PM PDT 24
Peak memory	281640 kb
Host	smart-22676ff1-7263-4bec-a09c-0d1addb42310
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185297121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1185297121
Directory	/workspace/19.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.flash_ctrl_wo.3101842794
Short name	T438
Test name
Test status
Simulation time	2036149800 ps
CPU time	170.28 seconds
Started	Jul 12 07:19:05 PM PDT 24
Finished	Jul 12 07:22:05 PM PDT 24
Peak memory	260000 kb
Host	smart-fa15f489-5754-408b-a5a6-1facf39da529
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101842794 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.flash_ctrl_wo.3101842794
Directory	/workspace/19.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_access_after_disable.2687959658
Short name	T46
Test name
Test status
Simulation time	12035700 ps
CPU time	13.61 seconds
Started	Jul 12 07:10:09 PM PDT 24
Finished	Jul 12 07:10:41 PM PDT 24
Peak memory	261496 kb
Host	smart-41cc179a-7a64-4479-8181-9e1e41b493c2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687959658 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.2687959658
Directory	/workspace/2.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_alert_test.3379407410
Short name	T640
Test name
Test status
Simulation time	63960700 ps
CPU time	13.85 seconds
Started	Jul 12 07:10:19 PM PDT 24
Finished	Jul 12 07:10:46 PM PDT 24
Peak memory	258280 kb
Host	smart-2d8c15f2-2de8-4b3c-a639-8687d56ab073
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379407410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.3 379407410
Directory	/workspace/2.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.flash_ctrl_connect.2640760421
Short name	T760
Test name
Test status
Simulation time	14139300 ps
CPU time	13.46 seconds
Started	Jul 12 07:10:01 PM PDT 24
Finished	Jul 12 07:10:21 PM PDT 24
Peak memory	274872 kb
Host	smart-a9cb3293-d633-40e5-992f-96c4173401cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640760421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.2640760421
Directory	/workspace/2.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/2.flash_ctrl_disable.4085053581
Short name	T339
Test name
Test status
Simulation time	10208600 ps
CPU time	21.84 seconds
Started	Jul 12 07:09:59 PM PDT 24
Finished	Jul 12 07:10:27 PM PDT 24
Peak memory	273604 kb
Host	smart-3941075a-47b3-481c-84e4-c8e3b3e1a004
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085053581 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_disable.4085053581
Directory	/workspace/2.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_mp.1459884742
Short name	T986
Test name
Test status
Simulation time	5421499600 ps
CPU time	2215.4 seconds
Started	Jul 12 07:09:32 PM PDT 24
Finished	Jul 12 07:46:34 PM PDT 24
Peak memory	265212 kb
Host	smart-d06babeb-4411-4c3c-b076-6d3146cc5a8e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1459884742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.1459884742
Directory	/workspace/2.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_type.3949041200
Short name	T75
Test name
Test status
Simulation time	590945800 ps
CPU time	1769.81 seconds
Started	Jul 12 07:09:30 PM PDT 24
Finished	Jul 12 07:39:07 PM PDT 24
Peak memory	264500 kb
Host	smart-c750bbeb-b70f-4ac6-8fd5-6d0212dd8395
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949041200 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.3949041200
Directory	/workspace/2.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_win.3954762052
Short name	T277
Test name
Test status
Simulation time	401896100 ps
CPU time	995.88 seconds
Started	Jul 12 07:09:31 PM PDT 24
Finished	Jul 12 07:26:14 PM PDT 24
Peak memory	273436 kb
Host	smart-34e7c864-2b65-46ec-aad2-3a5fbab97aef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954762052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.3954762052
Directory	/workspace/2.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fetch_code.754301148
Short name	T59
Test name
Test status
Simulation time	2430417000 ps
CPU time	34.01 seconds
Started	Jul 12 07:09:26 PM PDT 24
Finished	Jul 12 07:10:08 PM PDT 24
Peak memory	262456 kb
Host	smart-842df46b-9bcf-4983-95b5-6a945d9c487b
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754301148 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.754301148
Directory	/workspace/2.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fs_sup.159955844
Short name	T666
Test name
Test status
Simulation time	295522600 ps
CPU time	35.96 seconds
Started	Jul 12 07:10:08 PM PDT 24
Finished	Jul 12 07:11:00 PM PDT 24
Peak memory	265272 kb
Host	smart-28e72214-e6ff-4b94-a371-5a34a8dd739a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159955844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_fs_sup.159955844
Directory	/workspace/2.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/2.flash_ctrl_full_mem_access.324411834
Short name	T123
Test name
Test status
Simulation time	143801226000 ps
CPU time	4485.16 seconds
Started	Jul 12 07:09:33 PM PDT 24
Finished	Jul 12 08:24:25 PM PDT 24
Peak memory	265064 kb
Host	smart-d6b45c36-e26b-41bc-8b0f-768f7a55b2c7
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324411834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct rl_full_mem_access.324411834
Directory	/workspace/2.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_addr_infection.861638017
Short name	T1020
Test name
Test status
Simulation time	63744300 ps
CPU time	30.38 seconds
Started	Jul 12 07:10:20 PM PDT 24
Finished	Jul 12 07:11:04 PM PDT 24
Peak memory	275732 kb
Host	smart-f2df049f-46ca-4157-a98d-d87b0ce45547
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861638017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_host_addr_infection.861638017
Directory	/workspace/2.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3817989243
Short name	T820
Test name
Test status
Simulation time	288335800000 ps
CPU time	2799.97 seconds
Started	Jul 12 07:09:26 PM PDT 24
Finished	Jul 12 07:56:14 PM PDT 24
Peak memory	264196 kb
Host	smart-ff162366-5ae8-4d4d-a194-b6491abb32ac
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817989243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.flash_ctrl_host_ctrl_arb.3817989243
Directory	/workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_dir_rd.186827962
Short name	T1041
Test name
Test status
Simulation time	240647700 ps
CPU time	98.97 seconds
Started	Jul 12 07:09:24 PM PDT 24
Finished	Jul 12 07:11:12 PM PDT 24
Peak memory	265240 kb
Host	smart-625cedf4-84fe-453c-a995-e405def99c41
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=186827962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.186827962
Directory	/workspace/2.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.2109987261
Short name	T905
Test name
Test status
Simulation time	10019928200 ps
CPU time	100.83 seconds
Started	Jul 12 07:10:19 PM PDT 24
Finished	Jul 12 07:12:13 PM PDT 24
Peak memory	332476 kb
Host	smart-f9a98ca8-ec95-4e96-ac8b-1192f2f218e2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109987261 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.2109987261
Directory	/workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.1874537233
Short name	T268
Test name
Test status
Simulation time	15373200 ps
CPU time	13.37 seconds
Started	Jul 12 07:10:20 PM PDT 24
Finished	Jul 12 07:10:47 PM PDT 24
Peak memory	258532 kb
Host	smart-5a8dd5db-fa5f-480e-adaa-8519b8a9f019
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874537233 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.1874537233
Directory	/workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma.1105144970
Short name	T1036
Test name
Test status
Simulation time	139785637700 ps
CPU time	2127.91 seconds
Started	Jul 12 07:09:23 PM PDT 24
Finished	Jul 12 07:45:01 PM PDT 24
Peak memory	260432 kb
Host	smart-83f5ec20-9061-485a-b365-75b87a90c0b7
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105144970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.flash_ctrl_hw_rma.1105144970
Directory	/workspace/2.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.2068754558
Short name	T749
Test name
Test status
Simulation time	260208031700 ps
CPU time	935.01 seconds
Started	Jul 12 07:09:23 PM PDT 24
Finished	Jul 12 07:25:07 PM PDT 24
Peak memory	264532 kb
Host	smart-5b92985f-6fe0-41db-ac5c-acecdddebfcb
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068754558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.flash_ctrl_hw_rma_reset.2068754558
Directory	/workspace/2.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2490282345
Short name	T825
Test name
Test status
Simulation time	1716489000 ps
CPU time	150.48 seconds
Started	Jul 12 07:09:26 PM PDT 24
Finished	Jul 12 07:12:05 PM PDT 24
Peak memory	260856 kb
Host	smart-cf1ac463-7fe3-4610-b391-6bd2558d0971
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490282345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h w_sec_otp.2490282345
Directory	/workspace/2.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_integrity.2716059558
Short name	T232
Test name
Test status
Simulation time	17626495400 ps
CPU time	567.27 seconds
Started	Jul 12 07:10:02 PM PDT 24
Finished	Jul 12 07:19:36 PM PDT 24
Peak memory	338872 kb
Host	smart-056d3e7b-9166-4aa7-b29e-0fa3af416cd7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716059558 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_integrity.2716059558
Directory	/workspace/2.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd.3095363855
Short name	T704
Test name
Test status
Simulation time	4726046800 ps
CPU time	208.35 seconds
Started	Jul 12 07:09:59 PM PDT 24
Finished	Jul 12 07:13:34 PM PDT 24
Peak memory	284828 kb
Host	smart-0cc25a3d-dc09-4f19-afd8-9ffd38a5d225
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095363855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_intr_rd.3095363855
Directory	/workspace/2.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.917431799
Short name	T459
Test name
Test status
Simulation time	14249929200 ps
CPU time	158.07 seconds
Started	Jul 12 07:10:00 PM PDT 24
Finished	Jul 12 07:12:45 PM PDT 24
Peak memory	293600 kb
Host	smart-ec40c0e4-fdab-4dc1-9183-1b7328bfa1d3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917431799 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.917431799
Directory	/workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr.1108643500
Short name	T750
Test name
Test status
Simulation time	4313425000 ps
CPU time	74.16 seconds
Started	Jul 12 07:10:01 PM PDT 24
Finished	Jul 12 07:11:22 PM PDT 24
Peak memory	265208 kb
Host	smart-e8e2e815-c363-437b-915c-991f53402276
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108643500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_intr_wr.1108643500
Directory	/workspace/2.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.418159799
Short name	T1012
Test name
Test status
Simulation time	265406192700 ps
CPU time	388.93 seconds
Started	Jul 12 07:09:59 PM PDT 24
Finished	Jul 12 07:16:34 PM PDT 24
Peak memory	260544 kb
Host	smart-a11027c5-f659-45c8-b2f7-414c803f0344
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418 159799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.418159799
Directory	/workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_invalid_op.2567843433
Short name	T126
Test name
Test status
Simulation time	3365528400 ps
CPU time	66.99 seconds
Started	Jul 12 07:09:31 PM PDT 24
Finished	Jul 12 07:10:45 PM PDT 24
Peak memory	262644 kb
Host	smart-48d36c4a-1fd6-45c2-8ccd-5950c71acdd3
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567843433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2567843433
Directory	/workspace/2.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.3595886159
Short name	T484
Test name
Test status
Simulation time	85695700 ps
CPU time	13.68 seconds
Started	Jul 12 07:10:21 PM PDT 24
Finished	Jul 12 07:10:47 PM PDT 24
Peak memory	265064 kb
Host	smart-184e2b86-29f7-4e56-99c7-502d83403f30
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595886159 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.3595886159
Directory	/workspace/2.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mp_regions.2776479010
Short name	T654
Test name
Test status
Simulation time	4104887800 ps
CPU time	137.88 seconds
Started	Jul 12 07:09:28 PM PDT 24
Finished	Jul 12 07:11:54 PM PDT 24
Peak memory	265172 kb
Host	smart-f15a03e8-3607-45cc-9018-b566bed34b95
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776479010 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.2776479010
Directory	/workspace/2.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/2.flash_ctrl_oversize_error.3579772128
Short name	T720
Test name
Test status
Simulation time	3683457700 ps
CPU time	166.36 seconds
Started	Jul 12 07:10:01 PM PDT 24
Finished	Jul 12 07:12:53 PM PDT 24
Peak memory	281824 kb
Host	smart-63c5fed6-51c7-4542-9796-4992310e4a0d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579772128 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.3579772128
Directory	/workspace/2.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb.1986208151
Short name	T605
Test name
Test status
Simulation time	2343808500 ps
CPU time	642.96 seconds
Started	Jul 12 07:09:23 PM PDT 24
Finished	Jul 12 07:20:15 PM PDT 24
Peak memory	263096 kb
Host	smart-82713923-0835-4f67-8d98-cabde2b80162
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1986208151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1986208151
Directory	/workspace/2.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.2669748676
Short name	T177
Test name
Test status
Simulation time	15541700 ps
CPU time	14.43 seconds
Started	Jul 12 07:10:10 PM PDT 24
Finished	Jul 12 07:10:43 PM PDT 24
Peak memory	262984 kb
Host	smart-85fa5adc-4917-451a-99ae-851eec19a2ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669748676 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.2669748676
Directory	/workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_prog_reset.3041456936
Short name	T491
Test name
Test status
Simulation time	12180489000 ps
CPU time	184.03 seconds
Started	Jul 12 07:10:00 PM PDT 24
Finished	Jul 12 07:13:11 PM PDT 24
Peak memory	260568 kb
Host	smart-6c766d2a-6010-45de-b9f6-eb8d5ceec5b1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041456936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.flash_ctrl_prog_reset.3041456936
Directory	/workspace/2.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rand_ops.1937028323
Short name	T482
Test name
Test status
Simulation time	177765000 ps
CPU time	732.74 seconds
Started	Jul 12 07:09:27 PM PDT 24
Finished	Jul 12 07:21:47 PM PDT 24
Peak memory	285616 kb
Host	smart-4b41c47c-edb9-41a1-bdcb-66701d20db69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937028323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1937028323
Directory	/workspace/2.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_buff_evict.2765596357
Short name	T529
Test name
Test status
Simulation time	1471946900 ps
CPU time	117.4 seconds
Started	Jul 12 07:09:23 PM PDT 24
Finished	Jul 12 07:11:30 PM PDT 24
Peak memory	262780 kb
Host	smart-8bc1332e-bdb8-4c7e-ac85-84d950add537
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2765596357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2765596357
Directory	/workspace/2.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_intg.1615487821
Short name	T845
Test name
Test status
Simulation time	65254800 ps
CPU time	31.66 seconds
Started	Jul 12 07:10:03 PM PDT 24
Finished	Jul 12 07:10:42 PM PDT 24
Peak memory	275764 kb
Host	smart-9af36f97-9636-4cb0-be83-7e2d806254b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615487821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_rd_intg.1615487821
Directory	/workspace/2.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_re_evict.2018775728
Short name	T644
Test name
Test status
Simulation time	77792700 ps
CPU time	35.21 seconds
Started	Jul 12 07:10:03 PM PDT 24
Finished	Jul 12 07:10:45 PM PDT 24
Peak memory	275660 kb
Host	smart-6c8248f2-b962-4e86-a934-9d8f7fba0cd9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018775728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_re_evict.2018775728
Directory	/workspace/2.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.2986736291
Short name	T917
Test name
Test status
Simulation time	37170600 ps
CPU time	21.69 seconds
Started	Jul 12 07:09:50 PM PDT 24
Finished	Jul 12 07:10:20 PM PDT 24
Peak memory	265508 kb
Host	smart-90217dc7-54c8-4e6f-897b-74f079cb92c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986736291 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.2986736291
Directory	/workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.4009357257
Short name	T503
Test name
Test status
Simulation time	193333800 ps
CPU time	22.77 seconds
Started	Jul 12 07:09:41 PM PDT 24
Finished	Jul 12 07:10:11 PM PDT 24
Peak memory	265360 kb
Host	smart-ef4fb23e-17fd-4d86-bb5b-630a915e76d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009357257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_read_word_sweep_serr.4009357257
Directory	/workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rma_err.82888046
Short name	T71
Test name
Test status
Simulation time	562426809300 ps
CPU time	1230.25 seconds
Started	Jul 12 07:10:19 PM PDT 24
Finished	Jul 12 07:31:03 PM PDT 24
Peak memory	262780 kb
Host	smart-ae08063c-8ff8-468e-92e0-c168e526f33f
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82888046 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.82888046
Directory	/workspace/2.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro.1686421781
Short name	T1008
Test name
Test status
Simulation time	1819580400 ps
CPU time	122.82 seconds
Started	Jul 12 07:09:41 PM PDT 24
Finished	Jul 12 07:11:51 PM PDT 24
Peak memory	289948 kb
Host	smart-a4c06080-8e56-4dc4-9cd9-c4ec97e2e3f2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686421781 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_ro.1686421781
Directory	/workspace/2.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_derr.1223097582
Short name	T195
Test name
Test status
Simulation time	3118610400 ps
CPU time	172.31 seconds
Started	Jul 12 07:09:51 PM PDT 24
Finished	Jul 12 07:12:52 PM PDT 24
Peak memory	281820 kb
Host	smart-4cd5c29b-a6a8-4001-8091-b43fbb0d35a3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1223097582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1223097582
Directory	/workspace/2.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_serr.2954689610
Short name	T456
Test name
Test status
Simulation time	9290944800 ps
CPU time	153.96 seconds
Started	Jul 12 07:09:43 PM PDT 24
Finished	Jul 12 07:12:24 PM PDT 24
Peak memory	295064 kb
Host	smart-cd5696d9-cf1b-483c-baca-291295be2b1f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954689610 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.2954689610
Directory	/workspace/2.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw.472388297
Short name	T581
Test name
Test status
Simulation time	18153512400 ps
CPU time	632.1 seconds
Started	Jul 12 07:09:42 PM PDT 24
Finished	Jul 12 07:20:22 PM PDT 24
Peak memory	309412 kb
Host	smart-56a0c4b7-1dcf-44c5-9600-e4cfbda9c740
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472388297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.472388297
Directory	/workspace/2.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_derr.630298478
Short name	T204
Test name
Test status
Simulation time	14107106600 ps
CPU time	567.44 seconds
Started	Jul 12 07:10:03 PM PDT 24
Finished	Jul 12 07:19:37 PM PDT 24
Peak memory	329800 kb
Host	smart-32de4542-c3bd-4646-b603-a58b52a62b4b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630298478 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.flash_ctrl_rw_derr.630298478
Directory	/workspace/2.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict.2684317842
Short name	T400
Test name
Test status
Simulation time	29011700 ps
CPU time	31.36 seconds
Started	Jul 12 07:10:02 PM PDT 24
Finished	Jul 12 07:10:40 PM PDT 24
Peak memory	275848 kb
Host	smart-2553c2f2-8b75-4ec0-b94d-4a87684b7030
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684317842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_rw_evict.2684317842
Directory	/workspace/2.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.3865798536
Short name	T524
Test name
Test status
Simulation time	66335200 ps
CPU time	30.68 seconds
Started	Jul 12 07:10:00 PM PDT 24
Finished	Jul 12 07:10:37 PM PDT 24
Peak memory	273628 kb
Host	smart-813008e4-ff81-43a4-9dbe-752ae85cafe0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865798536 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.3865798536
Directory	/workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_cm.1280689196
Short name	T39
Test name
Test status
Simulation time	7777212200 ps
CPU time	4892.49 seconds
Started	Jul 12 07:09:59 PM PDT 24
Finished	Jul 12 08:31:39 PM PDT 24
Peak memory	289044 kb
Host	smart-17569b27-2b4e-417b-b30c-950ce0385dcb
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280689196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.1280689196
Directory	/workspace/2.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_info_access.3521690629
Short name	T951
Test name
Test status
Simulation time	610524200 ps
CPU time	66.45 seconds
Started	Jul 12 07:10:01 PM PDT 24
Finished	Jul 12 07:11:14 PM PDT 24
Peak memory	263600 kb
Host	smart-0c5ac137-99aa-4978-a7b1-92de1c8169b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521690629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.3521690629
Directory	/workspace/2.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_address.3838856509
Short name	T1075
Test name
Test status
Simulation time	5186326700 ps
CPU time	72.86 seconds
Started	Jul 12 07:09:51 PM PDT 24
Finished	Jul 12 07:11:12 PM PDT 24
Peak memory	265384 kb
Host	smart-f6568469-593a-4337-95be-312f81bb8616
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838856509 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_serr_address.3838856509
Directory	/workspace/2.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke.553857912
Short name	T488
Test name
Test status
Simulation time	239338800 ps
CPU time	121.65 seconds
Started	Jul 12 07:09:23 PM PDT 24
Finished	Jul 12 07:11:34 PM PDT 24
Peak memory	278756 kb
Host	smart-6d9629c2-8f4e-4db2-ba40-6aed06d467fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553857912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.553857912
Directory	/workspace/2.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke_hw.1706977665
Short name	T929
Test name
Test status
Simulation time	52070700 ps
CPU time	26.29 seconds
Started	Jul 12 07:09:24 PM PDT 24
Finished	Jul 12 07:09:59 PM PDT 24
Peak memory	259692 kb
Host	smart-8b1f0f00-5830-482f-b2ee-d1cd190783e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706977665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1706977665
Directory	/workspace/2.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_stress_all.4055772378
Short name	T21
Test name
Test status
Simulation time	210021500 ps
CPU time	166.28 seconds
Started	Jul 12 07:10:04 PM PDT 24
Finished	Jul 12 07:12:59 PM PDT 24
Peak memory	270340 kb
Host	smart-18af9655-0ccb-4814-ac6d-032f55cb34ef
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055772378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres s_all.4055772378
Directory	/workspace/2.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sw_op.4042165538
Short name	T1014
Test name
Test status
Simulation time	26118500 ps
CPU time	27.11 seconds
Started	Jul 12 07:09:27 PM PDT 24
Finished	Jul 12 07:10:01 PM PDT 24
Peak memory	262204 kb
Host	smart-5e0fd8b5-85e1-491b-969d-2c81b3f60413
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042165538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.4042165538
Directory	/workspace/2.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/20.flash_ctrl_alert_test.801755884
Short name	T476
Test name
Test status
Simulation time	21760800 ps
CPU time	13.53 seconds
Started	Jul 12 07:19:33 PM PDT 24
Finished	Jul 12 07:20:04 PM PDT 24
Peak memory	258280 kb
Host	smart-d51063c0-2307-43c0-8aa7-3727cdb8d015
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801755884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.801755884
Directory	/workspace/20.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.flash_ctrl_connect.208095447
Short name	T730
Test name
Test status
Simulation time	23965300 ps
CPU time	13.83 seconds
Started	Jul 12 07:19:36 PM PDT 24
Finished	Jul 12 07:20:09 PM PDT 24
Peak memory	284260 kb
Host	smart-54bc9907-cb0f-4f47-a8e6-8cf79cb14a95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208095447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.208095447
Directory	/workspace/20.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/20.flash_ctrl_disable.2656881468
Short name	T766
Test name
Test status
Simulation time	13374500 ps
CPU time	22.12 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:19:58 PM PDT 24
Peak memory	273536 kb
Host	smart-a541cb2e-d50d-4bf9-8ca0-e006cd175d09
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656881468 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_disable.2656881468
Directory	/workspace/20.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2288994360
Short name	T788
Test name
Test status
Simulation time	789237400 ps
CPU time	41.35 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:20:17 PM PDT 24
Peak memory	262904 kb
Host	smart-01bea470-2c8e-4bef-891e-4665cc736f07
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288994360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ hw_sec_otp.2288994360
Directory	/workspace/20.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.1657867733
Short name	T775
Test name
Test status
Simulation time	12637852300 ps
CPU time	253.7 seconds
Started	Jul 12 07:19:24 PM PDT 24
Finished	Jul 12 07:23:48 PM PDT 24
Peak memory	291500 kb
Host	smart-4ba23ee5-895f-467e-98cd-184241f4907b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657867733 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.1657867733
Directory	/workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/20.flash_ctrl_otp_reset.4140909458
Short name	T444
Test name
Test status
Simulation time	149378100 ps
CPU time	132.06 seconds
Started	Jul 12 07:19:25 PM PDT 24
Finished	Jul 12 07:21:49 PM PDT 24
Peak memory	261080 kb
Host	smart-295f5966-dd3d-418b-a3aa-3b7c039493d4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140909458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o tp_reset.4140909458
Directory	/workspace/20.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_prog_reset.2956476497
Short name	T346
Test name
Test status
Simulation time	65325700 ps
CPU time	13.39 seconds
Started	Jul 12 07:19:25 PM PDT 24
Finished	Jul 12 07:19:50 PM PDT 24
Peak memory	265168 kb
Host	smart-1501d39a-5ac6-4a48-9535-43f6827063df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956476497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.flash_ctrl_prog_reset.2956476497
Directory	/workspace/20.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict.3193824873
Short name	T403
Test name
Test status
Simulation time	301716000 ps
CPU time	28.77 seconds
Started	Jul 12 07:19:26 PM PDT 24
Finished	Jul 12 07:20:08 PM PDT 24
Peak memory	275644 kb
Host	smart-cf22606a-10b7-42ae-b4fa-2e4d42c1a834
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193824873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl ash_ctrl_rw_evict.3193824873
Directory	/workspace/20.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/20.flash_ctrl_sec_info_access.4223597712
Short name	T882
Test name
Test status
Simulation time	4625575500 ps
CPU time	71.42 seconds
Started	Jul 12 07:19:33 PM PDT 24
Finished	Jul 12 07:21:02 PM PDT 24
Peak memory	263560 kb
Host	smart-aad50d70-17c9-4086-b2c8-c744128908ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4223597712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.4223597712
Directory	/workspace/20.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/20.flash_ctrl_smoke.3206295939
Short name	T1074
Test name
Test status
Simulation time	77303500 ps
CPU time	126.14 seconds
Started	Jul 12 07:19:25 PM PDT 24
Finished	Jul 12 07:21:43 PM PDT 24
Peak memory	277552 kb
Host	smart-1568dad0-c6f4-4cc6-bd79-c5f8d37bce05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206295939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.3206295939
Directory	/workspace/20.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.flash_ctrl_alert_test.1890870254
Short name	T597
Test name
Test status
Simulation time	249085000 ps
CPU time	13.5 seconds
Started	Jul 12 07:19:35 PM PDT 24
Finished	Jul 12 07:20:07 PM PDT 24
Peak memory	265248 kb
Host	smart-478f934e-411a-49cc-88f5-588fc0adad7a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890870254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test. 1890870254
Directory	/workspace/21.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.flash_ctrl_connect.1413905504
Short name	T413
Test name
Test status
Simulation time	23608900 ps
CPU time	15.92 seconds
Started	Jul 12 07:19:35 PM PDT 24
Finished	Jul 12 07:20:09 PM PDT 24
Peak memory	284408 kb
Host	smart-44f97c3c-5bc2-4eda-a7ae-5470db5abd89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413905504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.1413905504
Directory	/workspace/21.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/21.flash_ctrl_disable.1138192174
Short name	T89
Test name
Test status
Simulation time	75864500 ps
CPU time	22.2 seconds
Started	Jul 12 07:19:36 PM PDT 24
Finished	Jul 12 07:20:17 PM PDT 24
Peak memory	273628 kb
Host	smart-927489a4-f69d-4ab5-aab5-22faa1cca03d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138192174 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_disable.1138192174
Directory	/workspace/21.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/21.flash_ctrl_hw_sec_otp.3706825016
Short name	T992
Test name
Test status
Simulation time	4747359100 ps
CPU time	171.63 seconds
Started	Jul 12 07:19:34 PM PDT 24
Finished	Jul 12 07:22:43 PM PDT 24
Peak memory	263472 kb
Host	smart-b162b2f5-864c-4e16-9012-66194e4276f1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706825016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ hw_sec_otp.3706825016
Directory	/workspace/21.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd.2757152930
Short name	T315
Test name
Test status
Simulation time	4301592900 ps
CPU time	132.84 seconds
Started	Jul 12 07:19:36 PM PDT 24
Finished	Jul 12 07:22:08 PM PDT 24
Peak memory	291524 kb
Host	smart-4e503ea1-5b2a-4d14-ae1b-a4e8ec8b0e82
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757152930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla sh_ctrl_intr_rd.2757152930
Directory	/workspace/21.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1421968558
Short name	T801
Test name
Test status
Simulation time	48851112700 ps
CPU time	301.31 seconds
Started	Jul 12 07:19:35 PM PDT 24
Finished	Jul 12 07:24:54 PM PDT 24
Peak memory	291032 kb
Host	smart-eccb03a6-3e46-4a70-85f9-8a699aaca27b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421968558 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.1421968558
Directory	/workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/21.flash_ctrl_otp_reset.4227461414
Short name	T655
Test name
Test status
Simulation time	134237000 ps
CPU time	132.15 seconds
Started	Jul 12 07:19:33 PM PDT 24
Finished	Jul 12 07:22:03 PM PDT 24
Peak memory	261152 kb
Host	smart-ab030f4b-fced-4696-9945-a9994749228e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227461414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o tp_reset.4227461414
Directory	/workspace/21.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_prog_reset.4127089589
Short name	T1099
Test name
Test status
Simulation time	8232130400 ps
CPU time	166.41 seconds
Started	Jul 12 07:19:35 PM PDT 24
Finished	Jul 12 07:22:39 PM PDT 24
Peak memory	260552 kb
Host	smart-f34cd661-7468-4b12-8e1f-1636f48ea936
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127089589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.flash_ctrl_prog_reset.4127089589
Directory	/workspace/21.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict.751789601
Short name	T394
Test name
Test status
Simulation time	27563900 ps
CPU time	30.91 seconds
Started	Jul 12 07:19:34 PM PDT 24
Finished	Jul 12 07:20:24 PM PDT 24
Peak memory	273612 kb
Host	smart-487f9444-5f28-4e0e-b236-1b71d25825ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751789601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla sh_ctrl_rw_evict.751789601
Directory	/workspace/21.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.2477585023
Short name	T401
Test name
Test status
Simulation time	84428400 ps
CPU time	31.55 seconds
Started	Jul 12 07:19:33 PM PDT 24
Finished	Jul 12 07:20:23 PM PDT 24
Peak memory	275716 kb
Host	smart-2a522a0f-5cdd-4d09-a07a-179f0f020d09
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477585023 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.2477585023
Directory	/workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/21.flash_ctrl_sec_info_access.662337795
Short name	T745
Test name
Test status
Simulation time	904096900 ps
CPU time	58.64 seconds
Started	Jul 12 07:19:36 PM PDT 24
Finished	Jul 12 07:20:52 PM PDT 24
Peak memory	264088 kb
Host	smart-3f74592d-29b1-4bcf-b26e-4d6523ab5a80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=662337795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.662337795
Directory	/workspace/21.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/21.flash_ctrl_smoke.3559704996
Short name	T636
Test name
Test status
Simulation time	27449400 ps
CPU time	98.5 seconds
Started	Jul 12 07:19:31 PM PDT 24
Finished	Jul 12 07:21:27 PM PDT 24
Peak memory	277200 kb
Host	smart-f3043155-b43e-45b2-b22e-748f960d9ea4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3559704996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.3559704996
Directory	/workspace/21.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.flash_ctrl_alert_test.243008452
Short name	T1039
Test name
Test status
Simulation time	31730400 ps
CPU time	13.72 seconds
Started	Jul 12 07:19:40 PM PDT 24
Finished	Jul 12 07:20:13 PM PDT 24
Peak memory	258268 kb
Host	smart-ecf3ec22-8851-48c8-9414-a70041acdbd3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243008452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.243008452
Directory	/workspace/22.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.flash_ctrl_connect.3781880767
Short name	T842
Test name
Test status
Simulation time	136200600 ps
CPU time	13.19 seconds
Started	Jul 12 07:19:41 PM PDT 24
Finished	Jul 12 07:20:14 PM PDT 24
Peak memory	284240 kb
Host	smart-0dfd5fe8-6cf9-4e0d-9fc5-0d9a584aee9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781880767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3781880767
Directory	/workspace/22.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/22.flash_ctrl_disable.1469113150
Short name	T337
Test name
Test status
Simulation time	10540100 ps
CPU time	21.84 seconds
Started	Jul 12 07:19:34 PM PDT 24
Finished	Jul 12 07:20:14 PM PDT 24
Peak memory	273616 kb
Host	smart-22f66002-aa7c-41de-ad18-a9f2d825949a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469113150 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_disable.1469113150
Directory	/workspace/22.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.3776119929
Short name	T423
Test name
Test status
Simulation time	9268387300 ps
CPU time	197.78 seconds
Started	Jul 12 07:19:36 PM PDT 24
Finished	Jul 12 07:23:13 PM PDT 24
Peak memory	260968 kb
Host	smart-8f691144-5f8f-4e89-9314-24f355404f5f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776119929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ hw_sec_otp.3776119929
Directory	/workspace/22.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1348611603
Short name	T117
Test name
Test status
Simulation time	22419216300 ps
CPU time	128.93 seconds
Started	Jul 12 07:19:36 PM PDT 24
Finished	Jul 12 07:22:04 PM PDT 24
Peak memory	292840 kb
Host	smart-f1a505be-d301-46b2-bd94-76460077bb6e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348611603 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.1348611603
Directory	/workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/22.flash_ctrl_otp_reset.2543093388
Short name	T158
Test name
Test status
Simulation time	37436900 ps
CPU time	131.89 seconds
Started	Jul 12 07:19:36 PM PDT 24
Finished	Jul 12 07:22:07 PM PDT 24
Peak memory	260208 kb
Host	smart-000bb619-dda7-4866-b73b-cafffc62105c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543093388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o tp_reset.2543093388
Directory	/workspace/22.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_prog_reset.1548219208
Short name	T678
Test name
Test status
Simulation time	2760915500 ps
CPU time	158.32 seconds
Started	Jul 12 07:19:35 PM PDT 24
Finished	Jul 12 07:22:32 PM PDT 24
Peak memory	260556 kb
Host	smart-c36ce326-432f-4f92-a310-f2f9ee12c084
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548219208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.flash_ctrl_prog_reset.1548219208
Directory	/workspace/22.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict.3740731471
Short name	T741
Test name
Test status
Simulation time	45035700 ps
CPU time	31.16 seconds
Started	Jul 12 07:19:45 PM PDT 24
Finished	Jul 12 07:20:34 PM PDT 24
Peak memory	268528 kb
Host	smart-f625eb4d-667a-4399-8b2a-9986d8554560
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740731471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl ash_ctrl_rw_evict.3740731471
Directory	/workspace/22.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.633037320
Short name	T946
Test name
Test status
Simulation time	68489900 ps
CPU time	32.61 seconds
Started	Jul 12 07:19:43 PM PDT 24
Finished	Jul 12 07:20:35 PM PDT 24
Peak memory	275696 kb
Host	smart-07c7d5f8-44d1-4eb0-92ae-759407beb0d4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633037320 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.633037320
Directory	/workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/22.flash_ctrl_sec_info_access.4060238996
Short name	T584
Test name
Test status
Simulation time	2822312800 ps
CPU time	67.46 seconds
Started	Jul 12 07:19:40 PM PDT 24
Finished	Jul 12 07:21:07 PM PDT 24
Peak memory	264088 kb
Host	smart-e9717837-cefc-4f19-935b-ad0b5f6839a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4060238996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.4060238996
Directory	/workspace/22.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/22.flash_ctrl_smoke.1264126839
Short name	T782
Test name
Test status
Simulation time	31699700 ps
CPU time	101.35 seconds
Started	Jul 12 07:19:34 PM PDT 24
Finished	Jul 12 07:21:33 PM PDT 24
Peak memory	277564 kb
Host	smart-d2c864ee-1cc5-4436-9c86-4a267c9b04ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264126839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.1264126839
Directory	/workspace/22.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.flash_ctrl_alert_test.857985477
Short name	T433
Test name
Test status
Simulation time	29650800 ps
CPU time	14.07 seconds
Started	Jul 12 07:19:44 PM PDT 24
Finished	Jul 12 07:20:16 PM PDT 24
Peak memory	265220 kb
Host	smart-0cbf6314-16a6-4b43-9fe7-b2808bd26153
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857985477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.857985477
Directory	/workspace/23.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.flash_ctrl_connect.462050308
Short name	T1079
Test name
Test status
Simulation time	26160500 ps
CPU time	15.68 seconds
Started	Jul 12 07:19:42 PM PDT 24
Finished	Jul 12 07:20:16 PM PDT 24
Peak memory	284412 kb
Host	smart-fefaf24b-370d-46d7-aecf-67c552093941
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=462050308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.462050308
Directory	/workspace/23.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/23.flash_ctrl_disable.675729495
Short name	T580
Test name
Test status
Simulation time	10013300 ps
CPU time	21.55 seconds
Started	Jul 12 07:19:44 PM PDT 24
Finished	Jul 12 07:20:24 PM PDT 24
Peak memory	273604 kb
Host	smart-2fe82d57-6df5-4347-86e1-aa18ded6c676
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675729495 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_disable.675729495
Directory	/workspace/23.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/23.flash_ctrl_hw_sec_otp.3164999203
Short name	T896
Test name
Test status
Simulation time	2935185300 ps
CPU time	238.03 seconds
Started	Jul 12 07:19:46 PM PDT 24
Finished	Jul 12 07:24:03 PM PDT 24
Peak memory	262772 kb
Host	smart-c34ecb2b-a0da-47a2-9a0a-1345a0cfb555
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164999203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_ hw_sec_otp.3164999203
Directory	/workspace/23.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd.984289202
Short name	T670
Test name
Test status
Simulation time	2048837000 ps
CPU time	236.87 seconds
Started	Jul 12 07:19:45 PM PDT 24
Finished	Jul 12 07:24:00 PM PDT 24
Peak memory	291536 kb
Host	smart-fae140f8-03a9-4a63-a6f8-c9162158dab0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984289202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flas h_ctrl_intr_rd.984289202
Directory	/workspace/23.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3140594068
Short name	T1073
Test name
Test status
Simulation time	16611355200 ps
CPU time	175.18 seconds
Started	Jul 12 07:19:41 PM PDT 24
Finished	Jul 12 07:22:56 PM PDT 24
Peak memory	294668 kb
Host	smart-c682837f-1df5-4fa1-9d1a-8205bbb7093c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140594068 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.3140594068
Directory	/workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/23.flash_ctrl_prog_reset.3163025548
Short name	T740
Test name
Test status
Simulation time	4627276200 ps
CPU time	195.69 seconds
Started	Jul 12 07:19:42 PM PDT 24
Finished	Jul 12 07:23:17 PM PDT 24
Peak memory	265120 kb
Host	smart-4c26ba1a-aecd-4499-a600-bdaeb95bacab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163025548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.flash_ctrl_prog_reset.3163025548
Directory	/workspace/23.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict.3044812453
Short name	T255
Test name
Test status
Simulation time	28807200 ps
CPU time	31.12 seconds
Started	Jul 12 07:19:40 PM PDT 24
Finished	Jul 12 07:20:30 PM PDT 24
Peak memory	275668 kb
Host	smart-6971c01a-1410-4547-8b18-82e9ccb1fda9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044812453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl ash_ctrl_rw_evict.3044812453
Directory	/workspace/23.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.443669363
Short name	T267
Test name
Test status
Simulation time	199061100 ps
CPU time	30.71 seconds
Started	Jul 12 07:19:40 PM PDT 24
Finished	Jul 12 07:20:30 PM PDT 24
Peak memory	275656 kb
Host	smart-22d06de3-88da-48fb-aa71-31c998a4a8be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443669363 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.443669363
Directory	/workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/23.flash_ctrl_sec_info_access.873927726
Short name	T598
Test name
Test status
Simulation time	13969781700 ps
CPU time	73.97 seconds
Started	Jul 12 07:19:41 PM PDT 24
Finished	Jul 12 07:21:15 PM PDT 24
Peak memory	263140 kb
Host	smart-5d6ede0d-0d65-48dc-aacd-ea0fcfc39c5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=873927726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.873927726
Directory	/workspace/23.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/23.flash_ctrl_smoke.2450506969
Short name	T542
Test name
Test status
Simulation time	86445000 ps
CPU time	96.9 seconds
Started	Jul 12 07:19:40 PM PDT 24
Finished	Jul 12 07:21:36 PM PDT 24
Peak memory	277448 kb
Host	smart-7d2310c1-3ea8-4bd8-8004-0731e6d771f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2450506969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.2450506969
Directory	/workspace/23.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.flash_ctrl_alert_test.2564053629
Short name	T236
Test name
Test status
Simulation time	75718000 ps
CPU time	13.53 seconds
Started	Jul 12 07:19:48 PM PDT 24
Finished	Jul 12 07:20:18 PM PDT 24
Peak memory	265136 kb
Host	smart-48903179-f117-40e0-a02e-fdb3428791bc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564053629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test. 2564053629
Directory	/workspace/24.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.flash_ctrl_connect.891468637
Short name	T486
Test name
Test status
Simulation time	15871600 ps
CPU time	13.63 seconds
Started	Jul 12 07:19:47 PM PDT 24
Finished	Jul 12 07:20:18 PM PDT 24
Peak memory	284268 kb
Host	smart-3532c449-2f75-4233-90ce-9fd3405d3c91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891468637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.891468637
Directory	/workspace/24.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/24.flash_ctrl_disable.4127938922
Short name	T540
Test name
Test status
Simulation time	21328200 ps
CPU time	22.1 seconds
Started	Jul 12 07:19:49 PM PDT 24
Finished	Jul 12 07:20:28 PM PDT 24
Peak memory	273540 kb
Host	smart-8db54f9c-edc8-4c58-9b08-aa2faf1fcaae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127938922 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_disable.4127938922
Directory	/workspace/24.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/24.flash_ctrl_hw_sec_otp.474575626
Short name	T450
Test name
Test status
Simulation time	3585829700 ps
CPU time	237.9 seconds
Started	Jul 12 07:19:45 PM PDT 24
Finished	Jul 12 07:24:01 PM PDT 24
Peak memory	260988 kb
Host	smart-b0d11228-b580-4e25-b75e-e418776cfb8e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474575626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_h w_sec_otp.474575626
Directory	/workspace/24.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd.3119290061
Short name	T835
Test name
Test status
Simulation time	496076100 ps
CPU time	134 seconds
Started	Jul 12 07:19:41 PM PDT 24
Finished	Jul 12 07:22:15 PM PDT 24
Peak memory	294072 kb
Host	smart-d15aa7cd-4d6c-4a81-823c-cc7d8e1f8b38
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119290061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla sh_ctrl_intr_rd.3119290061
Directory	/workspace/24.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.957934034
Short name	T32
Test name
Test status
Simulation time	12427982800 ps
CPU time	301.77 seconds
Started	Jul 12 07:19:48 PM PDT 24
Finished	Jul 12 07:25:06 PM PDT 24
Peak memory	292060 kb
Host	smart-8927f517-4a52-441c-9a22-93651d6605c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957934034 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.957934034
Directory	/workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/24.flash_ctrl_otp_reset.3161141014
Short name	T442
Test name
Test status
Simulation time	71199100 ps
CPU time	129.83 seconds
Started	Jul 12 07:19:42 PM PDT 24
Finished	Jul 12 07:22:11 PM PDT 24
Peak memory	260044 kb
Host	smart-1e8a9a70-2ef4-45d2-80ec-a05e18f054b2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161141014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o tp_reset.3161141014
Directory	/workspace/24.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_prog_reset.1067914605
Short name	T178
Test name
Test status
Simulation time	61594000 ps
CPU time	13.88 seconds
Started	Jul 12 07:19:49 PM PDT 24
Finished	Jul 12 07:20:20 PM PDT 24
Peak memory	259052 kb
Host	smart-24d36bf8-6e1a-46e6-9782-4d331b4a30a7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067914605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.flash_ctrl_prog_reset.1067914605
Directory	/workspace/24.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict.295498499
Short name	T855
Test name
Test status
Simulation time	43148600 ps
CPU time	30.58 seconds
Started	Jul 12 07:19:48 PM PDT 24
Finished	Jul 12 07:20:36 PM PDT 24
Peak memory	273632 kb
Host	smart-9cc6cdd9-acbe-4e67-bcdf-ca7dc26513a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295498499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla sh_ctrl_rw_evict.295498499
Directory	/workspace/24.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.182420975
Short name	T693
Test name
Test status
Simulation time	43411200 ps
CPU time	30.04 seconds
Started	Jul 12 07:19:47 PM PDT 24
Finished	Jul 12 07:20:35 PM PDT 24
Peak memory	275552 kb
Host	smart-070ebf72-3323-468f-86a0-ee227baa5224
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182420975 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.182420975
Directory	/workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/24.flash_ctrl_sec_info_access.3363972157
Short name	T373
Test name
Test status
Simulation time	4490140900 ps
CPU time	82.33 seconds
Started	Jul 12 07:19:49 PM PDT 24
Finished	Jul 12 07:21:29 PM PDT 24
Peak memory	263536 kb
Host	smart-33c4a35c-57ed-4eaa-917a-cb231da49438
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363972157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3363972157
Directory	/workspace/24.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/24.flash_ctrl_smoke.886279204
Short name	T910
Test name
Test status
Simulation time	39488300 ps
CPU time	51.47 seconds
Started	Jul 12 07:19:41 PM PDT 24
Finished	Jul 12 07:20:51 PM PDT 24
Peak memory	271300 kb
Host	smart-1700ac19-9515-457d-8aee-c3b147eabf92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=886279204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.886279204
Directory	/workspace/24.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.flash_ctrl_alert_test.389749515
Short name	T1026
Test name
Test status
Simulation time	73775900 ps
CPU time	13.81 seconds
Started	Jul 12 07:19:58 PM PDT 24
Finished	Jul 12 07:20:29 PM PDT 24
Peak memory	258380 kb
Host	smart-e7cafb4d-a90c-4c20-89cb-95e19e52a0b1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389749515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.389749515
Directory	/workspace/25.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.flash_ctrl_connect.1412761612
Short name	T499
Test name
Test status
Simulation time	20690300 ps
CPU time	15.73 seconds
Started	Jul 12 07:19:56 PM PDT 24
Finished	Jul 12 07:20:28 PM PDT 24
Peak memory	284336 kb
Host	smart-64551753-bf50-4d74-ac22-7509ac6a981b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412761612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1412761612
Directory	/workspace/25.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/25.flash_ctrl_disable.659282722
Short name	T699
Test name
Test status
Simulation time	13117800 ps
CPU time	22.25 seconds
Started	Jul 12 07:19:59 PM PDT 24
Finished	Jul 12 07:20:38 PM PDT 24
Peak memory	273540 kb
Host	smart-d89088b8-7a29-4ca1-bfd5-c7d7c7ea3086
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659282722 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_disable.659282722
Directory	/workspace/25.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/25.flash_ctrl_hw_sec_otp.2512393679
Short name	T1054
Test name
Test status
Simulation time	2600418900 ps
CPU time	100.08 seconds
Started	Jul 12 07:19:58 PM PDT 24
Finished	Jul 12 07:21:55 PM PDT 24
Peak memory	262480 kb
Host	smart-7e0a8c53-e5cd-4342-a375-a25f34f1543d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512393679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ hw_sec_otp.2512393679
Directory	/workspace/25.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd.453169214
Short name	T999
Test name
Test status
Simulation time	495219200 ps
CPU time	114 seconds
Started	Jul 12 07:19:58 PM PDT 24
Finished	Jul 12 07:22:09 PM PDT 24
Peak memory	294768 kb
Host	smart-1c9ca08e-d183-414f-8d21-6e225c9ca60b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453169214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flas h_ctrl_intr_rd.453169214
Directory	/workspace/25.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.300679173
Short name	T819
Test name
Test status
Simulation time	51097365100 ps
CPU time	279.48 seconds
Started	Jul 12 07:19:58 PM PDT 24
Finished	Jul 12 07:24:55 PM PDT 24
Peak memory	292024 kb
Host	smart-81a4dc6c-3011-4209-84fc-36142559178d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300679173 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.300679173
Directory	/workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/25.flash_ctrl_otp_reset.3627898266
Short name	T653
Test name
Test status
Simulation time	36804400 ps
CPU time	112.27 seconds
Started	Jul 12 07:19:56 PM PDT 24
Finished	Jul 12 07:22:05 PM PDT 24
Peak memory	260036 kb
Host	smart-b6425f72-b1f2-480b-bea3-ef907773b3b6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627898266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o tp_reset.3627898266
Directory	/workspace/25.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_prog_reset.2040847581
Short name	T717
Test name
Test status
Simulation time	113369500 ps
CPU time	13.32 seconds
Started	Jul 12 07:19:59 PM PDT 24
Finished	Jul 12 07:20:29 PM PDT 24
Peak memory	259120 kb
Host	smart-c6d891ce-919a-4b6c-b39a-c3cb707e9515
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040847581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.flash_ctrl_prog_reset.2040847581
Directory	/workspace/25.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict.1923772439
Short name	T50
Test name
Test status
Simulation time	76964900 ps
CPU time	31.34 seconds
Started	Jul 12 07:19:57 PM PDT 24
Finished	Jul 12 07:20:47 PM PDT 24
Peak memory	275692 kb
Host	smart-b730f100-8ae8-4b5d-9e33-35c991f45ef0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923772439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl ash_ctrl_rw_evict.1923772439
Directory	/workspace/25.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.1839530446
Short name	T212
Test name
Test status
Simulation time	82355900 ps
CPU time	28.5 seconds
Started	Jul 12 07:19:58 PM PDT 24
Finished	Jul 12 07:20:44 PM PDT 24
Peak memory	268496 kb
Host	smart-096d5f3b-294e-40b8-af12-584976cb8185
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839530446 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.1839530446
Directory	/workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/25.flash_ctrl_sec_info_access.937282255
Short name	T357
Test name
Test status
Simulation time	1224859000 ps
CPU time	69.4 seconds
Started	Jul 12 07:19:58 PM PDT 24
Finished	Jul 12 07:21:25 PM PDT 24
Peak memory	263176 kb
Host	smart-9af6c09f-080f-40da-be19-1e18c1445159
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=937282255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.937282255
Directory	/workspace/25.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/25.flash_ctrl_smoke.3086922882
Short name	T570
Test name
Test status
Simulation time	125117400 ps
CPU time	75.8 seconds
Started	Jul 12 07:19:59 PM PDT 24
Finished	Jul 12 07:21:32 PM PDT 24
Peak memory	275552 kb
Host	smart-7c02a057-04b5-4341-9a41-9116c308ec4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3086922882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3086922882
Directory	/workspace/25.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.flash_ctrl_alert_test.3325797601
Short name	T679
Test name
Test status
Simulation time	30779000 ps
CPU time	13.96 seconds
Started	Jul 12 07:20:06 PM PDT 24
Finished	Jul 12 07:20:35 PM PDT 24
Peak memory	265276 kb
Host	smart-2f682d71-4608-45fe-b311-4f0bb60facaa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325797601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test. 3325797601
Directory	/workspace/26.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.flash_ctrl_connect.3094088799
Short name	T998
Test name
Test status
Simulation time	16638300 ps
CPU time	16.11 seconds
Started	Jul 12 07:20:06 PM PDT 24
Finished	Jul 12 07:20:39 PM PDT 24
Peak memory	274980 kb
Host	smart-ed98e881-8fdf-46e2-bc81-02aa61c86d06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094088799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.3094088799
Directory	/workspace/26.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/26.flash_ctrl_disable.2881517331
Short name	T63
Test name
Test status
Simulation time	10285800 ps
CPU time	21.93 seconds
Started	Jul 12 07:28:38 PM PDT 24
Finished	Jul 12 07:29:08 PM PDT 24
Peak memory	273644 kb
Host	smart-170fa170-08cd-418f-b152-5d4f263141e5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881517331 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_disable.2881517331
Directory	/workspace/26.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/26.flash_ctrl_hw_sec_otp.3883160579
Short name	T1059
Test name
Test status
Simulation time	4424783600 ps
CPU time	75.93 seconds
Started	Jul 12 07:20:09 PM PDT 24
Finished	Jul 12 07:21:40 PM PDT 24
Peak memory	263276 kb
Host	smart-362c7f96-8e65-43a6-826b-046af2f21f91
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883160579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ hw_sec_otp.3883160579
Directory	/workspace/26.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd.3925056791
Short name	T776
Test name
Test status
Simulation time	2016485000 ps
CPU time	126.71 seconds
Started	Jul 12 07:20:07 PM PDT 24
Finished	Jul 12 07:22:29 PM PDT 24
Peak memory	294968 kb
Host	smart-21f785d1-c5e8-4861-a34d-a531f0e5513f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925056791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla sh_ctrl_intr_rd.3925056791
Directory	/workspace/26.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1879346887
Short name	T599
Test name
Test status
Simulation time	79507765000 ps
CPU time	172.1 seconds
Started	Jul 12 07:20:08 PM PDT 24
Finished	Jul 12 07:23:15 PM PDT 24
Peak memory	292832 kb
Host	smart-bc99cbe2-31b0-4a3f-b20a-e0ef4670d3c6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879346887 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1879346887
Directory	/workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/26.flash_ctrl_otp_reset.2120679043
Short name	T742
Test name
Test status
Simulation time	149218700 ps
CPU time	129.98 seconds
Started	Jul 12 07:20:09 PM PDT 24
Finished	Jul 12 07:22:34 PM PDT 24
Peak memory	260068 kb
Host	smart-e7b51d80-926b-490a-b612-8bae210387e7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120679043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o tp_reset.2120679043
Directory	/workspace/26.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_prog_reset.2875590943
Short name	T707
Test name
Test status
Simulation time	35326500 ps
CPU time	13.56 seconds
Started	Jul 12 07:20:09 PM PDT 24
Finished	Jul 12 07:20:37 PM PDT 24
Peak memory	259112 kb
Host	smart-91d6d4db-ba75-4ce0-a4fe-9657da62dcb3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875590943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.flash_ctrl_prog_reset.2875590943
Directory	/workspace/26.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict.721046599
Short name	T388
Test name
Test status
Simulation time	46164300 ps
CPU time	29.06 seconds
Started	Jul 12 07:20:07 PM PDT 24
Finished	Jul 12 07:20:52 PM PDT 24
Peak memory	275768 kb
Host	smart-d8c4cad6-b18b-4bae-8c98-6c3b53f414b1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721046599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla sh_ctrl_rw_evict.721046599
Directory	/workspace/26.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/26.flash_ctrl_sec_info_access.4277974376
Short name	T361
Test name
Test status
Simulation time	1397171200 ps
CPU time	68.13 seconds
Started	Jul 12 07:20:08 PM PDT 24
Finished	Jul 12 07:21:31 PM PDT 24
Peak memory	264160 kb
Host	smart-2226b676-6b9d-4caf-b4cd-77ed4c9da172
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277974376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.4277974376
Directory	/workspace/26.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/26.flash_ctrl_smoke.3169948119
Short name	T473
Test name
Test status
Simulation time	70093200 ps
CPU time	144.86 seconds
Started	Jul 12 07:20:00 PM PDT 24
Finished	Jul 12 07:22:42 PM PDT 24
Peak memory	278068 kb
Host	smart-0f3ec6e7-43e8-495f-a5ba-1dfa5164e24e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3169948119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3169948119
Directory	/workspace/26.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.flash_ctrl_alert_test.2160064706
Short name	T939
Test name
Test status
Simulation time	77943300 ps
CPU time	13.83 seconds
Started	Jul 12 07:20:18 PM PDT 24
Finished	Jul 12 07:20:45 PM PDT 24
Peak memory	258276 kb
Host	smart-66105a36-733f-46a1-acf2-8124bf287d09
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160064706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test. 2160064706
Directory	/workspace/27.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.flash_ctrl_connect.4037278956
Short name	T1016
Test name
Test status
Simulation time	61221600 ps
CPU time	16.24 seconds
Started	Jul 12 07:20:20 PM PDT 24
Finished	Jul 12 07:20:50 PM PDT 24
Peak memory	274836 kb
Host	smart-5e6bf5a2-90ec-415b-8e1b-c5d3ca6e1ef8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037278956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.4037278956
Directory	/workspace/27.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/27.flash_ctrl_disable.81039875
Short name	T88
Test name
Test status
Simulation time	16175300 ps
CPU time	22.73 seconds
Started	Jul 12 07:20:17 PM PDT 24
Finished	Jul 12 07:20:53 PM PDT 24
Peak memory	273572 kb
Host	smart-7b9603cf-ff58-4789-a83c-2bcbe6626bce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81039875 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 27.flash_ctrl_disable.81039875
Directory	/workspace/27.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.2856974115
Short name	T941
Test name
Test status
Simulation time	2887892600 ps
CPU time	63.86 seconds
Started	Jul 12 07:20:07 PM PDT 24
Finished	Jul 12 07:21:27 PM PDT 24
Peak memory	262824 kb
Host	smart-f8b8044b-dc16-420a-8ef0-405bc8245bfd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856974115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ hw_sec_otp.2856974115
Directory	/workspace/27.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd.2271667615
Short name	T837
Test name
Test status
Simulation time	6420131700 ps
CPU time	221.46 seconds
Started	Jul 12 07:20:08 PM PDT 24
Finished	Jul 12 07:24:05 PM PDT 24
Peak memory	284972 kb
Host	smart-cf819a22-60f2-4549-b4da-81004f250b7a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271667615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla sh_ctrl_intr_rd.2271667615
Directory	/workspace/27.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1261982892
Short name	T664
Test name
Test status
Simulation time	11895473300 ps
CPU time	148.62 seconds
Started	Jul 12 07:20:07 PM PDT 24
Finished	Jul 12 07:22:51 PM PDT 24
Peak memory	290920 kb
Host	smart-b52ba355-8925-4be4-b2c7-cafd3cac09fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261982892 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1261982892
Directory	/workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/27.flash_ctrl_otp_reset.1129150189
Short name	T153
Test name
Test status
Simulation time	145401600 ps
CPU time	131.53 seconds
Started	Jul 12 07:20:07 PM PDT 24
Finished	Jul 12 07:22:34 PM PDT 24
Peak memory	260088 kb
Host	smart-d14c2fe4-be12-4ba4-afb5-5a4b7c6135eb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129150189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o tp_reset.1129150189
Directory	/workspace/27.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_prog_reset.1645073873
Short name	T595
Test name
Test status
Simulation time	20978600 ps
CPU time	13.76 seconds
Started	Jul 12 07:20:18 PM PDT 24
Finished	Jul 12 07:20:45 PM PDT 24
Peak memory	265280 kb
Host	smart-f8905f73-c699-4cf2-9181-f058d964495c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645073873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.flash_ctrl_prog_reset.1645073873
Directory	/workspace/27.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict.4181823745
Short name	T645
Test name
Test status
Simulation time	65385500 ps
CPU time	31.89 seconds
Started	Jul 12 07:20:20 PM PDT 24
Finished	Jul 12 07:21:05 PM PDT 24
Peak memory	275688 kb
Host	smart-0328e899-84df-4770-89bc-c178ed442546
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181823745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl ash_ctrl_rw_evict.4181823745
Directory	/workspace/27.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.4036169371
Short name	T719
Test name
Test status
Simulation time	64378300 ps
CPU time	31.33 seconds
Started	Jul 12 07:20:17 PM PDT 24
Finished	Jul 12 07:21:01 PM PDT 24
Peak memory	275672 kb
Host	smart-e9149f1e-80a1-4754-9ba8-255ee56fe4ee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036169371 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.4036169371
Directory	/workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/27.flash_ctrl_sec_info_access.3328629951
Short name	T355
Test name
Test status
Simulation time	2153191100 ps
CPU time	57.3 seconds
Started	Jul 12 07:20:17 PM PDT 24
Finished	Jul 12 07:21:27 PM PDT 24
Peak memory	263828 kb
Host	smart-55ef49be-587b-4265-823b-399b18dfa5b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328629951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.3328629951
Directory	/workspace/27.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/27.flash_ctrl_smoke.287779938
Short name	T1031
Test name
Test status
Simulation time	23712500 ps
CPU time	49.49 seconds
Started	Jul 12 07:20:08 PM PDT 24
Finished	Jul 12 07:21:13 PM PDT 24
Peak memory	271272 kb
Host	smart-4bc4b12f-e9a1-48ed-b169-9109b64ec5fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=287779938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.287779938
Directory	/workspace/27.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.flash_ctrl_alert_test.1233184457
Short name	T714
Test name
Test status
Simulation time	90045600 ps
CPU time	13.87 seconds
Started	Jul 12 07:20:35 PM PDT 24
Finished	Jul 12 07:21:02 PM PDT 24
Peak memory	258200 kb
Host	smart-84c12de8-0c01-4076-a411-1a67725b3585
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233184457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test. 1233184457
Directory	/workspace/28.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.flash_ctrl_connect.3679371382
Short name	T959
Test name
Test status
Simulation time	67508700 ps
CPU time	13.1 seconds
Started	Jul 12 07:20:32 PM PDT 24
Finished	Jul 12 07:20:59 PM PDT 24
Peak memory	284212 kb
Host	smart-c6ea9ef0-7510-4ede-b5fe-847789046a4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679371382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.3679371382
Directory	/workspace/28.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/28.flash_ctrl_disable.4149838613
Short name	T340
Test name
Test status
Simulation time	22565900 ps
CPU time	21.98 seconds
Started	Jul 12 07:20:28 PM PDT 24
Finished	Jul 12 07:21:05 PM PDT 24
Peak memory	273556 kb
Host	smart-8fc376eb-d377-4d4e-9016-f1e2a6cb137f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149838613 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_disable.4149838613
Directory	/workspace/28.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2334927989
Short name	T708
Test name
Test status
Simulation time	2589556800 ps
CPU time	98.56 seconds
Started	Jul 12 07:20:18 PM PDT 24
Finished	Jul 12 07:22:10 PM PDT 24
Peak memory	262140 kb
Host	smart-497523da-540e-4722-a890-2a43ee44a5a1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334927989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ hw_sec_otp.2334927989
Directory	/workspace/28.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd.4013392298
Short name	T715
Test name
Test status
Simulation time	2902803400 ps
CPU time	215.99 seconds
Started	Jul 12 07:20:18 PM PDT 24
Finished	Jul 12 07:24:07 PM PDT 24
Peak memory	291400 kb
Host	smart-d3610b53-516f-452a-ae5b-5cbcc71abf63
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013392298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla sh_ctrl_intr_rd.4013392298
Directory	/workspace/28.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.4157959159
Short name	T665
Test name
Test status
Simulation time	35382233700 ps
CPU time	150.01 seconds
Started	Jul 12 07:20:18 PM PDT 24
Finished	Jul 12 07:23:01 PM PDT 24
Peak memory	292704 kb
Host	smart-7459af2c-cafd-4726-91e4-4815f6bf4059
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157959159 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.4157959159
Directory	/workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/28.flash_ctrl_otp_reset.3341612117
Short name	T994
Test name
Test status
Simulation time	145910000 ps
CPU time	108.93 seconds
Started	Jul 12 07:20:20 PM PDT 24
Finished	Jul 12 07:22:22 PM PDT 24
Peak memory	261160 kb
Host	smart-2e2e30a8-da30-47ae-be8e-6cc8b6bf9343
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341612117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o tp_reset.3341612117
Directory	/workspace/28.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_prog_reset.1094203570
Short name	T813
Test name
Test status
Simulation time	19374300 ps
CPU time	13.92 seconds
Started	Jul 12 07:20:25 PM PDT 24
Finished	Jul 12 07:20:54 PM PDT 24
Peak memory	265264 kb
Host	smart-dc50acb9-f3f9-4e14-9d24-c903c636109e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094203570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.flash_ctrl_prog_reset.1094203570
Directory	/workspace/28.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict.2584378921
Short name	T793
Test name
Test status
Simulation time	82074200 ps
CPU time	31.04 seconds
Started	Jul 12 07:20:35 PM PDT 24
Finished	Jul 12 07:21:19 PM PDT 24
Peak memory	275616 kb
Host	smart-c22292df-41d7-4eba-92fd-0f21eeca86a7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584378921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl ash_ctrl_rw_evict.2584378921
Directory	/workspace/28.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.2824281958
Short name	T263
Test name
Test status
Simulation time	54534000 ps
CPU time	30.33 seconds
Started	Jul 12 07:20:32 PM PDT 24
Finished	Jul 12 07:21:17 PM PDT 24
Peak memory	275656 kb
Host	smart-819fe621-39f1-4e73-ae74-892a4101d1bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824281958 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.2824281958
Directory	/workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/28.flash_ctrl_sec_info_access.2240990441
Short name	T955
Test name
Test status
Simulation time	7920665400 ps
CPU time	75.72 seconds
Started	Jul 12 07:20:27 PM PDT 24
Finished	Jul 12 07:21:57 PM PDT 24
Peak memory	263748 kb
Host	smart-7d286f11-8ade-4d53-9a33-f62e0afd7501
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2240990441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.2240990441
Directory	/workspace/28.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/28.flash_ctrl_smoke.948375936
Short name	T238
Test name
Test status
Simulation time	194251800 ps
CPU time	170.84 seconds
Started	Jul 12 07:20:21 PM PDT 24
Finished	Jul 12 07:23:25 PM PDT 24
Peak memory	277552 kb
Host	smart-feede1cf-6e29-42cc-815b-969ceb4128f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=948375936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.948375936
Directory	/workspace/28.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.flash_ctrl_alert_test.2159728613
Short name	T781
Test name
Test status
Simulation time	62569500 ps
CPU time	13.43 seconds
Started	Jul 12 07:20:35 PM PDT 24
Finished	Jul 12 07:21:03 PM PDT 24
Peak memory	265148 kb
Host	smart-53591ee1-8b51-4dfd-901a-b67d51b2a33d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159728613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test. 2159728613
Directory	/workspace/29.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.flash_ctrl_connect.2215583000
Short name	T904
Test name
Test status
Simulation time	15178800 ps
CPU time	15.98 seconds
Started	Jul 12 07:20:37 PM PDT 24
Finished	Jul 12 07:21:06 PM PDT 24
Peak memory	284264 kb
Host	smart-e9e91e38-0851-4e08-840b-2281c2d8f4a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215583000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.2215583000
Directory	/workspace/29.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/29.flash_ctrl_disable.1435672311
Short name	T683
Test name
Test status
Simulation time	21413800 ps
CPU time	22.47 seconds
Started	Jul 12 07:20:36 PM PDT 24
Finished	Jul 12 07:21:12 PM PDT 24
Peak memory	273692 kb
Host	smart-7f3b7718-742b-413c-8732-bf2eb7289797
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435672311 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_disable.1435672311
Directory	/workspace/29.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.422445961
Short name	T594
Test name
Test status
Simulation time	4290541900 ps
CPU time	70.33 seconds
Started	Jul 12 07:20:35 PM PDT 24
Finished	Jul 12 07:21:59 PM PDT 24
Peak memory	262796 kb
Host	smart-ad7b7ec8-c298-4329-a76c-0e945d93bd6e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422445961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_h w_sec_otp.422445961
Directory	/workspace/29.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd.3686818470
Short name	T509
Test name
Test status
Simulation time	4369464500 ps
CPU time	198.97 seconds
Started	Jul 12 07:20:34 PM PDT 24
Finished	Jul 12 07:24:06 PM PDT 24
Peak memory	292336 kb
Host	smart-8459b370-f852-4594-9682-c8c84b380865
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686818470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla sh_ctrl_intr_rd.3686818470
Directory	/workspace/29.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1735537137
Short name	T937
Test name
Test status
Simulation time	16571499800 ps
CPU time	354.94 seconds
Started	Jul 12 07:20:34 PM PDT 24
Finished	Jul 12 07:26:42 PM PDT 24
Peak memory	293768 kb
Host	smart-a2f5e366-5c24-440d-b924-4eb535f6c655
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735537137 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.1735537137
Directory	/workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/29.flash_ctrl_otp_reset.1677928344
Short name	T163
Test name
Test status
Simulation time	46452900 ps
CPU time	132.68 seconds
Started	Jul 12 07:20:34 PM PDT 24
Finished	Jul 12 07:23:00 PM PDT 24
Peak memory	261116 kb
Host	smart-74517662-e29a-4b9d-a1d4-36b05c246a71
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677928344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o tp_reset.1677928344
Directory	/workspace/29.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_prog_reset.463430774
Short name	T583
Test name
Test status
Simulation time	30594700 ps
CPU time	14.15 seconds
Started	Jul 12 07:20:36 PM PDT 24
Finished	Jul 12 07:21:04 PM PDT 24
Peak memory	265268 kb
Host	smart-a3581477-af4d-4436-9384-c9db1c3797fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463430774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.flash_ctrl_prog_reset.463430774
Directory	/workspace/29.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict.2107035431
Short name	T1019
Test name
Test status
Simulation time	44922000 ps
CPU time	28.71 seconds
Started	Jul 12 07:20:39 PM PDT 24
Finished	Jul 12 07:21:21 PM PDT 24
Peak memory	275668 kb
Host	smart-b8106e73-0ef7-4a0b-b979-4d9d3e268bf4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107035431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl ash_ctrl_rw_evict.2107035431
Directory	/workspace/29.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.1987214025
Short name	T660
Test name
Test status
Simulation time	41138100 ps
CPU time	27.98 seconds
Started	Jul 12 07:20:33 PM PDT 24
Finished	Jul 12 07:21:14 PM PDT 24
Peak memory	268464 kb
Host	smart-94c883ac-de9a-49c5-aced-8b2aeb676881
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987214025 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.1987214025
Directory	/workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/29.flash_ctrl_sec_info_access.1130328916
Short name	T919
Test name
Test status
Simulation time	2176537400 ps
CPU time	78.96 seconds
Started	Jul 12 07:20:37 PM PDT 24
Finished	Jul 12 07:22:09 PM PDT 24
Peak memory	263672 kb
Host	smart-f5c528b1-ef35-42f8-92bc-dcf166ebaf3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130328916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.1130328916
Directory	/workspace/29.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/29.flash_ctrl_smoke.3864568315
Short name	T554
Test name
Test status
Simulation time	120025800 ps
CPU time	173.44 seconds
Started	Jul 12 07:20:27 PM PDT 24
Finished	Jul 12 07:23:35 PM PDT 24
Peak memory	281620 kb
Host	smart-c8eb125f-21dc-4332-9856-ae2321d92913
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864568315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.3864568315
Directory	/workspace/29.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_alert_test.423217578
Short name	T1010
Test name
Test status
Simulation time	87120300 ps
CPU time	14.16 seconds
Started	Jul 12 07:11:53 PM PDT 24
Finished	Jul 12 07:13:13 PM PDT 24
Peak memory	265152 kb
Host	smart-5db83aa0-1229-4c16-a205-b9059110cbdb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423217578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.423217578
Directory	/workspace/3.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.flash_ctrl_config_regwen.3085394802
Short name	T58
Test name
Test status
Simulation time	85101800 ps
CPU time	13.75 seconds
Started	Jul 12 07:11:55 PM PDT 24
Finished	Jul 12 07:13:13 PM PDT 24
Peak memory	261404 kb
Host	smart-1c29cc5c-ad02-43d3-bbcd-7f32cbc94ed8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085394802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .flash_ctrl_config_regwen.3085394802
Directory	/workspace/3.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/3.flash_ctrl_connect.2990912870
Short name	T631
Test name
Test status
Simulation time	22176700 ps
CPU time	15.91 seconds
Started	Jul 12 07:10:59 PM PDT 24
Finished	Jul 12 07:11:26 PM PDT 24
Peak memory	274840 kb
Host	smart-e1465e06-5abf-4bf2-9c34-6ec4eff757ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990912870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2990912870
Directory	/workspace/3.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/3.flash_ctrl_disable.4149716901
Short name	T831
Test name
Test status
Simulation time	17710300 ps
CPU time	21.99 seconds
Started	Jul 12 07:10:59 PM PDT 24
Finished	Jul 12 07:11:32 PM PDT 24
Peak memory	273600 kb
Host	smart-f81e5990-94bc-42d2-852a-78d7b57c51c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149716901 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_disable.4149716901
Directory	/workspace/3.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/3.flash_ctrl_erase_suspend.899144097
Short name	T176
Test name
Test status
Simulation time	13406639100 ps
CPU time	562.07 seconds
Started	Jul 12 07:10:28 PM PDT 24
Finished	Jul 12 07:19:58 PM PDT 24
Peak memory	263504 kb
Host	smart-8d9aace9-de81-46bf-b672-c2e19076e512
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=899144097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.899144097
Directory	/workspace/3.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_mp.3110124422
Short name	T273
Test name
Test status
Simulation time	11742647100 ps
CPU time	2279.03 seconds
Started	Jul 12 07:10:35 PM PDT 24
Finished	Jul 12 07:48:41 PM PDT 24
Peak memory	265256 kb
Host	smart-ec6fd595-5849-4063-b6ca-005d32e7e1b5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3110124422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.3110124422
Directory	/workspace/3.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_type.1959526628
Short name	T857
Test name
Test status
Simulation time	4133164700 ps
CPU time	2451.92 seconds
Started	Jul 12 07:10:29 PM PDT 24
Finished	Jul 12 07:51:29 PM PDT 24
Peak memory	264472 kb
Host	smart-d5d1bfa6-cae5-478c-abb1-f0a388c321cf
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959526628 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.1959526628
Directory	/workspace/3.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_win.1713929341
Short name	T276
Test name
Test status
Simulation time	617461500 ps
CPU time	803.45 seconds
Started	Jul 12 07:10:31 PM PDT 24
Finished	Jul 12 07:24:02 PM PDT 24
Peak memory	271204 kb
Host	smart-5ae228dd-4397-4c76-9b7a-bf0536e4c121
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1713929341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1713929341
Directory	/workspace/3.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fetch_code.991549405
Short name	T49
Test name
Test status
Simulation time	207317400 ps
CPU time	22.59 seconds
Started	Jul 12 07:10:30 PM PDT 24
Finished	Jul 12 07:11:00 PM PDT 24
Peak memory	263652 kb
Host	smart-6e91fe77-53d0-4ad1-a4ad-13c10d2a673d
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991549405 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.991549405
Directory	/workspace/3.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_dir_rd.4069722657
Short name	T258
Test name
Test status
Simulation time	85750000 ps
CPU time	81.77 seconds
Started	Jul 12 07:10:17 PM PDT 24
Finished	Jul 12 07:11:54 PM PDT 24
Peak memory	265252 kb
Host	smart-16a2d4d0-a12e-4580-b7ad-e630c891eee5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4069722657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.4069722657
Directory	/workspace/3.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3033334155
Short name	T812
Test name
Test status
Simulation time	10051508500 ps
CPU time	48.92 seconds
Started	Jul 12 07:11:56 PM PDT 24
Finished	Jul 12 07:13:48 PM PDT 24
Peak memory	278068 kb
Host	smart-492ca7ea-b1c1-4555-95ae-f78753ee4d21
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033334155 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.3033334155
Directory	/workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.2219566669
Short name	T180
Test name
Test status
Simulation time	47172400 ps
CPU time	13.51 seconds
Started	Jul 12 07:11:54 PM PDT 24
Finished	Jul 12 07:13:13 PM PDT 24
Peak memory	264924 kb
Host	smart-5886302d-fa4e-4d96-819d-a58afc6c26d6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219566669 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.2219566669
Directory	/workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_rma_reset.1409376680
Short name	T694
Test name
Test status
Simulation time	160193507200 ps
CPU time	886.31 seconds
Started	Jul 12 07:10:29 PM PDT 24
Finished	Jul 12 07:25:23 PM PDT 24
Peak memory	260996 kb
Host	smart-ebb81686-d8ef-41a5-b602-489372f9aeda
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409376680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 3.flash_ctrl_hw_rma_reset.1409376680
Directory	/workspace/3.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_sec_otp.19595404
Short name	T290
Test name
Test status
Simulation time	3797886000 ps
CPU time	81.22 seconds
Started	Jul 12 07:10:29 PM PDT 24
Finished	Jul 12 07:11:58 PM PDT 24
Peak memory	260660 kb
Host	smart-de843045-d9fc-4c2f-9292-8301e1ae2dec
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19595404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_ sec_otp.19595404
Directory	/workspace/3.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd.2842684625
Short name	T621
Test name
Test status
Simulation time	2245678900 ps
CPU time	145.03 seconds
Started	Jul 12 07:10:43 PM PDT 24
Finished	Jul 12 07:13:14 PM PDT 24
Peak memory	293900 kb
Host	smart-ad6fd8b2-fc68-4046-9327-546acdeda858
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842684625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_intr_rd.2842684625
Directory	/workspace/3.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1266309547
Short name	T1105
Test name
Test status
Simulation time	5903917400 ps
CPU time	129.53 seconds
Started	Jul 12 07:10:42 PM PDT 24
Finished	Jul 12 07:12:58 PM PDT 24
Peak memory	293132 kb
Host	smart-d93fc7bb-d4df-4094-9fae-23b987e2e073
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266309547 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.1266309547
Directory	/workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr.1209253341
Short name	T424
Test name
Test status
Simulation time	9391109700 ps
CPU time	69.57 seconds
Started	Jul 12 07:10:45 PM PDT 24
Finished	Jul 12 07:11:59 PM PDT 24
Peak memory	260700 kb
Host	smart-5bf14af3-d2a5-47f0-93e1-c7723545ebaf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209253341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.flash_ctrl_intr_wr.1209253341
Directory	/workspace/3.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.2948648824
Short name	T481
Test name
Test status
Simulation time	86993511000 ps
CPU time	184.69 seconds
Started	Jul 12 07:10:49 PM PDT 24
Finished	Jul 12 07:13:57 PM PDT 24
Peak memory	260824 kb
Host	smart-7ccd793a-73d2-48a0-a4c6-5b0600d55f02
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294 8648824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.2948648824
Directory	/workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_lcmgr_intg.1516238815
Short name	T834
Test name
Test status
Simulation time	15241400 ps
CPU time	13.48 seconds
Started	Jul 12 07:11:56 PM PDT 24
Finished	Jul 12 07:13:14 PM PDT 24
Peak memory	265000 kb
Host	smart-9c4c79bd-8704-4547-8620-281642a9db52
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516238815 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.1516238815
Directory	/workspace/3.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mid_op_rst.432213845
Short name	T82
Test name
Test status
Simulation time	989497000 ps
CPU time	70.9 seconds
Started	Jul 12 07:10:36 PM PDT 24
Finished	Jul 12 07:11:53 PM PDT 24
Peak memory	260764 kb
Host	smart-bec583ad-4f69-44f9-b901-056ea3557efa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=432213845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.432213845
Directory	/workspace/3.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mp_regions.3452850767
Short name	T139
Test name
Test status
Simulation time	24487383500 ps
CPU time	287.22 seconds
Started	Jul 12 07:10:30 PM PDT 24
Finished	Jul 12 07:15:24 PM PDT 24
Peak memory	274220 kb
Host	smart-6fee95d2-6919-46e6-a7b4-fb4cfb1b92c3
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452850767 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.3452850767
Directory	/workspace/3.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/3.flash_ctrl_oversize_error.216829042
Short name	T744
Test name
Test status
Simulation time	1276584900 ps
CPU time	196.16 seconds
Started	Jul 12 07:10:43 PM PDT 24
Finished	Jul 12 07:14:05 PM PDT 24
Peak memory	281796 kb
Host	smart-f5b277a5-f21f-42a7-8dc1-d338eead0378
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216829042 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.216829042
Directory	/workspace/3.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.3331654682
Short name	T61
Test name
Test status
Simulation time	16309500 ps
CPU time	13.95 seconds
Started	Jul 12 07:11:55 PM PDT 24
Finished	Jul 12 07:13:13 PM PDT 24
Peak memory	277080 kb
Host	smart-454bbb82-5eed-450e-b7bf-f46272af3fec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3331654682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.3331654682
Directory	/workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb.4205822872
Short name	T624
Test name
Test status
Simulation time	3681270300 ps
CPU time	298.14 seconds
Started	Jul 12 07:10:18 PM PDT 24
Finished	Jul 12 07:15:30 PM PDT 24
Peak memory	263172 kb
Host	smart-d7837aa9-b96f-4c59-8a5a-1c445303d2a8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4205822872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.4205822872
Directory	/workspace/3.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.2077389210
Short name	T832
Test name
Test status
Simulation time	17372900 ps
CPU time	14.08 seconds
Started	Jul 12 07:11:52 PM PDT 24
Finished	Jul 12 07:13:13 PM PDT 24
Peak memory	262496 kb
Host	smart-5fb8a954-9ea4-4adc-814a-3f74a464fb3c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077389210 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.2077389210
Directory	/workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_prog_reset.4041456289
Short name	T853
Test name
Test status
Simulation time	28340589700 ps
CPU time	194.11 seconds
Started	Jul 12 07:10:52 PM PDT 24
Finished	Jul 12 07:14:08 PM PDT 24
Peak memory	260552 kb
Host	smart-f91f7ea0-90e3-4b25-81dc-df4235b792b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041456289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.flash_ctrl_prog_reset.4041456289
Directory	/workspace/3.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rand_ops.604170039
Short name	T144
Test name
Test status
Simulation time	1583327200 ps
CPU time	789.64 seconds
Started	Jul 12 07:10:21 PM PDT 24
Finished	Jul 12 07:23:43 PM PDT 24
Peak memory	283712 kb
Host	smart-0767090b-dedd-4856-b7fd-889f79eb4dfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604170039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.604170039
Directory	/workspace/3.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rd_buff_evict.2269515034
Short name	T839
Test name
Test status
Simulation time	143216400 ps
CPU time	104.1 seconds
Started	Jul 12 07:10:21 PM PDT 24
Finished	Jul 12 07:12:18 PM PDT 24
Peak memory	262904 kb
Host	smart-fce0c0fe-b2a2-403a-90c9-09b3f8b39463
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2269515034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.2269515034
Directory	/workspace/3.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_re_evict.1526749598
Short name	T658
Test name
Test status
Simulation time	1043439500 ps
CPU time	35.12 seconds
Started	Jul 12 07:10:52 PM PDT 24
Finished	Jul 12 07:11:29 PM PDT 24
Peak memory	275628 kb
Host	smart-a511690c-0095-48de-88b7-a06f94e96e81
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526749598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_re_evict.1526749598
Directory	/workspace/3.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.3273409431
Short name	T705
Test name
Test status
Simulation time	78952600 ps
CPU time	23.03 seconds
Started	Jul 12 07:10:43 PM PDT 24
Finished	Jul 12 07:11:12 PM PDT 24
Peak memory	265384 kb
Host	smart-f6837c4c-bf3f-4326-b795-92c8c9bc105c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273409431 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.3273409431
Directory	/workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.1677936979
Short name	T824
Test name
Test status
Simulation time	29128400 ps
CPU time	23.16 seconds
Started	Jul 12 07:10:35 PM PDT 24
Finished	Jul 12 07:11:05 PM PDT 24
Peak memory	265080 kb
Host	smart-ea55a198-c485-4467-bb52-c22502b0fe7e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677936979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl ash_ctrl_read_word_sweep_serr.1677936979
Directory	/workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro.723314190
Short name	T879
Test name
Test status
Simulation time	1814860900 ps
CPU time	127.69 seconds
Started	Jul 12 07:10:35 PM PDT 24
Finished	Jul 12 07:12:50 PM PDT 24
Peak memory	291380 kb
Host	smart-2a7afc0d-5223-49a5-ae2c-a1476a800290
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723314190 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.flash_ctrl_ro.723314190
Directory	/workspace/3.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_derr.1696164239
Short name	T172
Test name
Test status
Simulation time	8298911200 ps
CPU time	165.54 seconds
Started	Jul 12 07:10:44 PM PDT 24
Finished	Jul 12 07:13:34 PM PDT 24
Peak memory	282820 kb
Host	smart-249ee280-30c7-42c1-905d-f10293cebbe1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1696164239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.1696164239
Directory	/workspace/3.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_serr.2093047049
Short name	T889
Test name
Test status
Simulation time	665480400 ps
CPU time	145.31 seconds
Started	Jul 12 07:11:15 PM PDT 24
Finished	Jul 12 07:14:36 PM PDT 24
Peak memory	290504 kb
Host	smart-ba3877b8-2f8b-4524-a2f1-c130fb4d9a2a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093047049 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.2093047049
Directory	/workspace/3.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw.2913058151
Short name	T847
Test name
Test status
Simulation time	58202178300 ps
CPU time	612.49 seconds
Started	Jul 12 07:10:36 PM PDT 24
Finished	Jul 12 07:20:55 PM PDT 24
Peak memory	314312 kb
Host	smart-4dec89b2-808a-4a73-81df-311357340503
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913058151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.flash_ctrl_rw.2913058151
Directory	/workspace/3.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.2139132626
Short name	T265
Test name
Test status
Simulation time	86208800 ps
CPU time	27.98 seconds
Started	Jul 12 07:10:49 PM PDT 24
Finished	Jul 12 07:11:20 PM PDT 24
Peak memory	268500 kb
Host	smart-865e1831-5156-4f5d-8a67-0c505e20ec2a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139132626 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.2139132626
Directory	/workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_serr.3555556431
Short name	T686
Test name
Test status
Simulation time	35045089400 ps
CPU time	624.65 seconds
Started	Jul 12 07:10:38 PM PDT 24
Finished	Jul 12 07:21:09 PM PDT 24
Peak memory	320904 kb
Host	smart-1ae8e491-d764-4a40-9309-ea99bc655986
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555556431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s err.3555556431
Directory	/workspace/3.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_cm.965957727
Short name	T40
Test name
Test status
Simulation time	3045308300 ps
CPU time	4824.6 seconds
Started	Jul 12 07:10:57 PM PDT 24
Finished	Jul 12 08:31:30 PM PDT 24
Peak memory	287020 kb
Host	smart-ab47cc2d-f831-4b32-8e01-ec1065a82066
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965957727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.965957727
Directory	/workspace/3.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_info_access.3864839475
Short name	T186
Test name
Test status
Simulation time	5473846500 ps
CPU time	71.12 seconds
Started	Jul 12 07:10:58 PM PDT 24
Finished	Jul 12 07:12:19 PM PDT 24
Peak memory	263724 kb
Host	smart-9640b227-4ec3-4b35-804b-8e06b9a3a9e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864839475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.3864839475
Directory	/workspace/3.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_address.1547253763
Short name	T674
Test name
Test status
Simulation time	920929200 ps
CPU time	105.04 seconds
Started	Jul 12 07:10:35 PM PDT 24
Finished	Jul 12 07:12:27 PM PDT 24
Peak memory	273576 kb
Host	smart-b30e30ec-c1ef-4279-98a3-1a864c5a0cd2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547253763 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_serr_address.1547253763
Directory	/workspace/3.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_counter.1556214461
Short name	T881
Test name
Test status
Simulation time	3494884500 ps
CPU time	77.34 seconds
Started	Jul 12 07:10:36 PM PDT 24
Finished	Jul 12 07:11:59 PM PDT 24
Peak memory	265604 kb
Host	smart-cb5ae6c4-2f0e-4140-b95d-6dd8ef8f8ced
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556214461 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_serr_counter.1556214461
Directory	/workspace/3.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke.1087973825
Short name	T753
Test name
Test status
Simulation time	20468100 ps
CPU time	51.65 seconds
Started	Jul 12 07:10:21 PM PDT 24
Finished	Jul 12 07:11:25 PM PDT 24
Peak memory	271388 kb
Host	smart-82fa0438-a36b-4c15-9716-bff6a6305c76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087973825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1087973825
Directory	/workspace/3.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke_hw.1273763365
Short name	T520
Test name
Test status
Simulation time	92669800 ps
CPU time	23.82 seconds
Started	Jul 12 07:10:20 PM PDT 24
Finished	Jul 12 07:10:57 PM PDT 24
Peak memory	259648 kb
Host	smart-d9120f69-163f-4bad-a750-d968a02aa78b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1273763365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1273763365
Directory	/workspace/3.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_stress_all.2427767304
Short name	T912
Test name
Test status
Simulation time	46452600 ps
CPU time	156.11 seconds
Started	Jul 12 07:10:57 PM PDT 24
Finished	Jul 12 07:13:41 PM PDT 24
Peak memory	278732 kb
Host	smart-aa226f00-1a53-430c-b2be-330b2b1975e2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427767304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres s_all.2427767304
Directory	/workspace/3.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sw_op.3454114088
Short name	T382
Test name
Test status
Simulation time	29443700 ps
CPU time	24.17 seconds
Started	Jul 12 07:10:19 PM PDT 24
Finished	Jul 12 07:10:57 PM PDT 24
Peak memory	262184 kb
Host	smart-272427bf-5fbe-4ee0-ad84-7960357e7838
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3454114088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3454114088
Directory	/workspace/3.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_wo.3130134076
Short name	T502
Test name
Test status
Simulation time	14855287800 ps
CPU time	171.45 seconds
Started	Jul 12 07:10:39 PM PDT 24
Finished	Jul 12 07:13:36 PM PDT 24
Peak memory	260084 kb
Host	smart-6a09d3e1-c3ab-4661-a2f9-327fc0d80871
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130134076 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.flash_ctrl_wo.3130134076
Directory	/workspace/3.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/30.flash_ctrl_alert_test.3647628233
Short name	T18
Test name
Test status
Simulation time	57602500 ps
CPU time	13.86 seconds
Started	Jul 12 07:20:44 PM PDT 24
Finished	Jul 12 07:21:08 PM PDT 24
Peak memory	259212 kb
Host	smart-81f29e6f-2b79-452f-8561-7b98ce3bb123
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647628233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test. 3647628233
Directory	/workspace/30.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.flash_ctrl_connect.2658576650
Short name	T615
Test name
Test status
Simulation time	23251500 ps
CPU time	13.3 seconds
Started	Jul 12 07:20:43 PM PDT 24
Finished	Jul 12 07:21:07 PM PDT 24
Peak memory	274876 kb
Host	smart-ac476f2d-1f7b-4727-8730-6984c3f172ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658576650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2658576650
Directory	/workspace/30.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/30.flash_ctrl_disable.498399960
Short name	T764
Test name
Test status
Simulation time	16586600 ps
CPU time	22.25 seconds
Started	Jul 12 07:20:42 PM PDT 24
Finished	Jul 12 07:21:16 PM PDT 24
Peak memory	265628 kb
Host	smart-fe2f0ce8-14c9-448b-be76-ea925bd244a4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498399960 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_disable.498399960
Directory	/workspace/30.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/30.flash_ctrl_hw_sec_otp.222455003
Short name	T301
Test name
Test status
Simulation time	5926897100 ps
CPU time	110.01 seconds
Started	Jul 12 07:20:34 PM PDT 24
Finished	Jul 12 07:22:38 PM PDT 24
Peak memory	260952 kb
Host	smart-88c3c42c-5a39-4aae-bf58-8951462a71e9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222455003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_h w_sec_otp.222455003
Directory	/workspace/30.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd.582494929
Short name	T535
Test name
Test status
Simulation time	847281400 ps
CPU time	136.74 seconds
Started	Jul 12 07:20:44 PM PDT 24
Finished	Jul 12 07:23:12 PM PDT 24
Peak memory	291488 kb
Host	smart-d85604b1-03f0-45a8-8e6b-0fc31b6ca4a4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582494929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flas h_ctrl_intr_rd.582494929
Directory	/workspace/30.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.2740843576
Short name	T650
Test name
Test status
Simulation time	24167967400 ps
CPU time	333.41 seconds
Started	Jul 12 07:20:44 PM PDT 24
Finished	Jul 12 07:26:28 PM PDT 24
Peak memory	284972 kb
Host	smart-8588bb5d-108b-4d94-bb4d-540034145a31
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740843576 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.2740843576
Directory	/workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/30.flash_ctrl_otp_reset.3589045861
Short name	T154
Test name
Test status
Simulation time	37794300 ps
CPU time	112.08 seconds
Started	Jul 12 07:20:34 PM PDT 24
Finished	Jul 12 07:22:40 PM PDT 24
Peak memory	262296 kb
Host	smart-d6e711aa-8d7c-4dc3-b3d3-47088a37d643
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589045861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o tp_reset.3589045861
Directory	/workspace/30.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict.313343420
Short name	T111
Test name
Test status
Simulation time	49345400 ps
CPU time	31.75 seconds
Started	Jul 12 07:20:44 PM PDT 24
Finished	Jul 12 07:21:26 PM PDT 24
Peak memory	275652 kb
Host	smart-a5bacb55-7e04-4177-b447-9c834b764dc8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313343420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla sh_ctrl_rw_evict.313343420
Directory	/workspace/30.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.1087991480
Short name	T1055
Test name
Test status
Simulation time	43969300 ps
CPU time	31.64 seconds
Started	Jul 12 07:20:47 PM PDT 24
Finished	Jul 12 07:21:29 PM PDT 24
Peak memory	268444 kb
Host	smart-2e4fa9b9-c843-45bc-bf29-b8483ac3747e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087991480 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.1087991480
Directory	/workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/30.flash_ctrl_sec_info_access.562227846
Short name	T960
Test name
Test status
Simulation time	2638385900 ps
CPU time	77.75 seconds
Started	Jul 12 07:20:43 PM PDT 24
Finished	Jul 12 07:22:12 PM PDT 24
Peak memory	264996 kb
Host	smart-b5889dc0-52cd-498d-b189-2bb81099037f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562227846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.562227846
Directory	/workspace/30.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/30.flash_ctrl_smoke.2699013533
Short name	T747
Test name
Test status
Simulation time	37944200 ps
CPU time	169.74 seconds
Started	Jul 12 07:20:33 PM PDT 24
Finished	Jul 12 07:23:37 PM PDT 24
Peak memory	277444 kb
Host	smart-41284b85-4a98-4dd8-bdf2-7e9aefca939f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2699013533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.2699013533
Directory	/workspace/30.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.flash_ctrl_alert_test.1024097917
Short name	T733
Test name
Test status
Simulation time	29670200 ps
CPU time	13.57 seconds
Started	Jul 12 07:20:54 PM PDT 24
Finished	Jul 12 07:21:19 PM PDT 24
Peak memory	258408 kb
Host	smart-201506f0-79ba-4c75-8125-248f88d231cd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024097917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test. 1024097917
Directory	/workspace/31.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.flash_ctrl_connect.2696060255
Short name	T890
Test name
Test status
Simulation time	13908100 ps
CPU time	13.48 seconds
Started	Jul 12 07:20:55 PM PDT 24
Finished	Jul 12 07:21:20 PM PDT 24
Peak memory	274876 kb
Host	smart-a2794fa2-33d7-4e7a-bf24-e9cd0183fad9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2696060255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.2696060255
Directory	/workspace/31.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/31.flash_ctrl_disable.2937394600
Short name	T1027
Test name
Test status
Simulation time	34955400 ps
CPU time	20.62 seconds
Started	Jul 12 07:20:55 PM PDT 24
Finished	Jul 12 07:21:27 PM PDT 24
Peak memory	273572 kb
Host	smart-761b7ddf-4395-4ae3-a948-4e0770a01779
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937394600 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_disable.2937394600
Directory	/workspace/31.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3748567883
Short name	T431
Test name
Test status
Simulation time	3038002000 ps
CPU time	64.14 seconds
Started	Jul 12 07:20:57 PM PDT 24
Finished	Jul 12 07:22:14 PM PDT 24
Peak memory	262788 kb
Host	smart-7ad55011-1698-4114-89ef-08d75d5dd055
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748567883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_ hw_sec_otp.3748567883
Directory	/workspace/31.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd.308352302
Short name	T1034
Test name
Test status
Simulation time	1384052200 ps
CPU time	142.17 seconds
Started	Jul 12 07:20:54 PM PDT 24
Finished	Jul 12 07:23:28 PM PDT 24
Peak memory	291540 kb
Host	smart-d1747451-c956-4dca-89ed-4961ce9f3554
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308352302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flas h_ctrl_intr_rd.308352302
Directory	/workspace/31.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3470070546
Short name	T620
Test name
Test status
Simulation time	11320668600 ps
CPU time	177.29 seconds
Started	Jul 12 07:20:53 PM PDT 24
Finished	Jul 12 07:24:02 PM PDT 24
Peak memory	293008 kb
Host	smart-79f79d7c-8917-4c2e-a1c7-ca058c9f1ffb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470070546 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.3470070546
Directory	/workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict.408702304
Short name	T390
Test name
Test status
Simulation time	72655700 ps
CPU time	33.21 seconds
Started	Jul 12 07:20:53 PM PDT 24
Finished	Jul 12 07:21:38 PM PDT 24
Peak memory	275888 kb
Host	smart-e2331be7-678c-4ec0-af13-4c0c6b811e3c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408702304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla sh_ctrl_rw_evict.408702304
Directory	/workspace/31.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.4039750044
Short name	T932
Test name
Test status
Simulation time	72308800 ps
CPU time	31.17 seconds
Started	Jul 12 07:20:54 PM PDT 24
Finished	Jul 12 07:21:37 PM PDT 24
Peak memory	268508 kb
Host	smart-95f9bf15-e9a7-4ebe-9ebe-144b3e2de2a3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039750044 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.4039750044
Directory	/workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/31.flash_ctrl_sec_info_access.3762973295
Short name	T372
Test name
Test status
Simulation time	3374337900 ps
CPU time	71.51 seconds
Started	Jul 12 07:20:52 PM PDT 24
Finished	Jul 12 07:22:15 PM PDT 24
Peak memory	263596 kb
Host	smart-e0c1976e-3c70-4be6-82a0-3601ee131688
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3762973295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3762973295
Directory	/workspace/31.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/31.flash_ctrl_smoke.3094060841
Short name	T17
Test name
Test status
Simulation time	220347100 ps
CPU time	99.09 seconds
Started	Jul 12 07:20:44 PM PDT 24
Finished	Jul 12 07:22:33 PM PDT 24
Peak memory	276396 kb
Host	smart-c3084a03-65ee-4db8-b964-fcdc1e01c4fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094060841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.3094060841
Directory	/workspace/31.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.flash_ctrl_alert_test.304020650
Short name	T876
Test name
Test status
Simulation time	73183800 ps
CPU time	13.88 seconds
Started	Jul 12 07:20:56 PM PDT 24
Finished	Jul 12 07:21:22 PM PDT 24
Peak memory	258280 kb
Host	smart-a6d37b20-4989-47fa-951d-80bc54b127fe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304020650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.304020650
Directory	/workspace/32.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.flash_ctrl_connect.2025637335
Short name	T738
Test name
Test status
Simulation time	15876100 ps
CPU time	16.77 seconds
Started	Jul 12 07:20:54 PM PDT 24
Finished	Jul 12 07:21:23 PM PDT 24
Peak memory	284344 kb
Host	smart-25f7752a-3fe7-408b-b806-73426f90b08a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025637335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2025637335
Directory	/workspace/32.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/32.flash_ctrl_hw_sec_otp.1840374552
Short name	T978
Test name
Test status
Simulation time	1285979300 ps
CPU time	126.57 seconds
Started	Jul 12 07:20:54 PM PDT 24
Finished	Jul 12 07:23:13 PM PDT 24
Peak memory	260896 kb
Host	smart-26650883-5873-4366-a405-591c1bde2dde
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840374552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ hw_sec_otp.1840374552
Directory	/workspace/32.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd.1416913345
Short name	T60
Test name
Test status
Simulation time	1824167800 ps
CPU time	209.08 seconds
Started	Jul 12 07:20:53 PM PDT 24
Finished	Jul 12 07:24:33 PM PDT 24
Peak memory	292488 kb
Host	smart-2901740f-87d7-4bd3-9c41-9b3a13b61374
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416913345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla sh_ctrl_intr_rd.1416913345
Directory	/workspace/32.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2280319314
Short name	T57
Test name
Test status
Simulation time	11721710300 ps
CPU time	130.26 seconds
Started	Jul 12 07:20:56 PM PDT 24
Finished	Jul 12 07:23:19 PM PDT 24
Peak memory	293120 kb
Host	smart-3e284a64-8937-49a3-b1ea-31b1edfa1630
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280319314 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.2280319314
Directory	/workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/32.flash_ctrl_otp_reset.3769725303
Short name	T291
Test name
Test status
Simulation time	40175100 ps
CPU time	132.67 seconds
Started	Jul 12 07:20:56 PM PDT 24
Finished	Jul 12 07:23:22 PM PDT 24
Peak memory	260076 kb
Host	smart-23504c0b-d5ac-4dcc-bccf-613333abd8d6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769725303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o tp_reset.3769725303
Directory	/workspace/32.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict.1295191011
Short name	T393
Test name
Test status
Simulation time	76710100 ps
CPU time	31.56 seconds
Started	Jul 12 07:20:55 PM PDT 24
Finished	Jul 12 07:21:39 PM PDT 24
Peak memory	275632 kb
Host	smart-56987051-675d-4519-82e4-cb13cb3d9c7c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295191011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl ash_ctrl_rw_evict.1295191011
Directory	/workspace/32.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.1309604112
Short name	T639
Test name
Test status
Simulation time	54518300 ps
CPU time	31.68 seconds
Started	Jul 12 07:20:54 PM PDT 24
Finished	Jul 12 07:21:38 PM PDT 24
Peak memory	268544 kb
Host	smart-ef3a358e-00ac-4c84-b24a-c58797cd2c5c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309604112 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.1309604112
Directory	/workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/32.flash_ctrl_sec_info_access.3345423150
Short name	T963
Test name
Test status
Simulation time	3187708400 ps
CPU time	70.08 seconds
Started	Jul 12 07:20:56 PM PDT 24
Finished	Jul 12 07:22:18 PM PDT 24
Peak memory	263680 kb
Host	smart-5118dbcb-92ad-4b08-9812-b85fb5ec3d0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3345423150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3345423150
Directory	/workspace/32.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/32.flash_ctrl_smoke.1174744467
Short name	T480
Test name
Test status
Simulation time	19295300 ps
CPU time	122.9 seconds
Started	Jul 12 07:20:55 PM PDT 24
Finished	Jul 12 07:23:10 PM PDT 24
Peak memory	277332 kb
Host	smart-97fda148-e2f9-40b6-992c-055a5329a9b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174744467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.1174744467
Directory	/workspace/32.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.flash_ctrl_alert_test.1186905469
Short name	T589
Test name
Test status
Simulation time	109322200 ps
CPU time	14.05 seconds
Started	Jul 12 07:21:10 PM PDT 24
Finished	Jul 12 07:21:39 PM PDT 24
Peak memory	265168 kb
Host	smart-bd68a4d3-8864-49f8-a1e8-170b16ca8cba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186905469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test. 1186905469
Directory	/workspace/33.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.flash_ctrl_connect.1811001351
Short name	T864
Test name
Test status
Simulation time	55110700 ps
CPU time	16.06 seconds
Started	Jul 12 07:21:07 PM PDT 24
Finished	Jul 12 07:21:37 PM PDT 24
Peak memory	274984 kb
Host	smart-a3c65e25-3842-4ae9-94da-3a905de3b42b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811001351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.1811001351
Directory	/workspace/33.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.3267204198
Short name	T90
Test name
Test status
Simulation time	20706165400 ps
CPU time	141.4 seconds
Started	Jul 12 07:21:17 PM PDT 24
Finished	Jul 12 07:23:52 PM PDT 24
Peak memory	262712 kb
Host	smart-c145843f-e4b8-401a-8f13-9fa080dc72cb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267204198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ hw_sec_otp.3267204198
Directory	/workspace/33.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd.4233327697
Short name	T784
Test name
Test status
Simulation time	786915600 ps
CPU time	150.88 seconds
Started	Jul 12 07:21:07 PM PDT 24
Finished	Jul 12 07:23:51 PM PDT 24
Peak memory	284960 kb
Host	smart-b53b37e6-48af-4a13-a66b-fecf35c5effc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233327697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla sh_ctrl_intr_rd.4233327697
Directory	/workspace/33.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/33.flash_ctrl_otp_reset.2381457950
Short name	T684
Test name
Test status
Simulation time	159310200 ps
CPU time	132.33 seconds
Started	Jul 12 07:21:11 PM PDT 24
Finished	Jul 12 07:23:38 PM PDT 24
Peak memory	264988 kb
Host	smart-3480a656-e3ce-458e-9d2a-4eb72b3ce945
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381457950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o tp_reset.2381457950
Directory	/workspace/33.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict.1668281280
Short name	T1063
Test name
Test status
Simulation time	26744900 ps
CPU time	31.66 seconds
Started	Jul 12 07:21:07 PM PDT 24
Finished	Jul 12 07:21:52 PM PDT 24
Peak memory	268492 kb
Host	smart-c6782494-893a-4c6b-97cd-3a33910d7a7a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668281280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl ash_ctrl_rw_evict.1668281280
Directory	/workspace/33.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.2171898379
Short name	T962
Test name
Test status
Simulation time	42174900 ps
CPU time	27.73 seconds
Started	Jul 12 07:21:09 PM PDT 24
Finished	Jul 12 07:21:50 PM PDT 24
Peak memory	275716 kb
Host	smart-c6a8604b-c2be-4bb6-ba11-fea7252d5e85
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171898379 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.2171898379
Directory	/workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/33.flash_ctrl_smoke.1471827440
Short name	T816
Test name
Test status
Simulation time	160606900 ps
CPU time	215.01 seconds
Started	Jul 12 07:21:11 PM PDT 24
Finished	Jul 12 07:25:00 PM PDT 24
Peak memory	279424 kb
Host	smart-9851ac8e-6ff4-40cc-8e02-429712a18c52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1471827440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.1471827440
Directory	/workspace/33.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.flash_ctrl_alert_test.430187379
Short name	T452
Test name
Test status
Simulation time	32918200 ps
CPU time	13.83 seconds
Started	Jul 12 07:21:16 PM PDT 24
Finished	Jul 12 07:21:44 PM PDT 24
Peak memory	265272 kb
Host	smart-0b385b1b-552e-4ab2-bca5-d6b3cf338032
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430187379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.430187379
Directory	/workspace/34.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.flash_ctrl_connect.1314227534
Short name	T492
Test name
Test status
Simulation time	14115700 ps
CPU time	13.66 seconds
Started	Jul 12 07:21:09 PM PDT 24
Finished	Jul 12 07:21:38 PM PDT 24
Peak memory	284372 kb
Host	smart-4c1fbe01-ea14-456a-85ae-9250ffb3f033
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1314227534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1314227534
Directory	/workspace/34.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/34.flash_ctrl_disable.2665731802
Short name	T821
Test name
Test status
Simulation time	28982500 ps
CPU time	21.99 seconds
Started	Jul 12 07:21:17 PM PDT 24
Finished	Jul 12 07:21:52 PM PDT 24
Peak memory	273644 kb
Host	smart-0f488129-6d87-479d-bd0e-403908097984
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665731802 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_disable.2665731802
Directory	/workspace/34.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3032006882
Short name	T298
Test name
Test status
Simulation time	1696058800 ps
CPU time	63.61 seconds
Started	Jul 12 07:21:08 PM PDT 24
Finished	Jul 12 07:22:24 PM PDT 24
Peak memory	263268 kb
Host	smart-c349415c-105f-4cd0-925f-74e9dd192afe
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032006882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_ hw_sec_otp.3032006882
Directory	/workspace/34.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd.3228943049
Short name	T78
Test name
Test status
Simulation time	5972755100 ps
CPU time	195.35 seconds
Started	Jul 12 07:21:02 PM PDT 24
Finished	Jul 12 07:24:31 PM PDT 24
Peak memory	292920 kb
Host	smart-2d7abe07-7b00-4ed7-8eff-57c012bcf510
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228943049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla sh_ctrl_intr_rd.3228943049
Directory	/workspace/34.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3801919074
Short name	T1035
Test name
Test status
Simulation time	11265001600 ps
CPU time	166.08 seconds
Started	Jul 12 07:21:09 PM PDT 24
Finished	Jul 12 07:24:10 PM PDT 24
Peak memory	293056 kb
Host	smart-9859ecb5-7462-4ba8-bd85-4e81f95a73bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801919074 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.3801919074
Directory	/workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict.3967945703
Short name	T985
Test name
Test status
Simulation time	74375500 ps
CPU time	31.32 seconds
Started	Jul 12 07:21:09 PM PDT 24
Finished	Jul 12 07:21:55 PM PDT 24
Peak memory	273636 kb
Host	smart-80e21317-dc5e-4f08-b7fe-ada1f4f1b3c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967945703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl ash_ctrl_rw_evict.3967945703
Directory	/workspace/34.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.940130249
Short name	T392
Test name
Test status
Simulation time	54900500 ps
CPU time	30.59 seconds
Started	Jul 12 07:21:11 PM PDT 24
Finished	Jul 12 07:21:56 PM PDT 24
Peak memory	275696 kb
Host	smart-bda02870-ddf5-4db2-a14b-2afac1f6ead9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940130249 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.940130249
Directory	/workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/34.flash_ctrl_sec_info_access.2602661391
Short name	T585
Test name
Test status
Simulation time	1097732000 ps
CPU time	67.64 seconds
Started	Jul 12 07:21:08 PM PDT 24
Finished	Jul 12 07:22:29 PM PDT 24
Peak memory	264792 kb
Host	smart-e300f746-0bc2-4ef0-a296-a570a5c54c13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2602661391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.2602661391
Directory	/workspace/34.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/34.flash_ctrl_smoke.2816792412
Short name	T692
Test name
Test status
Simulation time	25131200 ps
CPU time	123.89 seconds
Started	Jul 12 07:21:03 PM PDT 24
Finished	Jul 12 07:23:21 PM PDT 24
Peak memory	269976 kb
Host	smart-34161a99-7f24-4dac-b890-4b2e09af8f79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816792412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.2816792412
Directory	/workspace/34.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.flash_ctrl_alert_test.429129775
Short name	T435
Test name
Test status
Simulation time	65474700 ps
CPU time	13.67 seconds
Started	Jul 12 07:21:16 PM PDT 24
Finished	Jul 12 07:21:43 PM PDT 24
Peak memory	258196 kb
Host	smart-11c047e2-a515-4ed8-ae17-8747728dd8b4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429129775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.429129775
Directory	/workspace/35.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.flash_ctrl_connect.3611359881
Short name	T734
Test name
Test status
Simulation time	14138400 ps
CPU time	16.19 seconds
Started	Jul 12 07:21:09 PM PDT 24
Finished	Jul 12 07:21:40 PM PDT 24
Peak memory	274972 kb
Host	smart-c7ed451c-cc7a-476a-a14e-f075b48727d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611359881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.3611359881
Directory	/workspace/35.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/35.flash_ctrl_disable.702632862
Short name	T43
Test name
Test status
Simulation time	13885600 ps
CPU time	22.09 seconds
Started	Jul 12 07:21:08 PM PDT 24
Finished	Jul 12 07:21:43 PM PDT 24
Peak memory	273580 kb
Host	smart-b25e983d-1289-43d3-9065-016083e2383d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702632862 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_disable.702632862
Directory	/workspace/35.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3829655553
Short name	T1018
Test name
Test status
Simulation time	2762442300 ps
CPU time	85.91 seconds
Started	Jul 12 07:21:10 PM PDT 24
Finished	Jul 12 07:22:51 PM PDT 24
Peak memory	263232 kb
Host	smart-5f25da2d-3896-4454-b13c-e9c181aaf88c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829655553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ hw_sec_otp.3829655553
Directory	/workspace/35.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.1859134826
Short name	T175
Test name
Test status
Simulation time	50144828100 ps
CPU time	552.44 seconds
Started	Jul 12 07:21:03 PM PDT 24
Finished	Jul 12 07:30:30 PM PDT 24
Peak memory	284780 kb
Host	smart-950c57fe-e117-4801-9ba7-0cace1b5d8a4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859134826 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.1859134826
Directory	/workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/35.flash_ctrl_otp_reset.2637380726
Short name	T1086
Test name
Test status
Simulation time	37073300 ps
CPU time	132.88 seconds
Started	Jul 12 07:21:03 PM PDT 24
Finished	Jul 12 07:23:30 PM PDT 24
Peak memory	261100 kb
Host	smart-59d891c8-17b3-44a3-b08e-c0545f5c4372
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637380726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o tp_reset.2637380726
Directory	/workspace/35.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict.2004804849
Short name	T827
Test name
Test status
Simulation time	45474900 ps
CPU time	31.19 seconds
Started	Jul 12 07:21:07 PM PDT 24
Finished	Jul 12 07:21:52 PM PDT 24
Peak memory	268520 kb
Host	smart-65382ac1-00f3-49ac-bbc5-e0bf8787f651
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004804849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl ash_ctrl_rw_evict.2004804849
Directory	/workspace/35.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.2162424837
Short name	T942
Test name
Test status
Simulation time	31155800 ps
CPU time	30.6 seconds
Started	Jul 12 07:21:11 PM PDT 24
Finished	Jul 12 07:21:56 PM PDT 24
Peak memory	268484 kb
Host	smart-e11cf02a-02c9-4925-9a78-948ea921e8fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162424837 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.2162424837
Directory	/workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/35.flash_ctrl_sec_info_access.3111908494
Short name	T1081
Test name
Test status
Simulation time	5018026100 ps
CPU time	82.72 seconds
Started	Jul 12 07:21:11 PM PDT 24
Finished	Jul 12 07:22:48 PM PDT 24
Peak memory	263748 kb
Host	smart-51f84f7f-4622-4705-839a-d3de3f7e37f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3111908494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.3111908494
Directory	/workspace/35.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/35.flash_ctrl_smoke.4289753535
Short name	T547
Test name
Test status
Simulation time	69705800 ps
CPU time	123.8 seconds
Started	Jul 12 07:21:02 PM PDT 24
Finished	Jul 12 07:23:20 PM PDT 24
Peak memory	277364 kb
Host	smart-26ae1d4a-c107-446e-8b05-91b55c15b51d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4289753535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.4289753535
Directory	/workspace/35.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.flash_ctrl_alert_test.994131958
Short name	T1098
Test name
Test status
Simulation time	54468000 ps
CPU time	13.71 seconds
Started	Jul 12 07:21:10 PM PDT 24
Finished	Jul 12 07:21:38 PM PDT 24
Peak memory	265216 kb
Host	smart-ea3a2c44-42fd-4bc5-8ab4-c4a3820a8254
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994131958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.994131958
Directory	/workspace/36.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.flash_ctrl_connect.796941297
Short name	T471
Test name
Test status
Simulation time	22168400 ps
CPU time	13.59 seconds
Started	Jul 12 07:21:11 PM PDT 24
Finished	Jul 12 07:21:39 PM PDT 24
Peak memory	274792 kb
Host	smart-26c76b6e-af68-4387-b22c-eaa3a7db344c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796941297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.796941297
Directory	/workspace/36.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/36.flash_ctrl_disable.1110709236
Short name	T849
Test name
Test status
Simulation time	13444200 ps
CPU time	22.5 seconds
Started	Jul 12 07:21:15 PM PDT 24
Finished	Jul 12 07:21:51 PM PDT 24
Peak memory	273588 kb
Host	smart-4600f3e3-58dc-4fe9-85a2-a33515afd463
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110709236 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_disable.1110709236
Directory	/workspace/36.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/36.flash_ctrl_hw_sec_otp.4241042890
Short name	T229
Test name
Test status
Simulation time	8898060600 ps
CPU time	141.34 seconds
Started	Jul 12 07:21:16 PM PDT 24
Finished	Jul 12 07:23:50 PM PDT 24
Peak memory	263112 kb
Host	smart-b4a550c9-8e54-421e-8ede-327496c991e1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241042890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_ hw_sec_otp.4241042890
Directory	/workspace/36.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd.482504488
Short name	T314
Test name
Test status
Simulation time	5934959300 ps
CPU time	245.24 seconds
Started	Jul 12 07:21:15 PM PDT 24
Finished	Jul 12 07:25:33 PM PDT 24
Peak memory	292288 kb
Host	smart-a0cf51c7-34d7-4036-97de-315729cd0b7d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482504488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flas h_ctrl_intr_rd.482504488
Directory	/workspace/36.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.191182357
Short name	T79
Test name
Test status
Simulation time	49625574700 ps
CPU time	350.86 seconds
Started	Jul 12 07:21:10 PM PDT 24
Finished	Jul 12 07:27:15 PM PDT 24
Peak memory	294008 kb
Host	smart-c1f1096d-9250-4c11-943b-799f82ede36f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191182357 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.191182357
Directory	/workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/36.flash_ctrl_otp_reset.2138539454
Short name	T521
Test name
Test status
Simulation time	38208900 ps
CPU time	131.99 seconds
Started	Jul 12 07:21:17 PM PDT 24
Finished	Jul 12 07:23:44 PM PDT 24
Peak memory	264912 kb
Host	smart-19591abc-0a6e-4445-9cb9-5905bec088a5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138539454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o tp_reset.2138539454
Directory	/workspace/36.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict.3369893207
Short name	T402
Test name
Test status
Simulation time	189235600 ps
CPU time	31.13 seconds
Started	Jul 12 07:21:08 PM PDT 24
Finished	Jul 12 07:21:53 PM PDT 24
Peak memory	275680 kb
Host	smart-2b523416-846f-4279-8b6e-5a50fdc07c50
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369893207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl ash_ctrl_rw_evict.3369893207
Directory	/workspace/36.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.2179141534
Short name	T24
Test name
Test status
Simulation time	37030600 ps
CPU time	28.74 seconds
Started	Jul 12 07:21:11 PM PDT 24
Finished	Jul 12 07:21:54 PM PDT 24
Peak memory	275608 kb
Host	smart-4c647827-e820-47ac-923e-ca42ba949b3f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179141534 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.2179141534
Directory	/workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/36.flash_ctrl_smoke.2962395713
Short name	T41
Test name
Test status
Simulation time	26874000 ps
CPU time	147.92 seconds
Started	Jul 12 07:21:14 PM PDT 24
Finished	Jul 12 07:23:56 PM PDT 24
Peak memory	278968 kb
Host	smart-0d10159b-cc8a-4e68-8ef2-f55062b2bee8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2962395713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2962395713
Directory	/workspace/36.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.flash_ctrl_alert_test.1199341306
Short name	T729
Test name
Test status
Simulation time	33560500 ps
CPU time	13.9 seconds
Started	Jul 12 07:21:17 PM PDT 24
Finished	Jul 12 07:21:44 PM PDT 24
Peak memory	265236 kb
Host	smart-57d68f69-fad9-479c-928f-3f990877c942
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199341306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test. 1199341306
Directory	/workspace/37.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.flash_ctrl_connect.2212202802
Short name	T409
Test name
Test status
Simulation time	28318400 ps
CPU time	13.44 seconds
Started	Jul 12 07:21:20 PM PDT 24
Finished	Jul 12 07:21:46 PM PDT 24
Peak memory	284352 kb
Host	smart-e3c9fed4-f8f1-44c4-8639-233db2ded5a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2212202802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2212202802
Directory	/workspace/37.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/37.flash_ctrl_disable.2412744639
Short name	T338
Test name
Test status
Simulation time	30286000 ps
CPU time	20.54 seconds
Started	Jul 12 07:21:18 PM PDT 24
Finished	Jul 12 07:21:52 PM PDT 24
Peak memory	273592 kb
Host	smart-3bd70af3-6a1e-41eb-8068-f1a77065fda7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412744639 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_disable.2412744639
Directory	/workspace/37.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/37.flash_ctrl_hw_sec_otp.786996563
Short name	T415
Test name
Test status
Simulation time	539809300 ps
CPU time	30.92 seconds
Started	Jul 12 07:21:18 PM PDT 24
Finished	Jul 12 07:22:03 PM PDT 24
Peak memory	260784 kb
Host	smart-bb9267f4-1efa-4219-ac20-034c8ece73ae
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786996563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_h w_sec_otp.786996563
Directory	/workspace/37.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd.4073428142
Short name	T318
Test name
Test status
Simulation time	2299218900 ps
CPU time	124.3 seconds
Started	Jul 12 07:21:19 PM PDT 24
Finished	Jul 12 07:23:37 PM PDT 24
Peak memory	291572 kb
Host	smart-c0f1a57c-4a61-46be-82a8-2e3ea3bf76bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073428142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla sh_ctrl_intr_rd.4073428142
Directory	/workspace/37.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2292921869
Short name	T567
Test name
Test status
Simulation time	25724496100 ps
CPU time	150.62 seconds
Started	Jul 12 07:21:18 PM PDT 24
Finished	Jul 12 07:24:03 PM PDT 24
Peak memory	293072 kb
Host	smart-a1e576c5-5443-4b58-8226-be997a26dfce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292921869 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.2292921869
Directory	/workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/37.flash_ctrl_otp_reset.2229154387
Short name	T351
Test name
Test status
Simulation time	215956200 ps
CPU time	132.39 seconds
Started	Jul 12 07:21:19 PM PDT 24
Finished	Jul 12 07:23:45 PM PDT 24
Peak memory	264852 kb
Host	smart-33e17e27-02d2-4508-847b-2dc1bcf757a0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229154387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o tp_reset.2229154387
Directory	/workspace/37.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict.2482227695
Short name	T954
Test name
Test status
Simulation time	30006800 ps
CPU time	30.32 seconds
Started	Jul 12 07:21:20 PM PDT 24
Finished	Jul 12 07:22:04 PM PDT 24
Peak memory	275576 kb
Host	smart-e34c6123-6ed7-4901-8399-92f34562529d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482227695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl ash_ctrl_rw_evict.2482227695
Directory	/workspace/37.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.1921911812
Short name	T1033
Test name
Test status
Simulation time	71684700 ps
CPU time	31.66 seconds
Started	Jul 12 07:21:18 PM PDT 24
Finished	Jul 12 07:22:03 PM PDT 24
Peak memory	275680 kb
Host	smart-43a181fa-705f-41a2-9f29-73d03e5628d9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921911812 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.1921911812
Directory	/workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/37.flash_ctrl_sec_info_access.4110662648
Short name	T359
Test name
Test status
Simulation time	508905500 ps
CPU time	58.82 seconds
Started	Jul 12 07:21:21 PM PDT 24
Finished	Jul 12 07:22:33 PM PDT 24
Peak memory	263712 kb
Host	smart-d3d03653-4b0d-4863-b704-329ec390cf4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4110662648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.4110662648
Directory	/workspace/37.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/37.flash_ctrl_smoke.632428928
Short name	T894
Test name
Test status
Simulation time	27797400 ps
CPU time	99.66 seconds
Started	Jul 12 07:21:19 PM PDT 24
Finished	Jul 12 07:23:12 PM PDT 24
Peak memory	276256 kb
Host	smart-efab5eac-d026-4a2c-ab02-c8b9f3bbff11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632428928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.632428928
Directory	/workspace/37.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.flash_ctrl_alert_test.3659137181
Short name	T458
Test name
Test status
Simulation time	36600400 ps
CPU time	14.07 seconds
Started	Jul 12 07:21:26 PM PDT 24
Finished	Jul 12 07:21:52 PM PDT 24
Peak memory	258216 kb
Host	smart-8798b211-6095-4d1d-821e-8380461c9106
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659137181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test. 3659137181
Directory	/workspace/38.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.flash_ctrl_connect.3105054823
Short name	T100
Test name
Test status
Simulation time	23866400 ps
CPU time	16.29 seconds
Started	Jul 12 07:21:25 PM PDT 24
Finished	Jul 12 07:21:53 PM PDT 24
Peak memory	274888 kb
Host	smart-6ae3f726-8945-49ac-9741-63f758c7c2a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105054823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3105054823
Directory	/workspace/38.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/38.flash_ctrl_disable.2265722721
Short name	T353
Test name
Test status
Simulation time	10239100 ps
CPU time	21.54 seconds
Started	Jul 12 07:21:26 PM PDT 24
Finished	Jul 12 07:21:59 PM PDT 24
Peak memory	273616 kb
Host	smart-6fffa3e3-ea69-4f55-a401-6251da8dbf15
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265722721 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_disable.2265722721
Directory	/workspace/38.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.1563448672
Short name	T637
Test name
Test status
Simulation time	3641911500 ps
CPU time	72.33 seconds
Started	Jul 12 07:21:18 PM PDT 24
Finished	Jul 12 07:22:44 PM PDT 24
Peak memory	263216 kb
Host	smart-59a3a250-721f-4b33-836e-aa6e6db2888d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563448672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ hw_sec_otp.1563448672
Directory	/workspace/38.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd.2830883012
Short name	T256
Test name
Test status
Simulation time	1390683800 ps
CPU time	141.56 seconds
Started	Jul 12 07:21:25 PM PDT 24
Finished	Jul 12 07:23:58 PM PDT 24
Peak memory	294024 kb
Host	smart-b2be6ae5-8c44-4bdb-8378-fdb9f464012c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830883012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla sh_ctrl_intr_rd.2830883012
Directory	/workspace/38.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1487458858
Short name	T1004
Test name
Test status
Simulation time	11809650300 ps
CPU time	273.71 seconds
Started	Jul 12 07:21:27 PM PDT 24
Finished	Jul 12 07:26:13 PM PDT 24
Peak memory	292964 kb
Host	smart-1fa0c7f8-e2c1-4ae2-807f-2318a02a7c34
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487458858 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.1487458858
Directory	/workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict.2369072318
Short name	T862
Test name
Test status
Simulation time	27386500 ps
CPU time	30.71 seconds
Started	Jul 12 07:21:27 PM PDT 24
Finished	Jul 12 07:22:09 PM PDT 24
Peak memory	275660 kb
Host	smart-6cf56cc8-d32a-4324-bda5-59a2bcb321ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369072318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl ash_ctrl_rw_evict.2369072318
Directory	/workspace/38.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.3460605197
Short name	T808
Test name
Test status
Simulation time	260147300 ps
CPU time	31.16 seconds
Started	Jul 12 07:21:25 PM PDT 24
Finished	Jul 12 07:22:08 PM PDT 24
Peak memory	268468 kb
Host	smart-eaa8e958-0872-43bf-b250-6a7478042432
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460605197 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.3460605197
Directory	/workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/38.flash_ctrl_sec_info_access.2700660067
Short name	T366
Test name
Test status
Simulation time	2267266300 ps
CPU time	76.58 seconds
Started	Jul 12 07:21:26 PM PDT 24
Finished	Jul 12 07:22:54 PM PDT 24
Peak memory	263696 kb
Host	smart-8e049d49-7ce4-4845-bc1a-751decefa13f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2700660067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2700660067
Directory	/workspace/38.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/38.flash_ctrl_smoke.3342967639
Short name	T870
Test name
Test status
Simulation time	79085000 ps
CPU time	175.34 seconds
Started	Jul 12 07:21:17 PM PDT 24
Finished	Jul 12 07:24:27 PM PDT 24
Peak memory	276968 kb
Host	smart-b3cbb515-2c86-4b3f-a306-59642297d57f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3342967639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3342967639
Directory	/workspace/38.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.flash_ctrl_alert_test.1332792299
Short name	T466
Test name
Test status
Simulation time	167430700 ps
CPU time	13.86 seconds
Started	Jul 12 07:21:34 PM PDT 24
Finished	Jul 12 07:21:59 PM PDT 24
Peak memory	258520 kb
Host	smart-ed5c9d2e-001d-4294-8ecd-3d81d439d9df
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332792299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test. 1332792299
Directory	/workspace/39.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.flash_ctrl_connect.2580848527
Short name	T101
Test name
Test status
Simulation time	51748900 ps
CPU time	13.33 seconds
Started	Jul 12 07:21:37 PM PDT 24
Finished	Jul 12 07:22:00 PM PDT 24
Peak memory	274932 kb
Host	smart-0fd302c3-278a-4aa5-84ed-1588b4e4271c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580848527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2580848527
Directory	/workspace/39.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1504965664
Short name	T4
Test name
Test status
Simulation time	7033719100 ps
CPU time	81.96 seconds
Started	Jul 12 07:21:35 PM PDT 24
Finished	Jul 12 07:23:07 PM PDT 24
Peak memory	260880 kb
Host	smart-5d38059f-71c5-4fd9-803f-85d132faae1d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504965664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_ hw_sec_otp.1504965664
Directory	/workspace/39.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd.3285184127
Short name	T34
Test name
Test status
Simulation time	6451470100 ps
CPU time	195.25 seconds
Started	Jul 12 07:21:34 PM PDT 24
Finished	Jul 12 07:25:00 PM PDT 24
Peak memory	284752 kb
Host	smart-d9140af1-fd34-4b96-b1ee-68f92a223dd6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285184127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla sh_ctrl_intr_rd.3285184127
Directory	/workspace/39.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.199689935
Short name	T406
Test name
Test status
Simulation time	22866835800 ps
CPU time	159.31 seconds
Started	Jul 12 07:21:34 PM PDT 24
Finished	Jul 12 07:24:24 PM PDT 24
Peak memory	294188 kb
Host	smart-08188649-55ac-4599-a534-fca6dd50b0ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199689935 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.199689935
Directory	/workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/39.flash_ctrl_otp_reset.432256829
Short name	T634
Test name
Test status
Simulation time	98898300 ps
CPU time	108.8 seconds
Started	Jul 12 07:21:33 PM PDT 24
Finished	Jul 12 07:23:32 PM PDT 24
Peak memory	260972 kb
Host	smart-2a30ad31-5dba-4a64-bc1c-baae7f7ce854
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432256829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_ot p_reset.432256829
Directory	/workspace/39.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict.998060916
Short name	T668
Test name
Test status
Simulation time	29586900 ps
CPU time	30.79 seconds
Started	Jul 12 07:21:34 PM PDT 24
Finished	Jul 12 07:22:14 PM PDT 24
Peak memory	268496 kb
Host	smart-5652c118-e8e5-4983-a5e6-254c8b478b45
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998060916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla sh_ctrl_rw_evict.998060916
Directory	/workspace/39.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.4179218667
Short name	T468
Test name
Test status
Simulation time	79637000 ps
CPU time	31.72 seconds
Started	Jul 12 07:21:33 PM PDT 24
Finished	Jul 12 07:22:15 PM PDT 24
Peak memory	275624 kb
Host	smart-755c35c8-9c6b-47d0-97f4-7ee0903b2221
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179218667 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.4179218667
Directory	/workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/39.flash_ctrl_sec_info_access.2925666962
Short name	T369
Test name
Test status
Simulation time	541615300 ps
CPU time	69.1 seconds
Started	Jul 12 07:21:37 PM PDT 24
Finished	Jul 12 07:22:56 PM PDT 24
Peak memory	263620 kb
Host	smart-1b4c315d-dd36-4bb8-a4e8-60f02f206cda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2925666962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.2925666962
Directory	/workspace/39.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/39.flash_ctrl_smoke.2170584029
Short name	T534
Test name
Test status
Simulation time	1398619100 ps
CPU time	82.17 seconds
Started	Jul 12 07:21:35 PM PDT 24
Finished	Jul 12 07:23:07 PM PDT 24
Peak memory	278436 kb
Host	smart-ffe7b8e5-aa45-4120-9c67-727dca32eb86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2170584029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.2170584029
Directory	/workspace/39.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_alert_test.2010642937
Short name	T915
Test name
Test status
Simulation time	34731600 ps
CPU time	13.54 seconds
Started	Jul 12 07:12:27 PM PDT 24
Finished	Jul 12 07:13:27 PM PDT 24
Peak memory	265192 kb
Host	smart-c95cf34b-db79-4657-9f2f-0762b2997bbc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010642937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.2 010642937
Directory	/workspace/4.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.flash_ctrl_config_regwen.507029371
Short name	T206
Test name
Test status
Simulation time	35529100 ps
CPU time	14.14 seconds
Started	Jul 12 07:12:22 PM PDT 24
Finished	Jul 12 07:13:25 PM PDT 24
Peak memory	261528 kb
Host	smart-31d81dcc-d23b-48c0-b1d9-7465786dc6b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507029371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. flash_ctrl_config_regwen.507029371
Directory	/workspace/4.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/4.flash_ctrl_connect.189692139
Short name	T767
Test name
Test status
Simulation time	18607900 ps
CPU time	15.85 seconds
Started	Jul 12 07:12:27 PM PDT 24
Finished	Jul 12 07:13:29 PM PDT 24
Peak memory	284248 kb
Host	smart-246cb445-5932-4266-a96b-f7ab814ae98b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=189692139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.189692139
Directory	/workspace/4.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/4.flash_ctrl_disable.1343034346
Short name	T168
Test name
Test status
Simulation time	25915300 ps
CPU time	22.05 seconds
Started	Jul 12 07:12:13 PM PDT 24
Finished	Jul 12 07:13:29 PM PDT 24
Peak memory	265352 kb
Host	smart-79c5d84b-6913-4ff4-a6ed-7a81ef550618
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343034346 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_disable.1343034346
Directory	/workspace/4.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/4.flash_ctrl_erase_suspend.3291704845
Short name	T1089
Test name
Test status
Simulation time	2701918500 ps
CPU time	445.58 seconds
Started	Jul 12 07:11:55 PM PDT 24
Finished	Jul 12 07:20:25 PM PDT 24
Peak memory	263504 kb
Host	smart-67c6da5c-20f3-44a2-acfb-c175dfe157ac
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3291704845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3291704845
Directory	/workspace/4.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_mp.3623067121
Short name	T907
Test name
Test status
Simulation time	35781071000 ps
CPU time	2456.33 seconds
Started	Jul 12 07:12:06 PM PDT 24
Finished	Jul 12 07:54:01 PM PDT 24
Peak memory	265184 kb
Host	smart-3dbfb8d7-bd88-4bf6-826f-45c7405b45e9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3623067121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.3623067121
Directory	/workspace/4.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_type.3207566596
Short name	T1003
Test name
Test status
Simulation time	1930061800 ps
CPU time	3289.8 seconds
Started	Jul 12 07:12:05 PM PDT 24
Finished	Jul 12 08:07:54 PM PDT 24
Peak memory	263760 kb
Host	smart-95cea1ca-961b-4b17-8bc2-eb881d7fa773
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207566596 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.3207566596
Directory	/workspace/4.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_win.2686053288
Short name	T935
Test name
Test status
Simulation time	769825000 ps
CPU time	1062.06 seconds
Started	Jul 12 07:12:04 PM PDT 24
Finished	Jul 12 07:30:46 PM PDT 24
Peak memory	272604 kb
Host	smart-cf952c9f-0966-4456-ba76-8b5f923cf3ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686053288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.2686053288
Directory	/workspace/4.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fetch_code.4238135906
Short name	T739
Test name
Test status
Simulation time	125306600 ps
CPU time	23.99 seconds
Started	Jul 12 07:12:04 PM PDT 24
Finished	Jul 12 07:13:28 PM PDT 24
Peak memory	263664 kb
Host	smart-42da261f-a0e7-444d-ad1c-c3d7e62004a8
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238135906 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.4238135906
Directory	/workspace/4.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fs_sup.2496421019
Short name	T72
Test name
Test status
Simulation time	667478400 ps
CPU time	42.82 seconds
Started	Jul 12 07:12:24 PM PDT 24
Finished	Jul 12 07:13:53 PM PDT 24
Peak memory	264948 kb
Host	smart-e4845391-7f38-4d08-8b1e-018b77487180
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496421019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 4.flash_ctrl_fs_sup.2496421019
Directory	/workspace/4.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/4.flash_ctrl_full_mem_access.607686028
Short name	T140
Test name
Test status
Simulation time	387383118400 ps
CPU time	3032.08 seconds
Started	Jul 12 07:12:03 PM PDT 24
Finished	Jul 12 08:03:36 PM PDT 24
Peak memory	265076 kb
Host	smart-1c3235b8-108e-4da1-8848-22b42482c5c0
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607686028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct rl_full_mem_access.607686028
Directory	/workspace/4.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.2311525545
Short name	T162
Test name
Test status
Simulation time	328643649200 ps
CPU time	2221.23 seconds
Started	Jul 12 07:12:06 PM PDT 24
Finished	Jul 12 07:50:06 PM PDT 24
Peak memory	265292 kb
Host	smart-aa4798c8-25c7-4c29-92ed-eb76957cd67a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311525545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.flash_ctrl_host_ctrl_arb.2311525545
Directory	/workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_dir_rd.3897332575
Short name	T1071
Test name
Test status
Simulation time	86014700 ps
CPU time	37.15 seconds
Started	Jul 12 07:11:53 PM PDT 24
Finished	Jul 12 07:13:36 PM PDT 24
Peak memory	265256 kb
Host	smart-9fcd6834-9ea6-4db9-8621-3a25aff59b50
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3897332575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.3897332575
Directory	/workspace/4.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.620085987
Short name	T270
Test name
Test status
Simulation time	10018835000 ps
CPU time	76.12 seconds
Started	Jul 12 07:12:23 PM PDT 24
Finished	Jul 12 07:14:27 PM PDT 24
Peak memory	292192 kb
Host	smart-7fe7a34a-d25b-4f42-a8e2-9f94675b3bbd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620085987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.620085987
Directory	/workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.1639547628
Short name	T1030
Test name
Test status
Simulation time	26994500 ps
CPU time	13.21 seconds
Started	Jul 12 07:12:24 PM PDT 24
Finished	Jul 12 07:13:24 PM PDT 24
Peak memory	265012 kb
Host	smart-bbfbb096-dabe-48ee-afe8-13d4391c1b4f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639547628 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.1639547628
Directory	/workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2975290660
Short name	T171
Test name
Test status
Simulation time	40121077800 ps
CPU time	783.61 seconds
Started	Jul 12 07:12:03 PM PDT 24
Finished	Jul 12 07:26:07 PM PDT 24
Peak memory	260936 kb
Host	smart-fd01dcee-4d4f-481c-a18a-dd0b96f6ed67
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975290660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.flash_ctrl_hw_rma_reset.2975290660
Directory	/workspace/4.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.2186191837
Short name	T300
Test name
Test status
Simulation time	4629465400 ps
CPU time	156.52 seconds
Started	Jul 12 07:11:56 PM PDT 24
Finished	Jul 12 07:15:37 PM PDT 24
Peak memory	263372 kb
Host	smart-6f2fdaf2-38a8-4d6f-adcb-4ac179120f97
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186191837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h w_sec_otp.2186191837
Directory	/workspace/4.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_integrity.3731907873
Short name	T231
Test name
Test status
Simulation time	13946059600 ps
CPU time	697.81 seconds
Started	Jul 12 07:12:16 PM PDT 24
Finished	Jul 12 07:24:46 PM PDT 24
Peak memory	335580 kb
Host	smart-848aaf90-ac04-4600-a9ce-d2d0533f5d04
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731907873 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_integrity.3731907873
Directory	/workspace/4.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd.1761657950
Short name	T1106
Test name
Test status
Simulation time	2157202900 ps
CPU time	139.69 seconds
Started	Jul 12 07:12:14 PM PDT 24
Finished	Jul 12 07:15:27 PM PDT 24
Peak memory	290920 kb
Host	smart-40499a60-c71a-478f-b480-668b6cb2150e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761657950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_intr_rd.1761657950
Directory	/workspace/4.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3799843951
Short name	T316
Test name
Test status
Simulation time	64570310800 ps
CPU time	280.8 seconds
Started	Jul 12 07:12:12 PM PDT 24
Finished	Jul 12 07:17:48 PM PDT 24
Peak memory	292028 kb
Host	smart-c351ea3c-24c7-48ae-9e65-b54d2a4caf88
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799843951 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.3799843951
Directory	/workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr.547836627
Short name	T27
Test name
Test status
Simulation time	9692853900 ps
CPU time	72.69 seconds
Started	Jul 12 07:12:12 PM PDT 24
Finished	Jul 12 07:14:20 PM PDT 24
Peak memory	265276 kb
Host	smart-ea453fd9-2340-475e-aa90-d7cfc3263408
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547836627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.flash_ctrl_intr_wr.547836627
Directory	/workspace/4.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3982642205
Short name	T1094
Test name
Test status
Simulation time	22522114100 ps
CPU time	190.62 seconds
Started	Jul 12 07:12:16 PM PDT 24
Finished	Jul 12 07:16:18 PM PDT 24
Peak memory	265312 kb
Host	smart-60e8f789-2793-4800-a1bf-af09c0ded7a2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398 2642205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3982642205
Directory	/workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_invalid_op.3855513186
Short name	T1013
Test name
Test status
Simulation time	3891158400 ps
CPU time	78.62 seconds
Started	Jul 12 07:12:02 PM PDT 24
Finished	Jul 12 07:14:20 PM PDT 24
Peak memory	263556 kb
Host	smart-790c2ffc-7621-431f-9175-708286152d06
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855513186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.3855513186
Directory	/workspace/4.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_lcmgr_intg.340077072
Short name	T906
Test name
Test status
Simulation time	55058100 ps
CPU time	13.78 seconds
Started	Jul 12 07:12:23 PM PDT 24
Finished	Jul 12 07:13:24 PM PDT 24
Peak memory	260028 kb
Host	smart-2114a47e-4eb5-4f19-b8ac-0fee0efeb923
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340077072 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.340077072
Directory	/workspace/4.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/4.flash_ctrl_otp_reset.1249164812
Short name	T1076
Test name
Test status
Simulation time	77216600 ps
CPU time	127.29 seconds
Started	Jul 12 07:12:02 PM PDT 24
Finished	Jul 12 07:15:09 PM PDT 24
Peak memory	260100 kb
Host	smart-09f9e824-04cc-43f2-a673-2ddc3eaaf44c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249164812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot p_reset.1249164812
Directory	/workspace/4.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_oversize_error.746291262
Short name	T1032
Test name
Test status
Simulation time	6134080700 ps
CPU time	208.73 seconds
Started	Jul 12 07:12:16 PM PDT 24
Finished	Jul 12 07:16:36 PM PDT 24
Peak memory	295224 kb
Host	smart-df78014d-5d3b-4695-be82-1d757bb6cf17
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746291262 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.746291262
Directory	/workspace/4.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2921472393
Short name	T213
Test name
Test status
Simulation time	195436400 ps
CPU time	13.72 seconds
Started	Jul 12 07:12:22 PM PDT 24
Finished	Jul 12 07:13:24 PM PDT 24
Peak memory	265044 kb
Host	smart-58d92b5c-0850-4c7f-bfd1-63469a263526
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2921472393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2921472393
Directory	/workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb.4087188308
Short name	T192
Test name
Test status
Simulation time	770450600 ps
CPU time	491.69 seconds
Started	Jul 12 07:11:55 PM PDT 24
Finished	Jul 12 07:21:11 PM PDT 24
Peak memory	263196 kb
Host	smart-a131514d-954f-430e-b3cb-94f8d0dc51ca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4087188308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.4087188308
Directory	/workspace/4.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_prog_reset.1512448553
Short name	T422
Test name
Test status
Simulation time	63986000 ps
CPU time	13.62 seconds
Started	Jul 12 07:12:12 PM PDT 24
Finished	Jul 12 07:13:21 PM PDT 24
Peak memory	265228 kb
Host	smart-e032695c-7a73-4c4b-98bb-4e378d026cdf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512448553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.flash_ctrl_prog_reset.1512448553
Directory	/workspace/4.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rand_ops.1611914606
Short name	T1011
Test name
Test status
Simulation time	270773500 ps
CPU time	1106.03 seconds
Started	Jul 12 07:11:53 PM PDT 24
Finished	Jul 12 07:31:25 PM PDT 24
Peak memory	286872 kb
Host	smart-a8efa840-b643-42a6-a8ee-d2b177aa2e50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1611914606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.1611914606
Directory	/workspace/4.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rd_buff_evict.593973312
Short name	T956
Test name
Test status
Simulation time	201719400 ps
CPU time	100.94 seconds
Started	Jul 12 07:11:56 PM PDT 24
Finished	Jul 12 07:14:41 PM PDT 24
Peak memory	262808 kb
Host	smart-6db84e9f-4da3-4bac-9562-6fc5b17da268
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=593973312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.593973312
Directory	/workspace/4.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_re_evict.2968638662
Short name	T533
Test name
Test status
Simulation time	86902400 ps
CPU time	36.4 seconds
Started	Jul 12 07:12:11 PM PDT 24
Finished	Jul 12 07:13:43 PM PDT 24
Peak memory	274880 kb
Host	smart-80531312-aca5-411f-900b-e2208e385f9d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968638662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_re_evict.2968638662
Directory	/workspace/4.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.3347151498
Short name	T191
Test name
Test status
Simulation time	61230700 ps
CPU time	23.37 seconds
Started	Jul 12 07:12:14 PM PDT 24
Finished	Jul 12 07:13:30 PM PDT 24
Peak memory	265152 kb
Host	smart-6ae20983-1afc-402f-8382-4a5ecb2c25dd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347151498 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.3347151498
Directory	/workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.418724588
Short name	T846
Test name
Test status
Simulation time	92355400 ps
CPU time	23.28 seconds
Started	Jul 12 07:12:12 PM PDT 24
Finished	Jul 12 07:13:30 PM PDT 24
Peak memory	264564 kb
Host	smart-b4233c8c-fd90-4ddd-9a21-38a2b1df60c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418724588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_read_word_sweep_serr.418724588
Directory	/workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro.2831984537
Short name	T987
Test name
Test status
Simulation time	556586900 ps
CPU time	122.7 seconds
Started	Jul 12 07:12:04 PM PDT 24
Finished	Jul 12 07:15:06 PM PDT 24
Peak memory	291256 kb
Host	smart-f29d4b7e-9a2f-4822-9f31-a4ded6dbd28f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831984537 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_ro.2831984537
Directory	/workspace/4.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_derr.1353219983
Short name	T375
Test name
Test status
Simulation time	2331472600 ps
CPU time	144.22 seconds
Started	Jul 12 07:12:11 PM PDT 24
Finished	Jul 12 07:15:31 PM PDT 24
Peak memory	281864 kb
Host	smart-50d18dab-b0ba-42d4-a12a-b898ddab3110
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1353219983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.1353219983
Directory	/workspace/4.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_serr.4052775495
Short name	T1085
Test name
Test status
Simulation time	7358939300 ps
CPU time	153.44 seconds
Started	Jul 12 07:12:14 PM PDT 24
Finished	Jul 12 07:15:40 PM PDT 24
Peak memory	294816 kb
Host	smart-3d3855fe-f7bd-4d57-978e-b4dc43bb15e0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052775495 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.4052775495
Directory	/workspace/4.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw.554073136
Short name	T1040
Test name
Test status
Simulation time	5966899900 ps
CPU time	528.93 seconds
Started	Jul 12 07:12:17 PM PDT 24
Finished	Jul 12 07:21:57 PM PDT 24
Peak memory	314452 kb
Host	smart-1d23fb7f-611c-4145-957d-c2b01ae81ea5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554073136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw.554073136
Directory	/workspace/4.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict.3828167660
Short name	T754
Test name
Test status
Simulation time	46875900 ps
CPU time	31.52 seconds
Started	Jul 12 07:12:12 PM PDT 24
Finished	Jul 12 07:13:39 PM PDT 24
Peak memory	273620 kb
Host	smart-b9050351-e9b9-43aa-9513-6f7bc76f8f82
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828167660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_rw_evict.3828167660
Directory	/workspace/4.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.3041261766
Short name	T1068
Test name
Test status
Simulation time	67438100 ps
CPU time	32.38 seconds
Started	Jul 12 07:12:12 PM PDT 24
Finished	Jul 12 07:13:39 PM PDT 24
Peak memory	268444 kb
Host	smart-7e135a78-d631-4030-9ff1-c24828860832
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041261766 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.3041261766
Directory	/workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_serr.3084161683
Short name	T1077
Test name
Test status
Simulation time	5911007600 ps
CPU time	583.43 seconds
Started	Jul 12 07:12:12 PM PDT 24
Finished	Jul 12 07:22:51 PM PDT 24
Peak memory	313096 kb
Host	smart-0336c434-ca24-4b56-b5d4-e83a1d137583
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084161683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s err.3084161683
Directory	/workspace/4.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_cm.1010774520
Short name	T102
Test name
Test status
Simulation time	15912806100 ps
CPU time	4915.93 seconds
Started	Jul 12 07:12:11 PM PDT 24
Finished	Jul 12 08:35:03 PM PDT 24
Peak memory	286292 kb
Host	smart-8ff2491a-0594-4d4f-bcbd-a0086b9072bb
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010774520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.1010774520
Directory	/workspace/4.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_info_access.2822952469
Short name	T800
Test name
Test status
Simulation time	12449519100 ps
CPU time	60.77 seconds
Started	Jul 12 07:12:13 PM PDT 24
Finished	Jul 12 07:14:08 PM PDT 24
Peak memory	263772 kb
Host	smart-f533c4b1-4fdf-441a-9cbb-b3bc538f70ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822952469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2822952469
Directory	/workspace/4.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_address.3241770640
Short name	T479
Test name
Test status
Simulation time	847229600 ps
CPU time	50.14 seconds
Started	Jul 12 07:12:12 PM PDT 24
Finished	Jul 12 07:13:57 PM PDT 24
Peak memory	273656 kb
Host	smart-fb53db64-b1f6-4dc4-8bce-d2e6c2aecd86
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241770640 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 4.flash_ctrl_serr_address.3241770640
Directory	/workspace/4.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_counter.1181469724
Short name	T5
Test name
Test status
Simulation time	6783015100 ps
CPU time	73.18 seconds
Started	Jul 12 07:12:12 PM PDT 24
Finished	Jul 12 07:14:20 PM PDT 24
Peak memory	274308 kb
Host	smart-4f4fa7b3-ef0e-4492-9c66-7f6cd5ee6f09
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181469724 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_serr_counter.1181469724
Directory	/workspace/4.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke.1537160257
Short name	T571
Test name
Test status
Simulation time	25454200 ps
CPU time	124.02 seconds
Started	Jul 12 07:11:56 PM PDT 24
Finished	Jul 12 07:15:04 PM PDT 24
Peak memory	276212 kb
Host	smart-17d5fb5c-81fd-49fa-9b0e-1e89c03b34e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537160257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.1537160257
Directory	/workspace/4.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke_hw.2045023897
Short name	T519
Test name
Test status
Simulation time	15174400 ps
CPU time	24.28 seconds
Started	Jul 12 07:11:53 PM PDT 24
Finished	Jul 12 07:13:23 PM PDT 24
Peak memory	259384 kb
Host	smart-a18518d5-3589-4c78-90e5-04f8f521386c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2045023897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.2045023897
Directory	/workspace/4.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_stress_all.1757990543
Short name	T713
Test name
Test status
Simulation time	1202052000 ps
CPU time	419.95 seconds
Started	Jul 12 07:12:27 PM PDT 24
Finished	Jul 12 07:20:13 PM PDT 24
Peak memory	289752 kb
Host	smart-d80c3d56-b8ff-4452-9502-2361e7f7c3f1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757990543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres s_all.1757990543
Directory	/workspace/4.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sw_op.1562917663
Short name	T497
Test name
Test status
Simulation time	39928900 ps
CPU time	27.23 seconds
Started	Jul 12 07:11:56 PM PDT 24
Finished	Jul 12 07:13:28 PM PDT 24
Peak memory	262224 kb
Host	smart-18bc565e-f834-464a-99ad-a61563edc34c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562917663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.1562917663
Directory	/workspace/4.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_wo.505129220
Short name	T924
Test name
Test status
Simulation time	8135761100 ps
CPU time	223.66 seconds
Started	Jul 12 07:12:03 PM PDT 24
Finished	Jul 12 07:16:47 PM PDT 24
Peak memory	265312 kb
Host	smart-8eb2ffb3-375e-4194-ae26-e0d0cebcfad9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505129220 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 4.flash_ctrl_wo.505129220
Directory	/workspace/4.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/40.flash_ctrl_alert_test.119020153
Short name	T412
Test name
Test status
Simulation time	46736600 ps
CPU time	13.84 seconds
Started	Jul 12 07:21:41 PM PDT 24
Finished	Jul 12 07:22:04 PM PDT 24
Peak memory	258176 kb
Host	smart-55427408-6c8f-4610-bf79-57cfc9bb843b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119020153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.119020153
Directory	/workspace/40.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.flash_ctrl_connect.2186242009
Short name	T489
Test name
Test status
Simulation time	27704400 ps
CPU time	16.44 seconds
Started	Jul 12 07:21:43 PM PDT 24
Finished	Jul 12 07:22:07 PM PDT 24
Peak memory	274972 kb
Host	smart-49a598bb-d0e8-4c19-beb6-3a1a1c5de5b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186242009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.2186242009
Directory	/workspace/40.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/40.flash_ctrl_disable.884031973
Short name	T577
Test name
Test status
Simulation time	13808300 ps
CPU time	23.22 seconds
Started	Jul 12 07:21:33 PM PDT 24
Finished	Jul 12 07:22:06 PM PDT 24
Peak memory	273700 kb
Host	smart-429728da-9912-4cfa-8f1f-ebe07b323e67
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884031973 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_disable.884031973
Directory	/workspace/40.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.275348555
Short name	T1046
Test name
Test status
Simulation time	18387103400 ps
CPU time	152.45 seconds
Started	Jul 12 07:21:34 PM PDT 24
Finished	Jul 12 07:24:16 PM PDT 24
Peak memory	263284 kb
Host	smart-fde2064a-d812-4e63-a4e0-25e4f05febba
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275348555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_h w_sec_otp.275348555
Directory	/workspace/40.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/40.flash_ctrl_otp_reset.990428272
Short name	T860
Test name
Test status
Simulation time	81223900 ps
CPU time	133.74 seconds
Started	Jul 12 07:21:35 PM PDT 24
Finished	Jul 12 07:23:59 PM PDT 24
Peak memory	261196 kb
Host	smart-a4f75494-721d-459c-b568-5485ed07afa1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990428272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ot p_reset.990428272
Directory	/workspace/40.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/40.flash_ctrl_sec_info_access.384907017
Short name	T523
Test name
Test status
Simulation time	5270605000 ps
CPU time	66.53 seconds
Started	Jul 12 07:21:41 PM PDT 24
Finished	Jul 12 07:22:56 PM PDT 24
Peak memory	262640 kb
Host	smart-4188102d-3101-42ae-85d5-7aae00884b54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384907017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.384907017
Directory	/workspace/40.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/40.flash_ctrl_smoke.782192007
Short name	T454
Test name
Test status
Simulation time	54702100 ps
CPU time	49.79 seconds
Started	Jul 12 07:21:33 PM PDT 24
Finished	Jul 12 07:22:33 PM PDT 24
Peak memory	271360 kb
Host	smart-a668b89f-43ce-4008-accc-f30b2cb3a47e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782192007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.782192007
Directory	/workspace/40.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.flash_ctrl_alert_test.778932165
Short name	T437
Test name
Test status
Simulation time	102670400 ps
CPU time	13.91 seconds
Started	Jul 12 07:21:41 PM PDT 24
Finished	Jul 12 07:22:04 PM PDT 24
Peak memory	265200 kb
Host	smart-22860e39-db4b-49c5-91a6-c379df835c86
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778932165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.778932165
Directory	/workspace/41.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.flash_ctrl_connect.2200429104
Short name	T710
Test name
Test status
Simulation time	26763800 ps
CPU time	16.34 seconds
Started	Jul 12 07:21:42 PM PDT 24
Finished	Jul 12 07:22:07 PM PDT 24
Peak memory	274896 kb
Host	smart-4ae0c760-6fc7-4611-ae50-41e8da7cf528
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2200429104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2200429104
Directory	/workspace/41.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/41.flash_ctrl_disable.2718479599
Short name	T725
Test name
Test status
Simulation time	15124500 ps
CPU time	22.24 seconds
Started	Jul 12 07:22:02 PM PDT 24
Finished	Jul 12 07:22:30 PM PDT 24
Peak memory	273528 kb
Host	smart-467d51f5-764e-462b-9be5-5dbaaa7cb20f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718479599 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_disable.2718479599
Directory	/workspace/41.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.2282653767
Short name	T498
Test name
Test status
Simulation time	1206539700 ps
CPU time	94.33 seconds
Started	Jul 12 07:21:41 PM PDT 24
Finished	Jul 12 07:23:24 PM PDT 24
Peak memory	263236 kb
Host	smart-9ce99143-f800-4783-989c-95e37809596b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282653767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ hw_sec_otp.2282653767
Directory	/workspace/41.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/41.flash_ctrl_otp_reset.2273734791
Short name	T786
Test name
Test status
Simulation time	37291800 ps
CPU time	110.18 seconds
Started	Jul 12 07:21:42 PM PDT 24
Finished	Jul 12 07:23:41 PM PDT 24
Peak memory	261072 kb
Host	smart-780d0617-8601-4d19-93ae-2d2fb685c451
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273734791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o tp_reset.2273734791
Directory	/workspace/41.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/41.flash_ctrl_sec_info_access.1511043723
Short name	T371
Test name
Test status
Simulation time	9433804100 ps
CPU time	82.43 seconds
Started	Jul 12 07:21:41 PM PDT 24
Finished	Jul 12 07:23:13 PM PDT 24
Peak memory	263156 kb
Host	smart-b9187e2b-2c4c-4d5d-8c00-dcc0871f6b84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1511043723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.1511043723
Directory	/workspace/41.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/41.flash_ctrl_smoke.938403724
Short name	T646
Test name
Test status
Simulation time	26421500 ps
CPU time	99.75 seconds
Started	Jul 12 07:21:42 PM PDT 24
Finished	Jul 12 07:23:30 PM PDT 24
Peak memory	275868 kb
Host	smart-a54defd9-d9bb-4b70-9a4e-253239ab9d4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938403724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.938403724
Directory	/workspace/41.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.flash_ctrl_alert_test.2824009339
Short name	T417
Test name
Test status
Simulation time	85807200 ps
CPU time	13.85 seconds
Started	Jul 12 07:21:51 PM PDT 24
Finished	Jul 12 07:22:10 PM PDT 24
Peak memory	258248 kb
Host	smart-3b8bf851-d0ee-4916-ac3f-951adbb53662
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824009339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test. 2824009339
Directory	/workspace/42.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.flash_ctrl_connect.225873964
Short name	T430
Test name
Test status
Simulation time	47594000 ps
CPU time	15.66 seconds
Started	Jul 12 07:21:51 PM PDT 24
Finished	Jul 12 07:22:12 PM PDT 24
Peak memory	274988 kb
Host	smart-6d6c2338-9862-4c46-a15f-cba721c70ed6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225873964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.225873964
Directory	/workspace/42.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/42.flash_ctrl_disable.1878252560
Short name	T556
Test name
Test status
Simulation time	27643000 ps
CPU time	20.22 seconds
Started	Jul 12 07:21:43 PM PDT 24
Finished	Jul 12 07:22:11 PM PDT 24
Peak memory	273612 kb
Host	smart-f9531ec6-659b-43bb-ab03-bb917b61a92f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878252560 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_disable.1878252560
Directory	/workspace/42.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.4211781700
Short name	T299
Test name
Test status
Simulation time	16804255100 ps
CPU time	246.35 seconds
Started	Jul 12 07:21:42 PM PDT 24
Finished	Jul 12 07:25:57 PM PDT 24
Peak memory	263312 kb
Host	smart-de83900c-0257-415d-8cb2-a4ec17c6b60b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211781700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_ hw_sec_otp.4211781700
Directory	/workspace/42.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/42.flash_ctrl_otp_reset.2928476425
Short name	T940
Test name
Test status
Simulation time	579067600 ps
CPU time	131.8 seconds
Started	Jul 12 07:21:42 PM PDT 24
Finished	Jul 12 07:24:02 PM PDT 24
Peak memory	261012 kb
Host	smart-743bc44b-0b52-475b-9908-5beb1ade48e7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928476425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o tp_reset.2928476425
Directory	/workspace/42.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/42.flash_ctrl_sec_info_access.1450544189
Short name	T108
Test name
Test status
Simulation time	2189197400 ps
CPU time	55.64 seconds
Started	Jul 12 07:21:51 PM PDT 24
Finished	Jul 12 07:22:52 PM PDT 24
Peak memory	263744 kb
Host	smart-1e16697e-db7d-433d-9ea6-df7326279bc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450544189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.1450544189
Directory	/workspace/42.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/42.flash_ctrl_smoke.3557911936
Short name	T463
Test name
Test status
Simulation time	33829400 ps
CPU time	123.99 seconds
Started	Jul 12 07:21:42 PM PDT 24
Finished	Jul 12 07:23:54 PM PDT 24
Peak memory	276368 kb
Host	smart-07e53e1e-b970-452f-926e-a9de2a578a7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557911936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3557911936
Directory	/workspace/42.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.flash_ctrl_alert_test.1417238926
Short name	T83
Test name
Test status
Simulation time	32041200 ps
CPU time	13.87 seconds
Started	Jul 12 07:21:53 PM PDT 24
Finished	Jul 12 07:22:12 PM PDT 24
Peak memory	258200 kb
Host	smart-52313883-10ca-45e0-86b6-0da7dc138434
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417238926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test. 1417238926
Directory	/workspace/43.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.flash_ctrl_connect.968049409
Short name	T110
Test name
Test status
Simulation time	47038500 ps
CPU time	15.74 seconds
Started	Jul 12 07:21:54 PM PDT 24
Finished	Jul 12 07:22:15 PM PDT 24
Peak memory	284356 kb
Host	smart-cb5164ec-bf8f-4171-b21e-540674e3d99b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968049409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.968049409
Directory	/workspace/43.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/43.flash_ctrl_disable.2783755020
Short name	T805
Test name
Test status
Simulation time	13556100 ps
CPU time	22.34 seconds
Started	Jul 12 07:21:54 PM PDT 24
Finished	Jul 12 07:22:21 PM PDT 24
Peak memory	273868 kb
Host	smart-b895c8aa-bd91-446b-a292-601f501def83
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783755020 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_disable.2783755020
Directory	/workspace/43.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/43.flash_ctrl_hw_sec_otp.3490770581
Short name	T1082
Test name
Test status
Simulation time	1767980200 ps
CPU time	88.34 seconds
Started	Jul 12 07:21:54 PM PDT 24
Finished	Jul 12 07:23:28 PM PDT 24
Peak memory	261012 kb
Host	smart-bf02eb68-e299-4410-b637-cac3a70a116b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490770581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_ hw_sec_otp.3490770581
Directory	/workspace/43.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/43.flash_ctrl_otp_reset.2709590537
Short name	T815
Test name
Test status
Simulation time	141445500 ps
CPU time	116.12 seconds
Started	Jul 12 07:21:52 PM PDT 24
Finished	Jul 12 07:23:53 PM PDT 24
Peak memory	261188 kb
Host	smart-19666cf7-9e5a-4754-819f-c1768031216c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709590537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o tp_reset.2709590537
Directory	/workspace/43.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/43.flash_ctrl_sec_info_access.798042225
Short name	T794
Test name
Test status
Simulation time	19358970500 ps
CPU time	89.19 seconds
Started	Jul 12 07:21:51 PM PDT 24
Finished	Jul 12 07:23:26 PM PDT 24
Peak memory	263792 kb
Host	smart-98aca65a-234e-4e05-9ad7-7569575554cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798042225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.798042225
Directory	/workspace/43.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/43.flash_ctrl_smoke.1245606611
Short name	T977
Test name
Test status
Simulation time	16534400 ps
CPU time	49.93 seconds
Started	Jul 12 07:21:50 PM PDT 24
Finished	Jul 12 07:22:46 PM PDT 24
Peak memory	271388 kb
Host	smart-82caaa50-2f19-4ffd-baaa-e4ee461af83c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245606611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1245606611
Directory	/workspace/43.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.flash_ctrl_alert_test.836482427
Short name	T84
Test name
Test status
Simulation time	174990400 ps
CPU time	13.98 seconds
Started	Jul 12 07:22:00 PM PDT 24
Finished	Jul 12 07:22:20 PM PDT 24
Peak memory	265284 kb
Host	smart-b1cd78a0-b5dc-4baa-b139-a4944583c0ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836482427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.836482427
Directory	/workspace/44.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.flash_ctrl_connect.2000922179
Short name	T579
Test name
Test status
Simulation time	15967400 ps
CPU time	15.76 seconds
Started	Jul 12 07:22:01 PM PDT 24
Finished	Jul 12 07:22:22 PM PDT 24
Peak memory	274892 kb
Host	smart-4d01f9a1-53c1-4269-8c73-07eac5d088ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000922179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2000922179
Directory	/workspace/44.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/44.flash_ctrl_disable.272101987
Short name	T344
Test name
Test status
Simulation time	136951400 ps
CPU time	22.19 seconds
Started	Jul 12 07:21:52 PM PDT 24
Finished	Jul 12 07:22:20 PM PDT 24
Peak memory	273512 kb
Host	smart-fa3ab893-72b1-4f01-9aa1-41503e0ae4f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272101987 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_disable.272101987
Directory	/workspace/44.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1732223967
Short name	T873
Test name
Test status
Simulation time	11168663900 ps
CPU time	192.92 seconds
Started	Jul 12 07:21:52 PM PDT 24
Finished	Jul 12 07:25:10 PM PDT 24
Peak memory	260764 kb
Host	smart-053772d1-c79a-47e3-8fa9-a6505d83c0da
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732223967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ hw_sec_otp.1732223967
Directory	/workspace/44.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/44.flash_ctrl_otp_reset.3888769786
Short name	T980
Test name
Test status
Simulation time	38676300 ps
CPU time	132.62 seconds
Started	Jul 12 07:21:53 PM PDT 24
Finished	Jul 12 07:24:11 PM PDT 24
Peak memory	260092 kb
Host	smart-1d11abba-ddae-4d5a-b983-bdbc42350aee
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888769786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o tp_reset.3888769786
Directory	/workspace/44.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/44.flash_ctrl_smoke.1113212032
Short name	T933
Test name
Test status
Simulation time	135439500 ps
CPU time	195.75 seconds
Started	Jul 12 07:21:52 PM PDT 24
Finished	Jul 12 07:25:14 PM PDT 24
Peak memory	278220 kb
Host	smart-42a08023-f02d-4886-8aef-015986f5d22e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113212032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.1113212032
Directory	/workspace/44.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.flash_ctrl_alert_test.2266144781
Short name	T545
Test name
Test status
Simulation time	156794800 ps
CPU time	13.52 seconds
Started	Jul 12 07:21:58 PM PDT 24
Finished	Jul 12 07:22:18 PM PDT 24
Peak memory	265272 kb
Host	smart-b82dbf50-fcce-4cc3-9ef4-99a86a125d98
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266144781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test. 2266144781
Directory	/workspace/45.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.flash_ctrl_connect.591869620
Short name	T1078
Test name
Test status
Simulation time	39427900 ps
CPU time	15.9 seconds
Started	Jul 12 07:22:01 PM PDT 24
Finished	Jul 12 07:22:22 PM PDT 24
Peak memory	284292 kb
Host	smart-50692e98-751d-41e7-8322-60645088b5ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591869620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.591869620
Directory	/workspace/45.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/45.flash_ctrl_disable.3804667746
Short name	T292
Test name
Test status
Simulation time	23940000 ps
CPU time	21.21 seconds
Started	Jul 12 07:21:58 PM PDT 24
Finished	Jul 12 07:22:26 PM PDT 24
Peak memory	273568 kb
Host	smart-63a95283-82d3-4419-9358-3c7d01d9e014
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804667746 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_disable.3804667746
Directory	/workspace/45.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.4140906382
Short name	T296
Test name
Test status
Simulation time	703398200 ps
CPU time	63.96 seconds
Started	Jul 12 07:21:59 PM PDT 24
Finished	Jul 12 07:23:09 PM PDT 24
Peak memory	262132 kb
Host	smart-92172f5c-f1d7-4356-9445-3c3ca5594f24
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140906382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_ hw_sec_otp.4140906382
Directory	/workspace/45.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/45.flash_ctrl_otp_reset.2705277959
Short name	T563
Test name
Test status
Simulation time	77481600 ps
CPU time	110.48 seconds
Started	Jul 12 07:21:59 PM PDT 24
Finished	Jul 12 07:23:56 PM PDT 24
Peak memory	261084 kb
Host	smart-b273bddf-07e5-41a8-ba8f-4b44893381ee
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705277959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o tp_reset.2705277959
Directory	/workspace/45.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/45.flash_ctrl_sec_info_access.1489335001
Short name	T1025
Test name
Test status
Simulation time	6156582400 ps
CPU time	67.99 seconds
Started	Jul 12 07:22:03 PM PDT 24
Finished	Jul 12 07:23:16 PM PDT 24
Peak memory	263124 kb
Host	smart-427a0da4-0de2-4bd3-9c5b-87ff21176b45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489335001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1489335001
Directory	/workspace/45.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/45.flash_ctrl_smoke.186764984
Short name	T53
Test name
Test status
Simulation time	22375500 ps
CPU time	49.12 seconds
Started	Jul 12 07:21:58 PM PDT 24
Finished	Jul 12 07:22:53 PM PDT 24
Peak memory	271232 kb
Host	smart-7922afd2-62ec-4260-85f1-f59a4db5e464
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=186764984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.186764984
Directory	/workspace/45.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.flash_ctrl_alert_test.648051101
Short name	T602
Test name
Test status
Simulation time	107946800 ps
CPU time	13.57 seconds
Started	Jul 12 07:22:10 PM PDT 24
Finished	Jul 12 07:22:29 PM PDT 24
Peak memory	258252 kb
Host	smart-21cd6891-4b60-4f28-9771-2584f6183c43
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648051101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.648051101
Directory	/workspace/46.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.flash_ctrl_connect.373259994
Short name	T1095
Test name
Test status
Simulation time	22034000 ps
CPU time	16.25 seconds
Started	Jul 12 07:22:09 PM PDT 24
Finished	Jul 12 07:22:31 PM PDT 24
Peak memory	274932 kb
Host	smart-07d8e4c2-1f46-443b-be26-d7f56771ea96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373259994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.373259994
Directory	/workspace/46.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/46.flash_ctrl_disable.2111073264
Short name	T875
Test name
Test status
Simulation time	10493300 ps
CPU time	21.9 seconds
Started	Jul 12 07:21:58 PM PDT 24
Finished	Jul 12 07:22:26 PM PDT 24
Peak memory	273652 kb
Host	smart-7600cf1a-9149-45e1-9920-8dc3f4a42241
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111073264 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_disable.2111073264
Directory	/workspace/46.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/46.flash_ctrl_hw_sec_otp.3698535711
Short name	T45
Test name
Test status
Simulation time	86453862300 ps
CPU time	194.73 seconds
Started	Jul 12 07:21:57 PM PDT 24
Finished	Jul 12 07:25:18 PM PDT 24
Peak memory	262836 kb
Host	smart-050a3640-25c6-4a6f-9fb3-227d9227ad35
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698535711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ hw_sec_otp.3698535711
Directory	/workspace/46.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/46.flash_ctrl_otp_reset.63211308
Short name	T1023
Test name
Test status
Simulation time	83940400 ps
CPU time	112.54 seconds
Started	Jul 12 07:21:58 PM PDT 24
Finished	Jul 12 07:23:56 PM PDT 24
Peak memory	259928 kb
Host	smart-55a2821c-5868-42df-8e76-5b6bfeb4f30e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63211308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp _reset.63211308
Directory	/workspace/46.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/46.flash_ctrl_sec_info_access.4086267856
Short name	T550
Test name
Test status
Simulation time	1637425300 ps
CPU time	80.29 seconds
Started	Jul 12 07:22:08 PM PDT 24
Finished	Jul 12 07:23:33 PM PDT 24
Peak memory	259640 kb
Host	smart-1fd8e109-f08c-4368-b75d-313daf9c8133
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086267856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.4086267856
Directory	/workspace/46.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/46.flash_ctrl_smoke.2783833669
Short name	T240
Test name
Test status
Simulation time	71271400 ps
CPU time	190.39 seconds
Started	Jul 12 07:21:57 PM PDT 24
Finished	Jul 12 07:25:14 PM PDT 24
Peak memory	269268 kb
Host	smart-c51235a2-197c-4eea-961c-0a0020c66b50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783833669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.2783833669
Directory	/workspace/46.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.flash_ctrl_alert_test.2576819909
Short name	T762
Test name
Test status
Simulation time	29947300 ps
CPU time	13.72 seconds
Started	Jul 12 07:22:07 PM PDT 24
Finished	Jul 12 07:22:25 PM PDT 24
Peak memory	265200 kb
Host	smart-6b305f6a-8d82-4ea7-865e-b20c27cf63e1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576819909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test. 2576819909
Directory	/workspace/47.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.flash_ctrl_connect.785163526
Short name	T756
Test name
Test status
Simulation time	13701700 ps
CPU time	14.17 seconds
Started	Jul 12 07:22:08 PM PDT 24
Finished	Jul 12 07:22:27 PM PDT 24
Peak memory	284284 kb
Host	smart-8b6646ec-9eff-41fc-a0f3-8fd1505136ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785163526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.785163526
Directory	/workspace/47.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/47.flash_ctrl_disable.2947531238
Short name	T638
Test name
Test status
Simulation time	26426100 ps
CPU time	20.49 seconds
Started	Jul 12 07:22:09 PM PDT 24
Finished	Jul 12 07:22:35 PM PDT 24
Peak memory	273796 kb
Host	smart-3360f3ac-3fd4-4249-8c62-ac657e8a4831
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947531238 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_disable.2947531238
Directory	/workspace/47.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/47.flash_ctrl_hw_sec_otp.2427945958
Short name	T974
Test name
Test status
Simulation time	7547170300 ps
CPU time	167.04 seconds
Started	Jul 12 07:22:07 PM PDT 24
Finished	Jul 12 07:24:59 PM PDT 24
Peak memory	263236 kb
Host	smart-37987aee-b295-4f3d-8560-783dd7ed2441
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427945958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ hw_sec_otp.2427945958
Directory	/workspace/47.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/47.flash_ctrl_otp_reset.1883832474
Short name	T11
Test name
Test status
Simulation time	37674200 ps
CPU time	131.55 seconds
Started	Jul 12 07:22:08 PM PDT 24
Finished	Jul 12 07:24:25 PM PDT 24
Peak memory	260996 kb
Host	smart-c7eb9894-b048-4069-aeca-772527c97465
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883832474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o tp_reset.1883832474
Directory	/workspace/47.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/47.flash_ctrl_sec_info_access.1284509514
Short name	T368
Test name
Test status
Simulation time	2864281700 ps
CPU time	63.32 seconds
Started	Jul 12 07:22:06 PM PDT 24
Finished	Jul 12 07:23:14 PM PDT 24
Peak memory	262724 kb
Host	smart-8d234981-3253-49b6-b6cb-cff0ac1a0e3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284509514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.1284509514
Directory	/workspace/47.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/47.flash_ctrl_smoke.1888735093
Short name	T878
Test name
Test status
Simulation time	41203700 ps
CPU time	99.49 seconds
Started	Jul 12 07:22:07 PM PDT 24
Finished	Jul 12 07:23:51 PM PDT 24
Peak memory	277200 kb
Host	smart-a4ccc33a-c643-4700-9cec-998da1fab948
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888735093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.1888735093
Directory	/workspace/47.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.flash_ctrl_alert_test.2399159924
Short name	T712
Test name
Test status
Simulation time	52669400 ps
CPU time	13.53 seconds
Started	Jul 12 07:22:08 PM PDT 24
Finished	Jul 12 07:22:26 PM PDT 24
Peak memory	265200 kb
Host	smart-9c9f2685-30cd-44b2-a2c1-1cb5eec77abd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399159924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test. 2399159924
Directory	/workspace/48.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.flash_ctrl_connect.2974192631
Short name	T511
Test name
Test status
Simulation time	48480200 ps
CPU time	16.37 seconds
Started	Jul 12 07:22:09 PM PDT 24
Finished	Jul 12 07:22:31 PM PDT 24
Peak memory	274916 kb
Host	smart-cb71a793-ffc0-4856-ad30-f278e4a7e440
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2974192631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2974192631
Directory	/workspace/48.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/48.flash_ctrl_disable.3507099494
Short name	T858
Test name
Test status
Simulation time	29193600 ps
CPU time	21.77 seconds
Started	Jul 12 07:22:08 PM PDT 24
Finished	Jul 12 07:22:35 PM PDT 24
Peak memory	273948 kb
Host	smart-29387dae-87d6-4275-836a-92d4d52c3488
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507099494 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_disable.3507099494
Directory	/workspace/48.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/48.flash_ctrl_hw_sec_otp.589371249
Short name	T614
Test name
Test status
Simulation time	5419757900 ps
CPU time	240.61 seconds
Started	Jul 12 07:22:07 PM PDT 24
Finished	Jul 12 07:26:13 PM PDT 24
Peak memory	263264 kb
Host	smart-fd49d1b9-59e0-4cfa-b15f-17458de8a7fb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589371249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_h w_sec_otp.589371249
Directory	/workspace/48.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/48.flash_ctrl_otp_reset.333768607
Short name	T588
Test name
Test status
Simulation time	161674700 ps
CPU time	134.45 seconds
Started	Jul 12 07:22:07 PM PDT 24
Finished	Jul 12 07:24:26 PM PDT 24
Peak memory	261140 kb
Host	smart-1ae005bc-0d1c-4303-a59e-7fb7c7cc1c0c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333768607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ot p_reset.333768607
Directory	/workspace/48.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/48.flash_ctrl_sec_info_access.1774693215
Short name	T364
Test name
Test status
Simulation time	3321048100 ps
CPU time	66.1 seconds
Started	Jul 12 07:22:10 PM PDT 24
Finished	Jul 12 07:23:22 PM PDT 24
Peak memory	263600 kb
Host	smart-cb99b00a-3cd9-487d-84e3-4785894a7867
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774693215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1774693215
Directory	/workspace/48.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/48.flash_ctrl_smoke.4101493631
Short name	T447
Test name
Test status
Simulation time	24866100 ps
CPU time	144.76 seconds
Started	Jul 12 07:22:10 PM PDT 24
Finished	Jul 12 07:24:41 PM PDT 24
Peak memory	278128 kb
Host	smart-51c9d080-90eb-4ff5-9c57-40bec31be652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4101493631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.4101493631
Directory	/workspace/48.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.flash_ctrl_alert_test.3537098232
Short name	T769
Test name
Test status
Simulation time	48710700 ps
CPU time	14.26 seconds
Started	Jul 12 07:22:15 PM PDT 24
Finished	Jul 12 07:22:35 PM PDT 24
Peak memory	265164 kb
Host	smart-a8041a71-f89d-4067-b20e-ee4c765f3601
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537098232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test. 3537098232
Directory	/workspace/49.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.flash_ctrl_connect.1773856740
Short name	T293
Test name
Test status
Simulation time	16485700 ps
CPU time	16.21 seconds
Started	Jul 12 07:22:16 PM PDT 24
Finished	Jul 12 07:22:38 PM PDT 24
Peak memory	274940 kb
Host	smart-6650135b-925c-4f54-b9ae-2019f738d5ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1773856740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.1773856740
Directory	/workspace/49.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/49.flash_ctrl_disable.106029698
Short name	T343
Test name
Test status
Simulation time	10515300 ps
CPU time	21.86 seconds
Started	Jul 12 07:22:15 PM PDT 24
Finished	Jul 12 07:22:42 PM PDT 24
Peak memory	273604 kb
Host	smart-67c3e28f-7864-4813-b4d5-fcd76dd516ba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106029698 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_disable.106029698
Directory	/workspace/49.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.2528177197
Short name	T303
Test name
Test status
Simulation time	37859562200 ps
CPU time	255.62 seconds
Started	Jul 12 07:22:08 PM PDT 24
Finished	Jul 12 07:26:29 PM PDT 24
Peak memory	263328 kb
Host	smart-cd96cb44-788d-4531-8960-74101d287852
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528177197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ hw_sec_otp.2528177197
Directory	/workspace/49.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/49.flash_ctrl_otp_reset.2286339570
Short name	T830
Test name
Test status
Simulation time	306653300 ps
CPU time	132.24 seconds
Started	Jul 12 07:22:14 PM PDT 24
Finished	Jul 12 07:24:32 PM PDT 24
Peak memory	261024 kb
Host	smart-b561f7a9-afd5-41f6-be5f-cfcfe7f68e5c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286339570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o tp_reset.2286339570
Directory	/workspace/49.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/49.flash_ctrl_sec_info_access.1610472443
Short name	T613
Test name
Test status
Simulation time	1637151600 ps
CPU time	56.69 seconds
Started	Jul 12 07:22:15 PM PDT 24
Finished	Jul 12 07:23:17 PM PDT 24
Peak memory	263752 kb
Host	smart-7afe372c-7189-4edb-9949-40ee16fa3077
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1610472443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.1610472443
Directory	/workspace/49.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/49.flash_ctrl_smoke.664743824
Short name	T925
Test name
Test status
Simulation time	33955500 ps
CPU time	77.91 seconds
Started	Jul 12 07:22:09 PM PDT 24
Finished	Jul 12 07:23:33 PM PDT 24
Peak memory	276696 kb
Host	smart-cb7454ae-89d8-44cc-b6f1-d4d705ae4621
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=664743824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.664743824
Directory	/workspace/49.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_alert_test.1335946507
Short name	T606
Test name
Test status
Simulation time	129242600 ps
CPU time	13.57 seconds
Started	Jul 12 07:12:59 PM PDT 24
Finished	Jul 12 07:13:34 PM PDT 24
Peak memory	265272 kb
Host	smart-107c4a28-f517-485a-a318-677f4ece9ccd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335946507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.1 335946507
Directory	/workspace/5.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.flash_ctrl_connect.3427766933
Short name	T928
Test name
Test status
Simulation time	75887500 ps
CPU time	15.92 seconds
Started	Jul 12 07:12:46 PM PDT 24
Finished	Jul 12 07:13:34 PM PDT 24
Peak memory	284408 kb
Host	smart-fa23a372-b81c-44b4-b186-c104d52f048c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427766933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.3427766933
Directory	/workspace/5.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/5.flash_ctrl_disable.3829547167
Short name	T965
Test name
Test status
Simulation time	16735500 ps
CPU time	21.74 seconds
Started	Jul 12 07:12:50 PM PDT 24
Finished	Jul 12 07:13:41 PM PDT 24
Peak memory	265624 kb
Host	smart-5b3db5bc-b8ae-4290-af36-b9aae2660723
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829547167 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_disable.3829547167
Directory	/workspace/5.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_mp.1552921527
Short name	T235
Test name
Test status
Simulation time	28876700000 ps
CPU time	2268.58 seconds
Started	Jul 12 07:12:31 PM PDT 24
Finished	Jul 12 07:51:02 PM PDT 24
Peak memory	265096 kb
Host	smart-77128e26-64c4-40ba-b201-c0b81b02252a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1552921527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.1552921527
Directory	/workspace/5.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_prog_win.1822044217
Short name	T975
Test name
Test status
Simulation time	992796300 ps
CPU time	745.84 seconds
Started	Jul 12 07:12:30 PM PDT 24
Finished	Jul 12 07:25:39 PM PDT 24
Peak memory	264824 kb
Host	smart-790f8a6c-1211-426a-8e2e-8b7b81f7f231
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1822044217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1822044217
Directory	/workspace/5.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/5.flash_ctrl_fetch_code.2279071290
Short name	T56
Test name
Test status
Simulation time	899819500 ps
CPU time	25.35 seconds
Started	Jul 12 07:12:30 PM PDT 24
Finished	Jul 12 07:13:39 PM PDT 24
Peak memory	262600 kb
Host	smart-9c438ae8-ad8c-42b6-bf3d-c957cd71d5db
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279071290 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.2279071290
Directory	/workspace/5.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2524496140
Short name	T716
Test name
Test status
Simulation time	10014863600 ps
CPU time	109.27 seconds
Started	Jul 12 07:12:53 PM PDT 24
Finished	Jul 12 07:15:09 PM PDT 24
Peak memory	342588 kb
Host	smart-a47cca21-cb78-4327-a529-a1fd1d99c497
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524496140 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.2524496140
Directory	/workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.1510085431
Short name	T147
Test name
Test status
Simulation time	49107000 ps
CPU time	13.43 seconds
Started	Jul 12 07:12:46 PM PDT 24
Finished	Jul 12 07:13:31 PM PDT 24
Peak memory	265064 kb
Host	smart-7e184a86-e1f1-49f9-bb90-a658831bb45d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510085431 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1510085431
Directory	/workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_rma_reset.832878027
Short name	T789
Test name
Test status
Simulation time	50125797300 ps
CPU time	884.94 seconds
Started	Jul 12 07:12:30 PM PDT 24
Finished	Jul 12 07:27:58 PM PDT 24
Peak memory	260948 kb
Host	smart-e79c1206-b811-4660-ba23-debc4c8114a0
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832878027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.flash_ctrl_hw_rma_reset.832878027
Directory	/workspace/5.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd.4010119517
Short name	T867
Test name
Test status
Simulation time	4927984700 ps
CPU time	261.43 seconds
Started	Jul 12 07:12:38 PM PDT 24
Finished	Jul 12 07:17:37 PM PDT 24
Peak memory	284976 kb
Host	smart-97b26c92-b418-4085-bf06-5ddf2b5108c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010119517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_intr_rd.4010119517
Directory	/workspace/5.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.23449632
Short name	T311
Test name
Test status
Simulation time	34469125100 ps
CPU time	301.61 seconds
Started	Jul 12 07:12:35 PM PDT 24
Finished	Jul 12 07:18:17 PM PDT 24
Peak memory	294068 kb
Host	smart-7c72901d-82bf-4a08-9e62-4c1e603611e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23449632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.23449632
Directory	/workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr.110167598
Short name	T675
Test name
Test status
Simulation time	5257268900 ps
CPU time	67.94 seconds
Started	Jul 12 07:12:37 PM PDT 24
Finished	Jul 12 07:14:24 PM PDT 24
Peak memory	265168 kb
Host	smart-e5635def-bb18-4e00-801d-5196f5aa5db5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110167598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 5.flash_ctrl_intr_wr.110167598
Directory	/workspace/5.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.4174064722
Short name	T848
Test name
Test status
Simulation time	92046957400 ps
CPU time	216.71 seconds
Started	Jul 12 07:12:37 PM PDT 24
Finished	Jul 12 07:16:53 PM PDT 24
Peak memory	259872 kb
Host	smart-61df4783-6fec-477f-858e-56712641cc94
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417 4064722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.4174064722
Directory	/workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_invalid_op.1197138156
Short name	T623
Test name
Test status
Simulation time	2082880800 ps
CPU time	66.65 seconds
Started	Jul 12 07:12:30 PM PDT 24
Finished	Jul 12 07:14:20 PM PDT 24
Peak memory	260592 kb
Host	smart-04ffb974-45d5-456c-9db1-fd57e35915e4
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197138156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1197138156
Directory	/workspace/5.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/5.flash_ctrl_lcmgr_intg.445317676
Short name	T682
Test name
Test status
Simulation time	51309500 ps
CPU time	13.6 seconds
Started	Jul 12 07:12:46 PM PDT 24
Finished	Jul 12 07:13:32 PM PDT 24
Peak memory	265008 kb
Host	smart-d28d53c9-75d6-47f0-93bb-86006529cd32
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445317676 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.445317676
Directory	/workspace/5.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/5.flash_ctrl_mp_regions.1743277588
Short name	T728
Test name
Test status
Simulation time	22940158600 ps
CPU time	476.35 seconds
Started	Jul 12 07:12:30 PM PDT 24
Finished	Jul 12 07:21:10 PM PDT 24
Peak memory	274360 kb
Host	smart-880f0d31-51aa-4aa1-9b56-22dacd6df763
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743277588 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.1743277588
Directory	/workspace/5.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/5.flash_ctrl_otp_reset.3434812548
Short name	T1050
Test name
Test status
Simulation time	66535300 ps
CPU time	112.48 seconds
Started	Jul 12 07:12:29 PM PDT 24
Finished	Jul 12 07:15:06 PM PDT 24
Peak memory	260124 kb
Host	smart-96cf29c0-2662-429a-9174-552634a034f8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434812548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot p_reset.3434812548
Directory	/workspace/5.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_phy_arb.4061792472
Short name	T619
Test name
Test status
Simulation time	61208300 ps
CPU time	233.21 seconds
Started	Jul 12 07:12:24 PM PDT 24
Finished	Jul 12 07:17:04 PM PDT 24
Peak memory	263240 kb
Host	smart-c4420c8e-41a5-41f3-b4d1-6e2aab231a97
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4061792472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.4061792472
Directory	/workspace/5.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/5.flash_ctrl_prog_reset.4172707253
Short name	T578
Test name
Test status
Simulation time	80733000 ps
CPU time	13.99 seconds
Started	Jul 12 07:12:47 PM PDT 24
Finished	Jul 12 07:13:33 PM PDT 24
Peak memory	265248 kb
Host	smart-1f816ec2-c2e9-4ff2-be60-1fd8b8270c28
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172707253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.flash_ctrl_prog_reset.4172707253
Directory	/workspace/5.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rand_ops.1536493568
Short name	T590
Test name
Test status
Simulation time	105083300 ps
CPU time	590.88 seconds
Started	Jul 12 07:12:25 PM PDT 24
Finished	Jul 12 07:23:04 PM PDT 24
Peak memory	284672 kb
Host	smart-0819c8be-193b-4868-97ca-de0fa50e6e88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536493568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.1536493568
Directory	/workspace/5.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/5.flash_ctrl_re_evict.3521703602
Short name	T635
Test name
Test status
Simulation time	138893600 ps
CPU time	34.81 seconds
Started	Jul 12 07:12:45 PM PDT 24
Finished	Jul 12 07:13:52 PM PDT 24
Peak memory	275616 kb
Host	smart-8526818d-91bd-40d1-9e22-49391b8aed51
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521703602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_re_evict.3521703602
Directory	/workspace/5.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro.2630630901
Short name	T1093
Test name
Test status
Simulation time	1065792200 ps
CPU time	111.47 seconds
Started	Jul 12 07:12:37 PM PDT 24
Finished	Jul 12 07:15:07 PM PDT 24
Peak memory	280880 kb
Host	smart-fc09833b-5390-44df-b023-7c8e94cd4761
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630630901 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_ro.2630630901
Directory	/workspace/5.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_serr.3423874327
Short name	T36
Test name
Test status
Simulation time	652528000 ps
CPU time	159.22 seconds
Started	Jul 12 07:12:38 PM PDT 24
Finished	Jul 12 07:15:54 PM PDT 24
Peak memory	295276 kb
Host	smart-91905dd9-aa72-4a6b-bf36-325db2465732
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423874327 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3423874327
Directory	/workspace/5.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw.2767925343
Short name	T691
Test name
Test status
Simulation time	4019781200 ps
CPU time	691.75 seconds
Started	Jul 12 07:12:39 PM PDT 24
Finished	Jul 12 07:24:47 PM PDT 24
Peak memory	310856 kb
Host	smart-1101c50b-08de-48c5-8edf-5aa6626385af
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767925343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.flash_ctrl_rw.2767925343
Directory	/workspace/5.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict.2020251611
Short name	T1042
Test name
Test status
Simulation time	40392900 ps
CPU time	28.03 seconds
Started	Jul 12 07:12:46 PM PDT 24
Finished	Jul 12 07:13:47 PM PDT 24
Peak memory	267524 kb
Host	smart-b4a99772-b3d2-4642-9ca4-a65893460108
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020251611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_rw_evict.2020251611
Directory	/workspace/5.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3480405077
Short name	T743
Test name
Test status
Simulation time	59085900 ps
CPU time	31.12 seconds
Started	Jul 12 07:12:45 PM PDT 24
Finished	Jul 12 07:13:49 PM PDT 24
Peak memory	275624 kb
Host	smart-192cdcca-845a-4b8b-b3c9-d75e23b2fe23
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480405077 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.3480405077
Directory	/workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_serr.3416681269
Short name	T854
Test name
Test status
Simulation time	11680116100 ps
CPU time	626.27 seconds
Started	Jul 12 07:12:36 PM PDT 24
Finished	Jul 12 07:23:42 PM PDT 24
Peak memory	312920 kb
Host	smart-2dde1946-55e9-47ea-8a94-d4a99d84be16
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416681269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s err.3416681269
Directory	/workspace/5.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_sec_info_access.2898361731
Short name	T726
Test name
Test status
Simulation time	4006545100 ps
CPU time	81.23 seconds
Started	Jul 12 07:12:46 PM PDT 24
Finished	Jul 12 07:14:39 PM PDT 24
Peak memory	263000 kb
Host	smart-7a8b0bf5-c177-4f35-8bd8-12f1475cef4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2898361731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.2898361731
Directory	/workspace/5.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/5.flash_ctrl_smoke.2909511754
Short name	T696
Test name
Test status
Simulation time	104786000 ps
CPU time	95.56 seconds
Started	Jul 12 07:12:22 PM PDT 24
Finished	Jul 12 07:14:45 PM PDT 24
Peak memory	276252 kb
Host	smart-65a45092-d346-4a74-ae9f-f5a47b4524c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909511754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2909511754
Directory	/workspace/5.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_wo.163753443
Short name	T135
Test name
Test status
Simulation time	4760200200 ps
CPU time	159.97 seconds
Started	Jul 12 07:12:33 PM PDT 24
Finished	Jul 12 07:15:55 PM PDT 24
Peak memory	265292 kb
Host	smart-4fce1b6a-8049-4d20-8305-8e18d435999a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163753443 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 5.flash_ctrl_wo.163753443
Directory	/workspace/5.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/50.flash_ctrl_connect.20769713
Short name	T609
Test name
Test status
Simulation time	28855300 ps
CPU time	16.09 seconds
Started	Jul 12 07:22:14 PM PDT 24
Finished	Jul 12 07:22:36 PM PDT 24
Peak memory	284300 kb
Host	smart-d75b2c8d-6a7f-4c43-8d46-cf92d47537e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=20769713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.20769713
Directory	/workspace/50.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/50.flash_ctrl_otp_reset.1513609554
Short name	T909
Test name
Test status
Simulation time	116794400 ps
CPU time	134.34 seconds
Started	Jul 12 07:22:16 PM PDT 24
Finished	Jul 12 07:24:36 PM PDT 24
Peak memory	261072 kb
Host	smart-2103cf6d-3352-4363-ae7c-792abd0f91c4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513609554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o tp_reset.1513609554
Directory	/workspace/50.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/51.flash_ctrl_connect.723629027
Short name	T539
Test name
Test status
Simulation time	46403900 ps
CPU time	13.31 seconds
Started	Jul 12 07:22:16 PM PDT 24
Finished	Jul 12 07:22:35 PM PDT 24
Peak memory	274944 kb
Host	smart-4a0011e8-4d2f-4196-b0ff-d48b7ee42906
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=723629027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.723629027
Directory	/workspace/51.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/51.flash_ctrl_otp_reset.2215676960
Short name	T649
Test name
Test status
Simulation time	67854000 ps
CPU time	114.83 seconds
Started	Jul 12 07:22:15 PM PDT 24
Finished	Jul 12 07:24:15 PM PDT 24
Peak memory	260004 kb
Host	smart-b06ee6b0-65ba-4932-a4e2-0e16cf59ddd2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215676960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o tp_reset.2215676960
Directory	/workspace/51.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/52.flash_ctrl_connect.292966285
Short name	T410
Test name
Test status
Simulation time	15118500 ps
CPU time	13.32 seconds
Started	Jul 12 07:22:23 PM PDT 24
Finished	Jul 12 07:22:40 PM PDT 24
Peak memory	284340 kb
Host	smart-f06e558e-04ee-4c1b-9ab9-776c74ab5dc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292966285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.292966285
Directory	/workspace/52.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/52.flash_ctrl_otp_reset.506954052
Short name	T787
Test name
Test status
Simulation time	305314100 ps
CPU time	111.34 seconds
Started	Jul 12 07:22:15 PM PDT 24
Finished	Jul 12 07:24:12 PM PDT 24
Peak memory	259992 kb
Host	smart-ed3d76a8-03cc-438d-a61c-4f175be6ef09
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506954052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_ot p_reset.506954052
Directory	/workspace/52.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/53.flash_ctrl_connect.1743423597
Short name	T428
Test name
Test status
Simulation time	28147600 ps
CPU time	14.19 seconds
Started	Jul 12 07:22:25 PM PDT 24
Finished	Jul 12 07:22:43 PM PDT 24
Peak memory	274996 kb
Host	smart-1be0306f-7bdb-4d43-bede-6257d7e2590e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1743423597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1743423597
Directory	/workspace/53.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/53.flash_ctrl_otp_reset.935334466
Short name	T161
Test name
Test status
Simulation time	51825200 ps
CPU time	109.5 seconds
Started	Jul 12 07:22:24 PM PDT 24
Finished	Jul 12 07:24:16 PM PDT 24
Peak memory	260000 kb
Host	smart-e73693cc-66e3-41fc-884c-f2d48c65449b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935334466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot p_reset.935334466
Directory	/workspace/53.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/54.flash_ctrl_connect.2321478332
Short name	T558
Test name
Test status
Simulation time	26103100 ps
CPU time	13.34 seconds
Started	Jul 12 07:22:27 PM PDT 24
Finished	Jul 12 07:22:44 PM PDT 24
Peak memory	284236 kb
Host	smart-f8789c85-186c-4ca5-935e-7d250b6c8328
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321478332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.2321478332
Directory	/workspace/54.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/54.flash_ctrl_otp_reset.3107742505
Short name	T160
Test name
Test status
Simulation time	73241300 ps
CPU time	110.99 seconds
Started	Jul 12 07:22:26 PM PDT 24
Finished	Jul 12 07:24:21 PM PDT 24
Peak memory	264404 kb
Host	smart-83ea9194-2082-4884-a2c4-29f473791335
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107742505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o tp_reset.3107742505
Directory	/workspace/54.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/55.flash_ctrl_connect.945489037
Short name	T663
Test name
Test status
Simulation time	45848700 ps
CPU time	13.54 seconds
Started	Jul 12 07:22:23 PM PDT 24
Finished	Jul 12 07:22:40 PM PDT 24
Peak memory	274936 kb
Host	smart-c0474d16-86a6-4b0c-a607-72731642c36c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945489037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.945489037
Directory	/workspace/55.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/56.flash_ctrl_connect.4253228761
Short name	T572
Test name
Test status
Simulation time	47181100 ps
CPU time	16.15 seconds
Started	Jul 12 07:22:23 PM PDT 24
Finished	Jul 12 07:22:42 PM PDT 24
Peak memory	274884 kb
Host	smart-f45e3caf-f8cb-404b-a51b-1a185e043503
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253228761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.4253228761
Directory	/workspace/56.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/56.flash_ctrl_otp_reset.621298857
Short name	T763
Test name
Test status
Simulation time	38023500 ps
CPU time	131.59 seconds
Started	Jul 12 07:22:22 PM PDT 24
Finished	Jul 12 07:24:37 PM PDT 24
Peak memory	260352 kb
Host	smart-6d3695c9-cdc1-45c7-8dcb-f7bc7eec0610
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621298857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_ot p_reset.621298857
Directory	/workspace/56.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/57.flash_ctrl_connect.2362566035
Short name	T797
Test name
Test status
Simulation time	27064900 ps
CPU time	15.76 seconds
Started	Jul 12 07:22:25 PM PDT 24
Finished	Jul 12 07:22:44 PM PDT 24
Peak memory	284548 kb
Host	smart-67583c56-41ae-431d-a1fe-2120551f91f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362566035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.2362566035
Directory	/workspace/57.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/57.flash_ctrl_otp_reset.2145287494
Short name	T152
Test name
Test status
Simulation time	92212000 ps
CPU time	130.01 seconds
Started	Jul 12 07:22:27 PM PDT 24
Finished	Jul 12 07:24:41 PM PDT 24
Peak memory	259928 kb
Host	smart-5f92a1b4-445d-496b-8f3f-1d9930605166
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145287494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o tp_reset.2145287494
Directory	/workspace/57.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/58.flash_ctrl_connect.1254302383
Short name	T457
Test name
Test status
Simulation time	13836100 ps
CPU time	13.45 seconds
Started	Jul 12 07:22:23 PM PDT 24
Finished	Jul 12 07:22:40 PM PDT 24
Peak memory	284236 kb
Host	smart-62ba3393-92e4-4465-ba56-595447e14741
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1254302383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1254302383
Directory	/workspace/58.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/58.flash_ctrl_otp_reset.3417643538
Short name	T1091
Test name
Test status
Simulation time	86313800 ps
CPU time	131.68 seconds
Started	Jul 12 07:22:24 PM PDT 24
Finished	Jul 12 07:24:39 PM PDT 24
Peak memory	264500 kb
Host	smart-ed9113d2-20d3-4f66-8efb-3980901bf3bf
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417643538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o tp_reset.3417643538
Directory	/workspace/58.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/59.flash_ctrl_connect.2099481279
Short name	T950
Test name
Test status
Simulation time	37539200 ps
CPU time	16.32 seconds
Started	Jul 12 07:22:22 PM PDT 24
Finished	Jul 12 07:22:41 PM PDT 24
Peak memory	284284 kb
Host	smart-b4c1cf87-820f-42bd-8f13-206e3efbc998
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099481279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2099481279
Directory	/workspace/59.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/59.flash_ctrl_otp_reset.1888899702
Short name	T1006
Test name
Test status
Simulation time	41691700 ps
CPU time	109.02 seconds
Started	Jul 12 07:22:26 PM PDT 24
Finished	Jul 12 07:24:19 PM PDT 24
Peak memory	261068 kb
Host	smart-faa324f5-f8a6-4470-b94b-4bfb0ecd0d9c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888899702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o tp_reset.1888899702
Directory	/workspace/59.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_alert_test.2422252722
Short name	T923
Test name
Test status
Simulation time	154228600 ps
CPU time	13.8 seconds
Started	Jul 12 07:13:44 PM PDT 24
Finished	Jul 12 07:14:05 PM PDT 24
Peak memory	265212 kb
Host	smart-0edead48-b293-4711-9ba1-7b0197c89838
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422252722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.2 422252722
Directory	/workspace/6.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.flash_ctrl_connect.4155884348
Short name	T751
Test name
Test status
Simulation time	14230300 ps
CPU time	16.52 seconds
Started	Jul 12 07:13:38 PM PDT 24
Finished	Jul 12 07:13:58 PM PDT 24
Peak memory	284384 kb
Host	smart-9be593ef-67ce-457c-8a4e-68a3fd78f98c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4155884348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.4155884348
Directory	/workspace/6.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/6.flash_ctrl_disable.1599546809
Short name	T893
Test name
Test status
Simulation time	17006900 ps
CPU time	21.78 seconds
Started	Jul 12 07:13:29 PM PDT 24
Finished	Jul 12 07:13:54 PM PDT 24
Peak memory	273576 kb
Host	smart-da7a7d40-cd34-4caf-b35e-d4f9bd7ffa61
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599546809 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_disable.1599546809
Directory	/workspace/6.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_mp.368275532
Short name	T901
Test name
Test status
Simulation time	16068639300 ps
CPU time	2222.81 seconds
Started	Jul 12 07:13:00 PM PDT 24
Finished	Jul 12 07:50:25 PM PDT 24
Peak memory	262908 kb
Host	smart-4f9741c4-2f4c-4191-829b-683434f58da5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=368275532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.368275532
Directory	/workspace/6.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_prog_win.3508130965
Short name	T701
Test name
Test status
Simulation time	350204600 ps
CPU time	836.73 seconds
Started	Jul 12 07:13:01 PM PDT 24
Finished	Jul 12 07:27:19 PM PDT 24
Peak memory	273368 kb
Host	smart-10400b15-b7c1-48f3-b998-81a7da698bec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3508130965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.3508130965
Directory	/workspace/6.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/6.flash_ctrl_fetch_code.1865845127
Short name	T964
Test name
Test status
Simulation time	6955976800 ps
CPU time	26.68 seconds
Started	Jul 12 07:13:01 PM PDT 24
Finished	Jul 12 07:13:49 PM PDT 24
Peak memory	262720 kb
Host	smart-2c34d480-beb2-4bea-ab55-335f82ff4282
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865845127 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.1865845127
Directory	/workspace/6.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2874088081
Short name	T1062
Test name
Test status
Simulation time	10034841400 ps
CPU time	104.2 seconds
Started	Jul 12 07:13:44 PM PDT 24
Finished	Jul 12 07:15:35 PM PDT 24
Peak memory	274760 kb
Host	smart-fef1a43f-545f-4883-a68a-12e94cd7a833
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874088081 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.2874088081
Directory	/workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.3581003159
Short name	T785
Test name
Test status
Simulation time	25885400 ps
CPU time	13.51 seconds
Started	Jul 12 07:13:40 PM PDT 24
Finished	Jul 12 07:13:56 PM PDT 24
Peak memory	265412 kb
Host	smart-5b28d313-55e1-4ab0-b8a9-aac6f0058112
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581003159 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.3581003159
Directory	/workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_rma_reset.4105205043
Short name	T107
Test name
Test status
Simulation time	40120724900 ps
CPU time	821.81 seconds
Started	Jul 12 07:13:00 PM PDT 24
Finished	Jul 12 07:27:03 PM PDT 24
Peak memory	260936 kb
Host	smart-8f8cfbd9-42c5-4b93-8372-b9d2397c472a
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105205043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.flash_ctrl_hw_rma_reset.4105205043
Directory	/workspace/6.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_sec_otp.3257919213
Short name	T687
Test name
Test status
Simulation time	1565753400 ps
CPU time	121.25 seconds
Started	Jul 12 07:13:05 PM PDT 24
Finished	Jul 12 07:15:24 PM PDT 24
Peak memory	263264 kb
Host	smart-ccc9c4cc-febb-4bb2-b983-0a3575dbb934
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257919213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h w_sec_otp.3257919213
Directory	/workspace/6.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd.766456779
Short name	T561
Test name
Test status
Simulation time	1599224700 ps
CPU time	150.51 seconds
Started	Jul 12 07:13:17 PM PDT 24
Finished	Jul 12 07:15:58 PM PDT 24
Peak memory	291388 kb
Host	smart-f6951fb9-306e-46d9-bd97-688fa8e93324
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766456779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash _ctrl_intr_rd.766456779
Directory	/workspace/6.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3448387751
Short name	T582
Test name
Test status
Simulation time	12566411600 ps
CPU time	266.44 seconds
Started	Jul 12 07:13:23 PM PDT 24
Finished	Jul 12 07:17:56 PM PDT 24
Peak memory	289912 kb
Host	smart-6a0eb565-09cc-44c1-a340-a2944d72ff57
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448387751 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.3448387751
Directory	/workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr.1645915798
Short name	T809
Test name
Test status
Simulation time	5848764900 ps
CPU time	87.67 seconds
Started	Jul 12 07:13:21 PM PDT 24
Finished	Jul 12 07:14:56 PM PDT 24
Peak memory	265276 kb
Host	smart-4820d5f6-c7fd-4911-a6de-c98982716dbb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645915798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.flash_ctrl_intr_wr.1645915798
Directory	/workspace/6.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2087411880
Short name	T449
Test name
Test status
Simulation time	24991347400 ps
CPU time	194.33 seconds
Started	Jul 12 07:13:24 PM PDT 24
Finished	Jul 12 07:16:44 PM PDT 24
Peak memory	259888 kb
Host	smart-8aa8e514-0968-4406-b7a1-33445f79363c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208 7411880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2087411880
Directory	/workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_invalid_op.693538092
Short name	T378
Test name
Test status
Simulation time	19341318900 ps
CPU time	92.78 seconds
Started	Jul 12 07:13:09 PM PDT 24
Finished	Jul 12 07:14:57 PM PDT 24
Peak memory	260816 kb
Host	smart-72fe13f0-f08c-4d87-9321-bf8711ff0052
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693538092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.693538092
Directory	/workspace/6.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/6.flash_ctrl_lcmgr_intg.2503923864
Short name	T811
Test name
Test status
Simulation time	30559900 ps
CPU time	13.53 seconds
Started	Jul 12 07:13:41 PM PDT 24
Finished	Jul 12 07:13:56 PM PDT 24
Peak memory	260868 kb
Host	smart-89e5dad8-1923-4e25-87d3-e681f0b16983
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503923864 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.2503923864
Directory	/workspace/6.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/6.flash_ctrl_mp_regions.3515056181
Short name	T936
Test name
Test status
Simulation time	4776646200 ps
CPU time	160.13 seconds
Started	Jul 12 07:13:01 PM PDT 24
Finished	Jul 12 07:16:03 PM PDT 24
Peak memory	265128 kb
Host	smart-65150bd5-d0fe-4823-8694-e2260befe876
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515056181 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.3515056181
Directory	/workspace/6.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/6.flash_ctrl_otp_reset.4139326621
Short name	T604
Test name
Test status
Simulation time	41486700 ps
CPU time	131.18 seconds
Started	Jul 12 07:13:00 PM PDT 24
Finished	Jul 12 07:15:33 PM PDT 24
Peak memory	259952 kb
Host	smart-d1d2bba3-27a2-4904-9068-a03620a28289
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139326621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot p_reset.4139326621
Directory	/workspace/6.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_phy_arb.1393484940
Short name	T1007
Test name
Test status
Simulation time	53471100 ps
CPU time	280.85 seconds
Started	Jul 12 07:12:53 PM PDT 24
Finished	Jul 12 07:18:01 PM PDT 24
Peak memory	263204 kb
Host	smart-f9b8d8bf-7f86-4e8b-b982-15ebcd9e4e31
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1393484940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.1393484940
Directory	/workspace/6.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/6.flash_ctrl_prog_reset.3893775185
Short name	T407
Test name
Test status
Simulation time	53440900 ps
CPU time	13.86 seconds
Started	Jul 12 07:13:24 PM PDT 24
Finished	Jul 12 07:13:44 PM PDT 24
Peak memory	259624 kb
Host	smart-aee8090f-a883-4b75-a173-3867c7db5431
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893775185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.flash_ctrl_prog_reset.3893775185
Directory	/workspace/6.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rand_ops.3179289024
Short name	T562
Test name
Test status
Simulation time	72964400 ps
CPU time	276.39 seconds
Started	Jul 12 07:12:51 PM PDT 24
Finished	Jul 12 07:17:56 PM PDT 24
Peak memory	281612 kb
Host	smart-7925532f-f492-49c1-acbb-80830756d606
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3179289024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.3179289024
Directory	/workspace/6.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/6.flash_ctrl_re_evict.451299945
Short name	T395
Test name
Test status
Simulation time	79976600 ps
CPU time	34.78 seconds
Started	Jul 12 07:13:31 PM PDT 24
Finished	Jul 12 07:14:08 PM PDT 24
Peak memory	275672 kb
Host	smart-7870a028-dedb-4ffa-9637-ac8c47dd314c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451299945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_re_evict.451299945
Directory	/workspace/6.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro.649069919
Short name	T608
Test name
Test status
Simulation time	1785903600 ps
CPU time	117.32 seconds
Started	Jul 12 07:13:08 PM PDT 24
Finished	Jul 12 07:15:22 PM PDT 24
Peak memory	289916 kb
Host	smart-361d4988-6edf-44de-a089-2673429b2485
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649069919 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.flash_ctrl_ro.649069919
Directory	/workspace/6.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_derr.3658916402
Short name	T1060
Test name
Test status
Simulation time	888190400 ps
CPU time	166.09 seconds
Started	Jul 12 07:13:13 PM PDT 24
Finished	Jul 12 07:16:12 PM PDT 24
Peak memory	281828 kb
Host	smart-7e30d43e-a3b1-4e0d-9f4b-ff1d06d94ba6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3658916402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.3658916402
Directory	/workspace/6.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_serr.636988686
Short name	T969
Test name
Test status
Simulation time	801086300 ps
CPU time	155.72 seconds
Started	Jul 12 07:13:08 PM PDT 24
Finished	Jul 12 07:16:00 PM PDT 24
Peak memory	281836 kb
Host	smart-1ebce187-b4ae-4ba0-882e-50d779d6ec79
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636988686 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.636988686
Directory	/workspace/6.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw.2128020367
Short name	T203
Test name
Test status
Simulation time	6314996000 ps
CPU time	419.15 seconds
Started	Jul 12 07:13:08 PM PDT 24
Finished	Jul 12 07:20:24 PM PDT 24
Peak memory	314080 kb
Host	smart-ad3a5d7f-7711-4dab-ae44-fe7b20e6db4e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128020367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.flash_ctrl_rw.2128020367
Directory	/workspace/6.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.405030900
Short name	T37
Test name
Test status
Simulation time	28056400 ps
CPU time	30.42 seconds
Started	Jul 12 07:13:21 PM PDT 24
Finished	Jul 12 07:13:59 PM PDT 24
Peak memory	273620 kb
Host	smart-f7bf5db0-b45a-440f-8461-e4631f56307f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405030900 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.405030900
Directory	/workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/6.flash_ctrl_sec_info_access.326218879
Short name	T185
Test name
Test status
Simulation time	680529400 ps
CPU time	77.17 seconds
Started	Jul 12 07:13:39 PM PDT 24
Finished	Jul 12 07:14:59 PM PDT 24
Peak memory	264744 kb
Host	smart-3db50c52-515b-4f9d-9dc0-0174c8186481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326218879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.326218879
Directory	/workspace/6.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/6.flash_ctrl_smoke.759952820
Short name	T607
Test name
Test status
Simulation time	42703700 ps
CPU time	76.81 seconds
Started	Jul 12 07:13:00 PM PDT 24
Finished	Jul 12 07:14:39 PM PDT 24
Peak memory	276824 kb
Host	smart-578c1fa1-3585-415d-8d93-ea541f548fbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759952820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.759952820
Directory	/workspace/6.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.flash_ctrl_wo.2591313329
Short name	T610
Test name
Test status
Simulation time	1694018300 ps
CPU time	129.82 seconds
Started	Jul 12 07:13:10 PM PDT 24
Finished	Jul 12 07:15:35 PM PDT 24
Peak memory	260008 kb
Host	smart-ce9b540a-0557-4c27-a302-5a09922d8f10
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591313329 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.flash_ctrl_wo.2591313329
Directory	/workspace/6.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/60.flash_ctrl_connect.832837630
Short name	T612
Test name
Test status
Simulation time	17140600 ps
CPU time	13.56 seconds
Started	Jul 12 07:22:29 PM PDT 24
Finished	Jul 12 07:22:46 PM PDT 24
Peak memory	274804 kb
Host	smart-dffe766b-ee29-43bb-91d6-4ee4c8753ee8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832837630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.832837630
Directory	/workspace/60.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/60.flash_ctrl_otp_reset.2269455249
Short name	T552
Test name
Test status
Simulation time	47738900 ps
CPU time	131.73 seconds
Started	Jul 12 07:22:22 PM PDT 24
Finished	Jul 12 07:24:36 PM PDT 24
Peak memory	261104 kb
Host	smart-1313bab2-41e1-4688-9563-0327ed46a082
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269455249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o tp_reset.2269455249
Directory	/workspace/60.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/61.flash_ctrl_connect.2941834265
Short name	T345
Test name
Test status
Simulation time	24235700 ps
CPU time	16 seconds
Started	Jul 12 07:22:28 PM PDT 24
Finished	Jul 12 07:22:47 PM PDT 24
Peak memory	274860 kb
Host	smart-8985dd49-efb2-477a-ba31-1abd1876c54f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2941834265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.2941834265
Directory	/workspace/61.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/61.flash_ctrl_otp_reset.4033196217
Short name	T981
Test name
Test status
Simulation time	39769800 ps
CPU time	110.19 seconds
Started	Jul 12 07:22:23 PM PDT 24
Finished	Jul 12 07:24:16 PM PDT 24
Peak memory	264828 kb
Host	smart-c28bb47d-267c-4cbe-9ef0-e5616a8270dd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033196217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o tp_reset.4033196217
Directory	/workspace/61.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/62.flash_ctrl_connect.661496490
Short name	T1090
Test name
Test status
Simulation time	52267500 ps
CPU time	15.67 seconds
Started	Jul 12 07:22:22 PM PDT 24
Finished	Jul 12 07:22:41 PM PDT 24
Peak memory	274852 kb
Host	smart-22830e7c-5fbd-4b4c-848c-73970daeb737
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=661496490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.661496490
Directory	/workspace/62.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/62.flash_ctrl_otp_reset.3474808698
Short name	T961
Test name
Test status
Simulation time	540399900 ps
CPU time	132.06 seconds
Started	Jul 12 07:22:22 PM PDT 24
Finished	Jul 12 07:24:37 PM PDT 24
Peak memory	264860 kb
Host	smart-d1f4a5c4-bbb5-4de9-82a0-c893b1be0b50
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474808698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o tp_reset.3474808698
Directory	/workspace/62.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/63.flash_ctrl_connect.3370721848
Short name	T883
Test name
Test status
Simulation time	13800800 ps
CPU time	13.44 seconds
Started	Jul 12 07:22:31 PM PDT 24
Finished	Jul 12 07:22:50 PM PDT 24
Peak memory	284264 kb
Host	smart-d2d6a2be-6958-47dc-b54d-ba65cc6cfa4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370721848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.3370721848
Directory	/workspace/63.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/63.flash_ctrl_otp_reset.3047152377
Short name	T349
Test name
Test status
Simulation time	140874400 ps
CPU time	109.26 seconds
Started	Jul 12 07:22:23 PM PDT 24
Finished	Jul 12 07:24:15 PM PDT 24
Peak memory	260088 kb
Host	smart-2c2ef6e0-1040-47ce-878b-fb7aa73fab83
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047152377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o tp_reset.3047152377
Directory	/workspace/63.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/64.flash_ctrl_connect.4196087649
Short name	T477
Test name
Test status
Simulation time	13861100 ps
CPU time	16.53 seconds
Started	Jul 12 07:22:34 PM PDT 24
Finished	Jul 12 07:22:55 PM PDT 24
Peak memory	284280 kb
Host	smart-c5804ebf-da73-4297-8470-307541fdb176
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4196087649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.4196087649
Directory	/workspace/64.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/64.flash_ctrl_otp_reset.2954800112
Short name	T676
Test name
Test status
Simulation time	134738300 ps
CPU time	133.3 seconds
Started	Jul 12 07:22:31 PM PDT 24
Finished	Jul 12 07:24:49 PM PDT 24
Peak memory	260012 kb
Host	smart-ba2bc177-c9fb-4739-8cbb-72fe60dcc0fc
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954800112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o tp_reset.2954800112
Directory	/workspace/64.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/65.flash_ctrl_otp_reset.4268766273
Short name	T798
Test name
Test status
Simulation time	71450000 ps
CPU time	132.26 seconds
Started	Jul 12 07:22:33 PM PDT 24
Finished	Jul 12 07:24:50 PM PDT 24
Peak memory	260100 kb
Host	smart-00e0c709-ea3b-451e-8fce-a5bbd1ea8686
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268766273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o tp_reset.4268766273
Directory	/workspace/65.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/66.flash_ctrl_connect.11953747
Short name	T127
Test name
Test status
Simulation time	15054200 ps
CPU time	15.78 seconds
Started	Jul 12 07:22:31 PM PDT 24
Finished	Jul 12 07:22:50 PM PDT 24
Peak memory	274980 kb
Host	smart-5e16e5e4-0be9-4725-8333-cca3b8bc68ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11953747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.11953747
Directory	/workspace/66.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/66.flash_ctrl_otp_reset.3939052126
Short name	T429
Test name
Test status
Simulation time	75001400 ps
CPU time	111.2 seconds
Started	Jul 12 07:22:31 PM PDT 24
Finished	Jul 12 07:24:26 PM PDT 24
Peak memory	259996 kb
Host	smart-c6350445-1bff-41c7-86e7-37d6701d6350
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939052126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o tp_reset.3939052126
Directory	/workspace/66.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/67.flash_ctrl_connect.3782456916
Short name	T432
Test name
Test status
Simulation time	13974900 ps
CPU time	16.15 seconds
Started	Jul 12 07:22:30 PM PDT 24
Finished	Jul 12 07:22:50 PM PDT 24
Peak memory	284384 kb
Host	smart-ca127974-bdd9-4524-9bde-16ac2e863749
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782456916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.3782456916
Directory	/workspace/67.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/67.flash_ctrl_otp_reset.2562081936
Short name	T711
Test name
Test status
Simulation time	75233600 ps
CPU time	131.8 seconds
Started	Jul 12 07:22:32 PM PDT 24
Finished	Jul 12 07:24:49 PM PDT 24
Peak memory	260064 kb
Host	smart-037e8911-1381-4929-878b-9f7ce3be0eb6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562081936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o tp_reset.2562081936
Directory	/workspace/67.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/68.flash_ctrl_connect.3708591282
Short name	T945
Test name
Test status
Simulation time	25436700 ps
CPU time	13.24 seconds
Started	Jul 12 07:22:35 PM PDT 24
Finished	Jul 12 07:22:52 PM PDT 24
Peak memory	275000 kb
Host	smart-e7de854c-bf26-4941-996f-7cc7d977e2ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708591282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3708591282
Directory	/workspace/68.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/68.flash_ctrl_otp_reset.3316988537
Short name	T159
Test name
Test status
Simulation time	140772700 ps
CPU time	132.44 seconds
Started	Jul 12 07:22:29 PM PDT 24
Finished	Jul 12 07:24:45 PM PDT 24
Peak memory	261084 kb
Host	smart-d2eb3155-9455-4f6e-b3b3-562626818651
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316988537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o tp_reset.3316988537
Directory	/workspace/68.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/69.flash_ctrl_connect.917602468
Short name	T779
Test name
Test status
Simulation time	13926400 ps
CPU time	16.15 seconds
Started	Jul 12 07:22:31 PM PDT 24
Finished	Jul 12 07:22:51 PM PDT 24
Peak memory	284328 kb
Host	smart-bcd757e2-4a2a-485f-8af1-f76a02d51941
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=917602468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.917602468
Directory	/workspace/69.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/69.flash_ctrl_otp_reset.1219674174
Short name	T600
Test name
Test status
Simulation time	39843700 ps
CPU time	129.72 seconds
Started	Jul 12 07:22:34 PM PDT 24
Finished	Jul 12 07:24:48 PM PDT 24
Peak memory	265140 kb
Host	smart-ac8eecd5-6ae0-4e29-bff3-ae8c849a7670
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219674174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o tp_reset.1219674174
Directory	/workspace/69.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_alert_test.758903109
Short name	T777
Test name
Test status
Simulation time	107586900 ps
CPU time	13.58 seconds
Started	Jul 12 07:15:15 PM PDT 24
Finished	Jul 12 07:16:14 PM PDT 24
Peak memory	258240 kb
Host	smart-6510a12b-9690-4b37-9d8f-5e18fb5ceebb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758903109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.758903109
Directory	/workspace/7.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.flash_ctrl_connect.887980557
Short name	T944
Test name
Test status
Simulation time	31624600 ps
CPU time	13.73 seconds
Started	Jul 12 07:15:15 PM PDT 24
Finished	Jul 12 07:16:14 PM PDT 24
Peak memory	275012 kb
Host	smart-742fbef5-aaa4-4459-919c-79461bbae18b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=887980557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.887980557
Directory	/workspace/7.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/7.flash_ctrl_disable.2677801739
Short name	T167
Test name
Test status
Simulation time	28299900 ps
CPU time	21.96 seconds
Started	Jul 12 07:15:14 PM PDT 24
Finished	Jul 12 07:16:22 PM PDT 24
Peak memory	273692 kb
Host	smart-8f3394e3-16a9-4e7e-a99a-c8fe806422bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677801739 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_disable.2677801739
Directory	/workspace/7.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_mp.1548410126
Short name	T125
Test name
Test status
Simulation time	2575194300 ps
CPU time	2119.27 seconds
Started	Jul 12 07:13:54 PM PDT 24
Finished	Jul 12 07:49:23 PM PDT 24
Peak memory	262800 kb
Host	smart-f79bf585-691b-4407-8fa2-75894645ba68
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1548410126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.1548410126
Directory	/workspace/7.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_prog_win.1837013831
Short name	T591
Test name
Test status
Simulation time	384350300 ps
CPU time	819.61 seconds
Started	Jul 12 07:13:55 PM PDT 24
Finished	Jul 12 07:27:43 PM PDT 24
Peak memory	273428 kb
Host	smart-f45dceb4-e2fb-4490-b038-0953c2ea9e54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837013831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.1837013831
Directory	/workspace/7.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/7.flash_ctrl_fetch_code.1437622970
Short name	T947
Test name
Test status
Simulation time	172775600 ps
CPU time	29.46 seconds
Started	Jul 12 07:13:55 PM PDT 24
Finished	Jul 12 07:14:33 PM PDT 24
Peak memory	263696 kb
Host	smart-b5c03bf0-db43-434a-937e-7a29fe659bf1
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437622970 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.1437622970
Directory	/workspace/7.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.1946181674
Short name	T271
Test name
Test status
Simulation time	10034531200 ps
CPU time	107.93 seconds
Started	Jul 12 07:15:13 PM PDT 24
Finished	Jul 12 07:17:47 PM PDT 24
Peak memory	276876 kb
Host	smart-0c5a4133-8060-4b39-9056-73881271264a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946181674 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.1946181674
Directory	/workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_rma_reset.2988895097
Short name	T642
Test name
Test status
Simulation time	40124161900 ps
CPU time	858.74 seconds
Started	Jul 12 07:13:49 PM PDT 24
Finished	Jul 12 07:28:18 PM PDT 24
Peak memory	264476 kb
Host	smart-0aa74b85-3184-4ea9-a0f5-912f32e9555a
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988895097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.flash_ctrl_hw_rma_reset.2988895097
Directory	/workspace/7.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_sec_otp.2479175451
Short name	T1088
Test name
Test status
Simulation time	3498939100 ps
CPU time	71.73 seconds
Started	Jul 12 07:13:49 PM PDT 24
Finished	Jul 12 07:15:11 PM PDT 24
Peak memory	263404 kb
Host	smart-929e0d89-03ee-445e-ab99-9074dd64930a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479175451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h w_sec_otp.2479175451
Directory	/workspace/7.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd.1549084212
Short name	T868
Test name
Test status
Simulation time	8204313900 ps
CPU time	224.25 seconds
Started	Jul 12 07:14:08 PM PDT 24
Finished	Jul 12 07:18:06 PM PDT 24
Peak memory	291568 kb
Host	smart-d960dee9-a87a-4fdf-9b30-d57a7eb52fd1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549084212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_intr_rd.1549084212
Directory	/workspace/7.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3415117216
Short name	T418
Test name
Test status
Simulation time	22480542400 ps
CPU time	129.5 seconds
Started	Jul 12 07:14:06 PM PDT 24
Finished	Jul 12 07:16:26 PM PDT 24
Peak memory	293164 kb
Host	smart-128e7736-ef33-49e2-8523-a222b43344bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415117216 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.3415117216
Directory	/workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr.320557907
Short name	T495
Test name
Test status
Simulation time	4410248800 ps
CPU time	69.16 seconds
Started	Jul 12 07:14:06 PM PDT 24
Finished	Jul 12 07:15:24 PM PDT 24
Peak memory	260576 kb
Host	smart-1897152b-4c75-49e4-b091-c67f2d84d5e7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320557907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 7.flash_ctrl_intr_wr.320557907
Directory	/workspace/7.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.687264546
Short name	T496
Test name
Test status
Simulation time	51769765200 ps
CPU time	199.2 seconds
Started	Jul 12 07:14:04 PM PDT 24
Finished	Jul 12 07:17:32 PM PDT 24
Peak memory	260472 kb
Host	smart-40819cb3-439c-43aa-a9e0-00e71cf1c86c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687 264546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.687264546
Directory	/workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_invalid_op.335855834
Short name	T379
Test name
Test status
Simulation time	2314349300 ps
CPU time	92.97 seconds
Started	Jul 12 07:13:55 PM PDT 24
Finished	Jul 12 07:15:37 PM PDT 24
Peak memory	260612 kb
Host	smart-3d1f695b-cc57-4eaa-b568-2cff71372574
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335855834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.335855834
Directory	/workspace/7.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/7.flash_ctrl_lcmgr_intg.1697289891
Short name	T440
Test name
Test status
Simulation time	79850200 ps
CPU time	13.59 seconds
Started	Jul 12 07:16:11 PM PDT 24
Finished	Jul 12 07:17:03 PM PDT 24
Peak memory	260904 kb
Host	smart-5d77841c-6b47-4591-b126-e332e2f21adf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697289891 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.1697289891
Directory	/workspace/7.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/7.flash_ctrl_mp_regions.1025894721
Short name	T138
Test name
Test status
Simulation time	27154469500 ps
CPU time	288.65 seconds
Started	Jul 12 07:13:55 PM PDT 24
Finished	Jul 12 07:18:52 PM PDT 24
Peak memory	274752 kb
Host	smart-3d99d295-17f6-49e0-a2cf-471804d1ce75
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025894721 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.1025894721
Directory	/workspace/7.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/7.flash_ctrl_otp_reset.1926090352
Short name	T304
Test name
Test status
Simulation time	75973900 ps
CPU time	130.13 seconds
Started	Jul 12 07:13:48 PM PDT 24
Finished	Jul 12 07:16:08 PM PDT 24
Peak memory	260120 kb
Host	smart-37964408-c03e-489b-9a7a-52e1fec459af
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926090352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot p_reset.1926090352
Directory	/workspace/7.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_phy_arb.183761049
Short name	T778
Test name
Test status
Simulation time	91758500 ps
CPU time	447.97 seconds
Started	Jul 12 07:13:51 PM PDT 24
Finished	Jul 12 07:21:29 PM PDT 24
Peak memory	263160 kb
Host	smart-03b3908b-f0b9-48f3-aacf-2af01bc2abc6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=183761049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.183761049
Directory	/workspace/7.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/7.flash_ctrl_prog_reset.19893267
Short name	T841
Test name
Test status
Simulation time	4306713900 ps
CPU time	199.18 seconds
Started	Jul 12 07:14:07 PM PDT 24
Finished	Jul 12 07:17:37 PM PDT 24
Peak memory	265164 kb
Host	smart-29fdfc4b-0f5a-4b93-9488-c8e99310516b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19893267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U VM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_prog_reset.19893267
Directory	/workspace/7.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rand_ops.1806126570
Short name	T1002
Test name
Test status
Simulation time	25973700 ps
CPU time	119.07 seconds
Started	Jul 12 07:13:45 PM PDT 24
Finished	Jul 12 07:15:52 PM PDT 24
Peak memory	276668 kb
Host	smart-a4302a63-cb44-4ae2-8b93-ca6adf81accd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1806126570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.1806126570
Directory	/workspace/7.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/7.flash_ctrl_re_evict.2940858400
Short name	T384
Test name
Test status
Simulation time	137659200 ps
CPU time	32.26 seconds
Started	Jul 12 07:15:14 PM PDT 24
Finished	Jul 12 07:16:32 PM PDT 24
Peak memory	276708 kb
Host	smart-e2a6aa9a-ded3-4d9f-a13b-be3cc51a16fc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940858400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_re_evict.2940858400
Directory	/workspace/7.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro.3831722521
Short name	T966
Test name
Test status
Simulation time	2347772600 ps
CPU time	119.26 seconds
Started	Jul 12 07:13:56 PM PDT 24
Finished	Jul 12 07:16:05 PM PDT 24
Peak memory	291700 kb
Host	smart-cb2484a7-9215-474e-910b-64e8f234b0e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831722521 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_ro.3831722521
Directory	/workspace/7.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_derr.362999923
Short name	T1069
Test name
Test status
Simulation time	546936400 ps
CPU time	159.47 seconds
Started	Jul 12 07:14:06 PM PDT 24
Finished	Jul 12 07:16:56 PM PDT 24
Peak memory	281844 kb
Host	smart-24ae2bff-806d-4b66-8d81-5a0190e7dc78
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 362999923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.362999923
Directory	/workspace/7.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_serr.3855362488
Short name	T884
Test name
Test status
Simulation time	1852487400 ps
CPU time	131.5 seconds
Started	Jul 12 07:14:07 PM PDT 24
Finished	Jul 12 07:16:30 PM PDT 24
Peak memory	295200 kb
Host	smart-981abfb1-fbf6-403f-a6b9-1e37e83f4c3a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855362488 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.3855362488
Directory	/workspace/7.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw.2184262260
Short name	T504
Test name
Test status
Simulation time	8751964900 ps
CPU time	721.91 seconds
Started	Jul 12 07:13:55 PM PDT 24
Finished	Jul 12 07:26:06 PM PDT 24
Peak memory	318888 kb
Host	smart-ff915204-883a-4b77-934e-90e7075465fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184262260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.flash_ctrl_rw.2184262260
Directory	/workspace/7.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_derr.2047201963
Short name	T871
Test name
Test status
Simulation time	15424845200 ps
CPU time	589.57 seconds
Started	Jul 12 07:14:06 PM PDT 24
Finished	Jul 12 07:24:06 PM PDT 24
Peak memory	334444 kb
Host	smart-e554d70a-e218-4847-97a0-c3bd1f1af122
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047201963 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_rw_derr.2047201963
Directory	/workspace/7.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict.2284146500
Short name	T817
Test name
Test status
Simulation time	30228400 ps
CPU time	32.17 seconds
Started	Jul 12 07:14:07 PM PDT 24
Finished	Jul 12 07:14:51 PM PDT 24
Peak memory	275632 kb
Host	smart-7b4605b8-92dc-48bd-9dd5-416f2e3c7b47
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284146500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_rw_evict.2284146500
Directory	/workspace/7.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.2700283610
Short name	T886
Test name
Test status
Simulation time	31340800 ps
CPU time	30.78 seconds
Started	Jul 12 07:14:07 PM PDT 24
Finished	Jul 12 07:14:50 PM PDT 24
Peak memory	275620 kb
Host	smart-9b492948-e393-4809-a651-4ecec53f7297
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700283610 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.2700283610
Directory	/workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_serr.171286792
Short name	T109
Test name
Test status
Simulation time	16300806200 ps
CPU time	786.8 seconds
Started	Jul 12 07:14:08 PM PDT 24
Finished	Jul 12 07:27:26 PM PDT 24
Peak memory	313068 kb
Host	smart-7f8d2a4f-5296-4da8-bf1e-8dd84303e334
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171286792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_se rr.171286792
Directory	/workspace/7.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_sec_info_access.2057186283
Short name	T187
Test name
Test status
Simulation time	457709700 ps
CPU time	58.23 seconds
Started	Jul 12 07:15:14 PM PDT 24
Finished	Jul 12 07:16:58 PM PDT 24
Peak memory	264772 kb
Host	smart-16589e4a-62c1-41ab-8e94-ede27b760cd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057186283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2057186283
Directory	/workspace/7.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/7.flash_ctrl_smoke.2317657519
Short name	T667
Test name
Test status
Simulation time	129206400 ps
CPU time	121.61 seconds
Started	Jul 12 07:13:39 PM PDT 24
Finished	Jul 12 07:15:43 PM PDT 24
Peak memory	276516 kb
Host	smart-083fce23-c855-4995-b301-7986cf87b49d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2317657519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2317657519
Directory	/workspace/7.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.flash_ctrl_wo.3327395289
Short name	T527
Test name
Test status
Simulation time	7054401600 ps
CPU time	178.1 seconds
Started	Jul 12 07:13:56 PM PDT 24
Finished	Jul 12 07:17:03 PM PDT 24
Peak memory	265252 kb
Host	smart-1b5c450a-47c0-45b8-b776-326739fbe827
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327395289 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.flash_ctrl_wo.3327395289
Directory	/workspace/7.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/70.flash_ctrl_connect.579620289
Short name	T416
Test name
Test status
Simulation time	140690200 ps
CPU time	13.69 seconds
Started	Jul 12 07:22:30 PM PDT 24
Finished	Jul 12 07:22:47 PM PDT 24
Peak memory	274964 kb
Host	smart-0af0e9dc-46fe-4960-a2e7-c5e4f7905e5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579620289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.579620289
Directory	/workspace/70.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/70.flash_ctrl_otp_reset.234830944
Short name	T991
Test name
Test status
Simulation time	72092400 ps
CPU time	112.01 seconds
Started	Jul 12 07:22:31 PM PDT 24
Finished	Jul 12 07:24:26 PM PDT 24
Peak memory	261120 kb
Host	smart-26d03439-3f29-4885-9cc0-87b52cd7cc62
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234830944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_ot p_reset.234830944
Directory	/workspace/70.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/71.flash_ctrl_connect.2642030658
Short name	T510
Test name
Test status
Simulation time	56181700 ps
CPU time	16.22 seconds
Started	Jul 12 07:22:34 PM PDT 24
Finished	Jul 12 07:22:55 PM PDT 24
Peak memory	275052 kb
Host	smart-16061297-9991-40ce-9204-9b366b15ebc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2642030658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2642030658
Directory	/workspace/71.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/71.flash_ctrl_otp_reset.211558331
Short name	T887
Test name
Test status
Simulation time	98039800 ps
CPU time	132.36 seconds
Started	Jul 12 07:22:35 PM PDT 24
Finished	Jul 12 07:24:51 PM PDT 24
Peak memory	260120 kb
Host	smart-faa5c067-e99a-451b-a79f-9b2cb534b1a5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211558331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_ot p_reset.211558331
Directory	/workspace/71.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/72.flash_ctrl_connect.2050754529
Short name	T451
Test name
Test status
Simulation time	93187100 ps
CPU time	13.31 seconds
Started	Jul 12 07:22:33 PM PDT 24
Finished	Jul 12 07:22:51 PM PDT 24
Peak memory	284324 kb
Host	smart-95dc2cf5-6ba3-409c-831d-57889f369469
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050754529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.2050754529
Directory	/workspace/72.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/72.flash_ctrl_otp_reset.2920143550
Short name	T12
Test name
Test status
Simulation time	36610800 ps
CPU time	131.59 seconds
Started	Jul 12 07:22:31 PM PDT 24
Finished	Jul 12 07:24:46 PM PDT 24
Peak memory	260104 kb
Host	smart-0a351bc0-cc81-406a-9ac8-5bc81259b910
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920143550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o tp_reset.2920143550
Directory	/workspace/72.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/73.flash_ctrl_connect.3461796033
Short name	T856
Test name
Test status
Simulation time	28101000 ps
CPU time	15.6 seconds
Started	Jul 12 07:22:41 PM PDT 24
Finished	Jul 12 07:23:00 PM PDT 24
Peak memory	274784 kb
Host	smart-8959bb4f-cbe3-4931-9cdb-0b9176d58b24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461796033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.3461796033
Directory	/workspace/73.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/73.flash_ctrl_otp_reset.2175490164
Short name	T541
Test name
Test status
Simulation time	135628100 ps
CPU time	130.04 seconds
Started	Jul 12 07:22:38 PM PDT 24
Finished	Jul 12 07:24:51 PM PDT 24
Peak memory	259928 kb
Host	smart-c7345e43-511a-4d74-87a7-05724a1cc0c2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175490164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o tp_reset.2175490164
Directory	/workspace/73.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/74.flash_ctrl_connect.3677683861
Short name	T1001
Test name
Test status
Simulation time	26078400 ps
CPU time	15.78 seconds
Started	Jul 12 07:22:39 PM PDT 24
Finished	Jul 12 07:22:59 PM PDT 24
Peak memory	274916 kb
Host	smart-d8b63941-e554-4bd7-88ae-03ae924744af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3677683861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.3677683861
Directory	/workspace/74.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/74.flash_ctrl_otp_reset.4001015024
Short name	T165
Test name
Test status
Simulation time	43611100 ps
CPU time	130.38 seconds
Started	Jul 12 07:22:41 PM PDT 24
Finished	Jul 12 07:24:56 PM PDT 24
Peak memory	260124 kb
Host	smart-98cab0f4-69c7-406e-9a7f-dc608ce1d288
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001015024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o tp_reset.4001015024
Directory	/workspace/74.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/75.flash_ctrl_connect.1112090244
Short name	T652
Test name
Test status
Simulation time	27594300 ps
CPU time	15.75 seconds
Started	Jul 12 07:22:40 PM PDT 24
Finished	Jul 12 07:23:01 PM PDT 24
Peak memory	284396 kb
Host	smart-067a70a1-1a0b-4bed-9512-d51f58a2590d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112090244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.1112090244
Directory	/workspace/75.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/75.flash_ctrl_otp_reset.744872453
Short name	T151
Test name
Test status
Simulation time	66145100 ps
CPU time	131.53 seconds
Started	Jul 12 07:22:40 PM PDT 24
Finished	Jul 12 07:24:55 PM PDT 24
Peak memory	264656 kb
Host	smart-5fa0f92f-e438-4019-a471-8089065fa866
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744872453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_ot p_reset.744872453
Directory	/workspace/75.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/76.flash_ctrl_connect.353104908
Short name	T460
Test name
Test status
Simulation time	65589800 ps
CPU time	16.3 seconds
Started	Jul 12 07:22:40 PM PDT 24
Finished	Jul 12 07:23:01 PM PDT 24
Peak memory	274928 kb
Host	smart-a07da5ce-7496-48e4-b2f8-0b773afc578c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353104908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.353104908
Directory	/workspace/76.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/76.flash_ctrl_otp_reset.2957797205
Short name	T445
Test name
Test status
Simulation time	38732900 ps
CPU time	110.28 seconds
Started	Jul 12 07:22:38 PM PDT 24
Finished	Jul 12 07:24:30 PM PDT 24
Peak memory	260200 kb
Host	smart-5c86e580-c9ed-4057-8a0e-d4e0df0c2f95
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957797205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o tp_reset.2957797205
Directory	/workspace/76.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/77.flash_ctrl_connect.2782638324
Short name	T508
Test name
Test status
Simulation time	14245000 ps
CPU time	13.33 seconds
Started	Jul 12 07:22:38 PM PDT 24
Finished	Jul 12 07:22:54 PM PDT 24
Peak memory	274872 kb
Host	smart-22288455-df92-4f60-b56f-55320beea7b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782638324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2782638324
Directory	/workspace/77.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/77.flash_ctrl_otp_reset.1248454596
Short name	T436
Test name
Test status
Simulation time	39489300 ps
CPU time	113.21 seconds
Started	Jul 12 07:22:38 PM PDT 24
Finished	Jul 12 07:24:33 PM PDT 24
Peak memory	265344 kb
Host	smart-33bb33b5-27f7-42f7-baa1-cee93b907727
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248454596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o tp_reset.1248454596
Directory	/workspace/77.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/78.flash_ctrl_connect.553028404
Short name	T897
Test name
Test status
Simulation time	22321200 ps
CPU time	15.74 seconds
Started	Jul 12 07:22:40 PM PDT 24
Finished	Jul 12 07:23:00 PM PDT 24
Peak memory	284268 kb
Host	smart-5ca1b47d-cbe2-431f-9483-8f6164e58049
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553028404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.553028404
Directory	/workspace/78.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/78.flash_ctrl_otp_reset.3577978594
Short name	T350
Test name
Test status
Simulation time	427077000 ps
CPU time	109.51 seconds
Started	Jul 12 07:22:40 PM PDT 24
Finished	Jul 12 07:24:33 PM PDT 24
Peak memory	264336 kb
Host	smart-04231057-df03-4759-b1b5-82aa2b170c70
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577978594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o tp_reset.3577978594
Directory	/workspace/78.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/79.flash_ctrl_connect.3055598432
Short name	T421
Test name
Test status
Simulation time	134627700 ps
CPU time	13.43 seconds
Started	Jul 12 07:22:40 PM PDT 24
Finished	Jul 12 07:22:57 PM PDT 24
Peak memory	274964 kb
Host	smart-f81666df-d78b-4c01-a854-d2df8793a672
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055598432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.3055598432
Directory	/workspace/79.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/79.flash_ctrl_otp_reset.3784585526
Short name	T1028
Test name
Test status
Simulation time	38583800 ps
CPU time	108.41 seconds
Started	Jul 12 07:22:39 PM PDT 24
Finished	Jul 12 07:24:30 PM PDT 24
Peak memory	260004 kb
Host	smart-3b6f8688-178d-4619-adb0-9331ac251ca2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784585526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o tp_reset.3784585526
Directory	/workspace/79.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_alert_test.444626445
Short name	T420
Test name
Test status
Simulation time	81763300 ps
CPU time	13.84 seconds
Started	Jul 12 07:15:22 PM PDT 24
Finished	Jul 12 07:16:23 PM PDT 24
Peak memory	258256 kb
Host	smart-02dbb354-d0b6-498c-bc50-104067e08a76
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444626445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.444626445
Directory	/workspace/8.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.flash_ctrl_connect.1580343591
Short name	T840
Test name
Test status
Simulation time	15996700 ps
CPU time	13.3 seconds
Started	Jul 12 07:15:26 PM PDT 24
Finished	Jul 12 07:16:26 PM PDT 24
Peak memory	274844 kb
Host	smart-69c879da-b755-4c20-b709-fdf1813d61f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1580343591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.1580343591
Directory	/workspace/8.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_mp.2747498219
Short name	T142
Test name
Test status
Simulation time	10248933800 ps
CPU time	2311.13 seconds
Started	Jul 12 07:15:15 PM PDT 24
Finished	Jul 12 07:54:32 PM PDT 24
Peak memory	262900 kb
Host	smart-2fbb171b-8fb1-4580-a8a4-501b1d43ee94
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2747498219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.2747498219
Directory	/workspace/8.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_prog_win.3437979161
Short name	T723
Test name
Test status
Simulation time	832711200 ps
CPU time	912.67 seconds
Started	Jul 12 07:15:12 PM PDT 24
Finished	Jul 12 07:31:08 PM PDT 24
Peak memory	273272 kb
Host	smart-160192d0-5aef-426b-96ca-cb6e5fb00333
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437979161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3437979161
Directory	/workspace/8.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/8.flash_ctrl_fetch_code.3273642842
Short name	T48
Test name
Test status
Simulation time	114027700 ps
CPU time	19.45 seconds
Started	Jul 12 07:15:14 PM PDT 24
Finished	Jul 12 07:16:19 PM PDT 24
Peak memory	263552 kb
Host	smart-cb6bb715-ae20-401b-8367-9c3eb65a73be
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273642842 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.3273642842
Directory	/workspace/8.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3514503059
Short name	T718
Test name
Test status
Simulation time	10015972500 ps
CPU time	93.36 seconds
Started	Jul 12 07:15:26 PM PDT 24
Finished	Jul 12 07:17:47 PM PDT 24
Peak memory	292264 kb
Host	smart-2bca5e62-b1e6-4868-b176-0b267644f80a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514503059 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3514503059
Directory	/workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3611428585
Short name	T179
Test name
Test status
Simulation time	26047500 ps
CPU time	13.31 seconds
Started	Jul 12 07:15:22 PM PDT 24
Finished	Jul 12 07:16:23 PM PDT 24
Peak memory	264908 kb
Host	smart-fdbfca2d-5c78-4422-a947-75bdc8fe5148
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611428585 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3611428585
Directory	/workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.1480827139
Short name	T95
Test name
Test status
Simulation time	80154696100 ps
CPU time	844.78 seconds
Started	Jul 12 07:15:14 PM PDT 24
Finished	Jul 12 07:30:05 PM PDT 24
Peak memory	264464 kb
Host	smart-0127c7f1-7ba4-423c-970c-d7f12b71f3f1
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480827139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.flash_ctrl_hw_rma_reset.1480827139
Directory	/workspace/8.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2098558073
Short name	T838
Test name
Test status
Simulation time	12709163300 ps
CPU time	123.72 seconds
Started	Jul 12 07:15:15 PM PDT 24
Finished	Jul 12 07:18:04 PM PDT 24
Peak memory	263232 kb
Host	smart-1b9adaef-776e-4a45-9c45-dd3219b28efb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098558073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h w_sec_otp.2098558073
Directory	/workspace/8.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd.2015676973
Short name	T1080
Test name
Test status
Simulation time	10143945100 ps
CPU time	203.67 seconds
Started	Jul 12 07:15:22 PM PDT 24
Finished	Jul 12 07:19:34 PM PDT 24
Peak memory	292320 kb
Host	smart-a1a38f55-fbf3-42cd-9897-fccf36a0f24d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015676973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_intr_rd.2015676973
Directory	/workspace/8.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2307071528
Short name	T207
Test name
Test status
Simulation time	11519519800 ps
CPU time	156.47 seconds
Started	Jul 12 07:15:35 PM PDT 24
Finished	Jul 12 07:19:00 PM PDT 24
Peak memory	290948 kb
Host	smart-90192ee6-8797-4aef-92fc-a97f4084cdc8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307071528 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.2307071528
Directory	/workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr.3373837309
Short name	T970
Test name
Test status
Simulation time	2302995000 ps
CPU time	64.73 seconds
Started	Jul 12 07:15:24 PM PDT 24
Finished	Jul 12 07:17:15 PM PDT 24
Peak memory	260068 kb
Host	smart-c7e2fa6d-5467-4105-b69b-75f775b02e80
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373837309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.flash_ctrl_intr_wr.3373837309
Directory	/workspace/8.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1757107658
Short name	T629
Test name
Test status
Simulation time	40473435400 ps
CPU time	181.63 seconds
Started	Jul 12 07:15:26 PM PDT 24
Finished	Jul 12 07:19:14 PM PDT 24
Peak memory	260404 kb
Host	smart-fe4961b3-07ba-48a2-9d07-2d65465904b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175 7107658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.1757107658
Directory	/workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_invalid_op.3471868238
Short name	T376
Test name
Test status
Simulation time	2020537900 ps
CPU time	79.68 seconds
Started	Jul 12 07:15:16 PM PDT 24
Finished	Jul 12 07:17:20 PM PDT 24
Peak memory	263424 kb
Host	smart-1988256a-3cbc-485b-8257-4c2f02ceb8d6
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471868238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3471868238
Directory	/workspace/8.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/8.flash_ctrl_lcmgr_intg.2907063712
Short name	T150
Test name
Test status
Simulation time	72203100 ps
CPU time	13.38 seconds
Started	Jul 12 07:15:23 PM PDT 24
Finished	Jul 12 07:16:24 PM PDT 24
Peak memory	265252 kb
Host	smart-f16affe4-d022-4782-a900-fddcd489effa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907063712 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.2907063712
Directory	/workspace/8.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/8.flash_ctrl_mp_regions.751587843
Short name	T1107
Test name
Test status
Simulation time	10790824700 ps
CPU time	335.1 seconds
Started	Jul 12 07:15:17 PM PDT 24
Finished	Jul 12 07:21:37 PM PDT 24
Peak memory	274260 kb
Host	smart-27512015-147d-4ad6-90b5-5e17155c3696
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751587843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.751587843
Directory	/workspace/8.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/8.flash_ctrl_otp_reset.3456576147
Short name	T872
Test name
Test status
Simulation time	36986900 ps
CPU time	111.29 seconds
Started	Jul 12 07:15:15 PM PDT 24
Finished	Jul 12 07:17:52 PM PDT 24
Peak memory	261152 kb
Host	smart-d67beee6-6ed4-4933-90a1-69aed0157bb0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456576147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot p_reset.3456576147
Directory	/workspace/8.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_phy_arb.3704014030
Short name	T574
Test name
Test status
Simulation time	65330500 ps
CPU time	110.81 seconds
Started	Jul 12 07:15:13 PM PDT 24
Finished	Jul 12 07:17:50 PM PDT 24
Peak memory	263296 kb
Host	smart-e95f3373-13ff-4f1f-8bce-4f8f266c9a60
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3704014030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3704014030
Directory	/workspace/8.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/8.flash_ctrl_prog_reset.1188851458
Short name	T790
Test name
Test status
Simulation time	19054926500 ps
CPU time	235.99 seconds
Started	Jul 12 07:15:22 PM PDT 24
Finished	Jul 12 07:20:03 PM PDT 24
Peak memory	260628 kb
Host	smart-ba6ad8db-75c0-4fad-9a04-07a580dc7db2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188851458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.flash_ctrl_prog_reset.1188851458
Directory	/workspace/8.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rand_ops.2253688585
Short name	T130
Test name
Test status
Simulation time	1797803500 ps
CPU time	937.24 seconds
Started	Jul 12 07:15:17 PM PDT 24
Finished	Jul 12 07:31:40 PM PDT 24
Peak memory	286592 kb
Host	smart-2b0c62b0-2f12-40fd-b3f9-a4a406baabcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253688585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2253688585
Directory	/workspace/8.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/8.flash_ctrl_re_evict.1698445437
Short name	T399
Test name
Test status
Simulation time	106027400 ps
CPU time	33.74 seconds
Started	Jul 12 07:15:24 PM PDT 24
Finished	Jul 12 07:16:44 PM PDT 24
Peak memory	273656 kb
Host	smart-07345fab-81ac-48ad-ac28-4b993a6120b4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698445437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_re_evict.1698445437
Directory	/workspace/8.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro.1430756473
Short name	T201
Test name
Test status
Simulation time	2503627900 ps
CPU time	107.03 seconds
Started	Jul 12 07:15:14 PM PDT 24
Finished	Jul 12 07:17:47 PM PDT 24
Peak memory	289184 kb
Host	smart-69595a2e-f878-4293-bf20-1099aed05c5b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430756473 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_ro.1430756473
Directory	/workspace/8.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_derr.289793395
Short name	T911
Test name
Test status
Simulation time	674972600 ps
CPU time	128.73 seconds
Started	Jul 12 07:15:16 PM PDT 24
Finished	Jul 12 07:18:09 PM PDT 24
Peak memory	283008 kb
Host	smart-a03abca3-86c2-4238-a731-0870c1c68400
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 289793395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.289793395
Directory	/workspace/8.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_serr.1435545141
Short name	T87
Test name
Test status
Simulation time	10952039000 ps
CPU time	156.29 seconds
Started	Jul 12 07:15:17 PM PDT 24
Finished	Jul 12 07:18:39 PM PDT 24
Peak memory	281772 kb
Host	smart-8b5b8de4-aa82-4edb-b448-d16bd4039f40
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435545141 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.1435545141
Directory	/workspace/8.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw.218241009
Short name	T689
Test name
Test status
Simulation time	4665077300 ps
CPU time	601.53 seconds
Started	Jul 12 07:15:14 PM PDT 24
Finished	Jul 12 07:26:01 PM PDT 24
Peak memory	314548 kb
Host	smart-322c5208-75ff-43ca-a938-ab20f635e7d1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218241009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.218241009
Directory	/workspace/8.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_derr.1314024330
Short name	T374
Test name
Test status
Simulation time	14236422500 ps
CPU time	728.62 seconds
Started	Jul 12 07:15:25 PM PDT 24
Finished	Jul 12 07:28:19 PM PDT 24
Peak memory	332960 kb
Host	smart-0871955f-7a73-4abe-91f5-0ed095f2ae0a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314024330 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_rw_derr.1314024330
Directory	/workspace/8.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict.1797776128
Short name	T398
Test name
Test status
Simulation time	32350200 ps
CPU time	31.51 seconds
Started	Jul 12 07:15:24 PM PDT 24
Finished	Jul 12 07:16:41 PM PDT 24
Peak memory	268532 kb
Host	smart-7bce883e-a97e-46bf-9910-a7de67e552f8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797776128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_rw_evict.1797776128
Directory	/workspace/8.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.2693722390
Short name	T1104
Test name
Test status
Simulation time	29209900 ps
CPU time	31.12 seconds
Started	Jul 12 07:15:22 PM PDT 24
Finished	Jul 12 07:16:41 PM PDT 24
Peak memory	275656 kb
Host	smart-7a92ab1a-2e99-4c7f-8221-ff7b6ff6bd9e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693722390 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.2693722390
Directory	/workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_serr.1452154112
Short name	T982
Test name
Test status
Simulation time	20555522700 ps
CPU time	798.95 seconds
Started	Jul 12 07:15:16 PM PDT 24
Finished	Jul 12 07:29:19 PM PDT 24
Peak memory	314048 kb
Host	smart-461cb32a-e440-4d6c-b254-b9bce5535dd2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452154112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s err.1452154112
Directory	/workspace/8.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_sec_info_access.3454327551
Short name	T836
Test name
Test status
Simulation time	342615200 ps
CPU time	61.31 seconds
Started	Jul 12 07:15:20 PM PDT 24
Finished	Jul 12 07:17:07 PM PDT 24
Peak memory	264700 kb
Host	smart-d5f9006a-660b-47ef-abf1-bdb71c626718
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3454327551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.3454327551
Directory	/workspace/8.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/8.flash_ctrl_smoke.562029109
Short name	T957
Test name
Test status
Simulation time	194102900 ps
CPU time	124.86 seconds
Started	Jul 12 07:15:14 PM PDT 24
Finished	Jul 12 07:18:04 PM PDT 24
Peak memory	276580 kb
Host	smart-5e43f120-f2f0-4a5e-bdbf-a9b7a644eddc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562029109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.562029109
Directory	/workspace/8.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.flash_ctrl_wo.2686209277
Short name	T814
Test name
Test status
Simulation time	3074817700 ps
CPU time	137.89 seconds
Started	Jul 12 07:15:15 PM PDT 24
Finished	Jul 12 07:18:18 PM PDT 24
Peak memory	259368 kb
Host	smart-1cbcdbd5-e8e0-47aa-9017-760d848ac4f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686209277 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.flash_ctrl_wo.2686209277
Directory	/workspace/8.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/9.flash_ctrl_alert_test.2876079023
Short name	T593
Test name
Test status
Simulation time	63464800 ps
CPU time	13.52 seconds
Started	Jul 12 07:15:43 PM PDT 24
Finished	Jul 12 07:16:41 PM PDT 24
Peak memory	265264 kb
Host	smart-64afe429-0278-4480-9a88-94370d8fbf06
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876079023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2 876079023
Directory	/workspace/9.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.flash_ctrl_connect.2507468068
Short name	T596
Test name
Test status
Simulation time	22785000 ps
CPU time	16.02 seconds
Started	Jul 12 07:15:40 PM PDT 24
Finished	Jul 12 07:16:42 PM PDT 24
Peak memory	274928 kb
Host	smart-b9b513eb-c242-49e8-9475-4e7b706cb8f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507468068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.2507468068
Directory	/workspace/9.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/9.flash_ctrl_disable.1096534301
Short name	T341
Test name
Test status
Simulation time	11218000 ps
CPU time	21.9 seconds
Started	Jul 12 07:15:33 PM PDT 24
Finished	Jul 12 07:16:41 PM PDT 24
Peak memory	274796 kb
Host	smart-c0758129-e615-4c54-8b23-1228eb72ad66
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096534301 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_disable.1096534301
Directory	/workspace/9.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_mp.2128915630
Short name	T895
Test name
Test status
Simulation time	9385099600 ps
CPU time	2265.63 seconds
Started	Jul 12 07:15:31 PM PDT 24
Finished	Jul 12 07:54:02 PM PDT 24
Peak memory	265156 kb
Host	smart-1dcb707b-8b87-4ce1-86e1-e6b38c0d1ce7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2128915630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.2128915630
Directory	/workspace/9.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_prog_win.2407818124
Short name	T1045
Test name
Test status
Simulation time	2134357600 ps
CPU time	735.36 seconds
Started	Jul 12 07:15:34 PM PDT 24
Finished	Jul 12 07:28:35 PM PDT 24
Peak memory	265148 kb
Host	smart-9f8bf32a-ebc3-43af-8eb3-70f68521ca9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407818124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2407818124
Directory	/workspace/9.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/9.flash_ctrl_fetch_code.3935225698
Short name	T863
Test name
Test status
Simulation time	116034800 ps
CPU time	23.38 seconds
Started	Jul 12 07:15:34 PM PDT 24
Finished	Jul 12 07:16:43 PM PDT 24
Peak memory	263492 kb
Host	smart-70dfa1c9-faad-455c-abb0-872683591fc1
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935225698 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.3935225698
Directory	/workspace/9.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.424147113
Short name	T1072
Test name
Test status
Simulation time	10012431000 ps
CPU time	116.01 seconds
Started	Jul 12 07:15:40 PM PDT 24
Finished	Jul 12 07:18:22 PM PDT 24
Peak memory	341248 kb
Host	smart-ae5d51ba-e1fb-40e2-8fb6-243e5ba91f02
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424147113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.424147113
Directory	/workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.2955311678
Short name	T643
Test name
Test status
Simulation time	46248900 ps
CPU time	13.33 seconds
Started	Jul 12 07:15:42 PM PDT 24
Finished	Jul 12 07:16:39 PM PDT 24
Peak memory	260368 kb
Host	smart-75de51dd-9c01-49c2-a17c-af2c623d8c35
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955311678 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.2955311678
Directory	/workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_rma_reset.1664577708
Short name	T513
Test name
Test status
Simulation time	160172115200 ps
CPU time	926.86 seconds
Started	Jul 12 07:15:24 PM PDT 24
Finished	Jul 12 07:31:37 PM PDT 24
Peak memory	264844 kb
Host	smart-c56064c6-b054-4567-a87a-e0b19835fcad
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664577708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.flash_ctrl_hw_rma_reset.1664577708
Directory	/workspace/9.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_sec_otp.768887544
Short name	T528
Test name
Test status
Simulation time	1266209500 ps
CPU time	36.56 seconds
Started	Jul 12 07:15:26 PM PDT 24
Finished	Jul 12 07:16:50 PM PDT 24
Peak memory	260992 kb
Host	smart-c594c59f-4787-4b39-b9c5-e43a120ca1a6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768887544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw _sec_otp.768887544
Directory	/workspace/9.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd.3928554631
Short name	T565
Test name
Test status
Simulation time	2495756700 ps
CPU time	142.5 seconds
Started	Jul 12 07:15:32 PM PDT 24
Finished	Jul 12 07:18:41 PM PDT 24
Peak memory	294312 kb
Host	smart-be9347d9-4ea1-44f9-9caa-fd6da4788d5d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928554631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_intr_rd.3928554631
Directory	/workspace/9.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1772209819
Short name	T1092
Test name
Test status
Simulation time	12203551800 ps
CPU time	132.21 seconds
Started	Jul 12 07:15:29 PM PDT 24
Finished	Jul 12 07:18:27 PM PDT 24
Peak memory	293228 kb
Host	smart-e6071f87-722d-4733-8c37-efcb2a7c64c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772209819 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.1772209819
Directory	/workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr.3239322882
Short name	T546
Test name
Test status
Simulation time	8932185200 ps
CPU time	77.16 seconds
Started	Jul 12 07:15:31 PM PDT 24
Finished	Jul 12 07:17:34 PM PDT 24
Peak memory	260588 kb
Host	smart-3b6b047c-dd1f-4d27-8741-e53883612e8c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239322882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_intr_wr.3239322882
Directory	/workspace/9.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2686156129
Short name	T828
Test name
Test status
Simulation time	107935279600 ps
CPU time	293.48 seconds
Started	Jul 12 07:15:29 PM PDT 24
Finished	Jul 12 07:21:10 PM PDT 24
Peak memory	265208 kb
Host	smart-b0ee8899-34cc-4274-85e4-42fd1d4c97a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268 6156129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.2686156129
Directory	/workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_invalid_op.2302524629
Short name	T843
Test name
Test status
Simulation time	6477147900 ps
CPU time	73.92 seconds
Started	Jul 12 07:15:32 PM PDT 24
Finished	Jul 12 07:17:33 PM PDT 24
Peak memory	262708 kb
Host	smart-1372d832-2749-40c4-b277-2c8fef7bcb37
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302524629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2302524629
Directory	/workspace/9.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1958329121
Short name	T425
Test name
Test status
Simulation time	40636800 ps
CPU time	13.4 seconds
Started	Jul 12 07:15:42 PM PDT 24
Finished	Jul 12 07:16:39 PM PDT 24
Peak memory	265020 kb
Host	smart-573e9138-b95d-436e-b8af-cbcb57666398
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958329121 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1958329121
Directory	/workspace/9.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/9.flash_ctrl_mp_regions.791709036
Short name	T724
Test name
Test status
Simulation time	276525951100 ps
CPU time	411.47 seconds
Started	Jul 12 07:15:32 PM PDT 24
Finished	Jul 12 07:23:11 PM PDT 24
Peak memory	274940 kb
Host	smart-97c60f13-6e90-45ba-a8fc-bb6fb84efe67
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791709036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.791709036
Directory	/workspace/9.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/9.flash_ctrl_otp_reset.1615576328
Short name	T68
Test name
Test status
Simulation time	40657700 ps
CPU time	132.79 seconds
Started	Jul 12 07:15:21 PM PDT 24
Finished	Jul 12 07:18:19 PM PDT 24
Peak memory	260900 kb
Host	smart-1d2b8cf0-b73b-4e67-95e0-608f2de08fe8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615576328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot p_reset.1615576328
Directory	/workspace/9.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_phy_arb.907402456
Short name	T483
Test name
Test status
Simulation time	208533300 ps
CPU time	234.95 seconds
Started	Jul 12 07:15:23 PM PDT 24
Finished	Jul 12 07:20:05 PM PDT 24
Peak memory	263276 kb
Host	smart-3516dc10-18c0-4901-bd38-482ac32c7689
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=907402456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.907402456
Directory	/workspace/9.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/9.flash_ctrl_prog_reset.895396569
Short name	T289
Test name
Test status
Simulation time	22349200 ps
CPU time	13.94 seconds
Started	Jul 12 07:15:30 PM PDT 24
Finished	Jul 12 07:16:31 PM PDT 24
Peak memory	259108 kb
Host	smart-adeae739-4d59-456d-93e9-d912dad38fbf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895396569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.flash_ctrl_prog_reset.895396569
Directory	/workspace/9.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rand_ops.3780457893
Short name	T1021
Test name
Test status
Simulation time	2830781300 ps
CPU time	650.82 seconds
Started	Jul 12 07:15:22 PM PDT 24
Finished	Jul 12 07:27:00 PM PDT 24
Peak memory	285708 kb
Host	smart-e47e2f61-b0f0-44c4-ae32-7d357147d4df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3780457893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.3780457893
Directory	/workspace/9.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/9.flash_ctrl_re_evict.3122178716
Short name	T958
Test name
Test status
Simulation time	248285600 ps
CPU time	34.84 seconds
Started	Jul 12 07:15:31 PM PDT 24
Finished	Jul 12 07:16:52 PM PDT 24
Peak memory	268508 kb
Host	smart-8bdeab24-c774-424d-afa0-20146c73a6e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122178716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_re_evict.3122178716
Directory	/workspace/9.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro.1507379467
Short name	T64
Test name
Test status
Simulation time	623423000 ps
CPU time	106.25 seconds
Started	Jul 12 07:15:33 PM PDT 24
Finished	Jul 12 07:18:06 PM PDT 24
Peak memory	281724 kb
Host	smart-92b1097b-cac1-43fe-9728-336db59c39ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507379467 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_ro.1507379467
Directory	/workspace/9.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_derr.1152266982
Short name	T103
Test name
Test status
Simulation time	2929360200 ps
CPU time	148.86 seconds
Started	Jul 12 07:15:32 PM PDT 24
Finished	Jul 12 07:18:48 PM PDT 24
Peak memory	282000 kb
Host	smart-b3cb0f97-53d7-4b92-85e3-e8946ee24e95
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1152266982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.1152266982
Directory	/workspace/9.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_serr.990441329
Short name	T1057
Test name
Test status
Simulation time	1437016100 ps
CPU time	143.37 seconds
Started	Jul 12 07:15:34 PM PDT 24
Finished	Jul 12 07:18:43 PM PDT 24
Peak memory	281776 kb
Host	smart-14e15a33-3cec-4c57-92d7-821649616eac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990441329 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.990441329
Directory	/workspace/9.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw.2994770357
Short name	T210
Test name
Test status
Simulation time	18854676100 ps
CPU time	641.27 seconds
Started	Jul 12 07:15:29 PM PDT 24
Finished	Jul 12 07:26:56 PM PDT 24
Peak memory	309524 kb
Host	smart-0ee63b74-7a86-40dc-a378-4184da1edd5a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994770357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.flash_ctrl_rw.2994770357
Directory	/workspace/9.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_derr.1058677167
Short name	T52
Test name
Test status
Simulation time	10179685000 ps
CPU time	544.7 seconds
Started	Jul 12 07:15:30 PM PDT 24
Finished	Jul 12 07:25:21 PM PDT 24
Peak memory	332776 kb
Host	smart-b74c837f-3bad-4d43-93e1-c3b3ca19df31
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058677167 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_rw_derr.1058677167
Directory	/workspace/9.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict.1473092387
Short name	T380
Test name
Test status
Simulation time	35954100 ps
CPU time	27.75 seconds
Started	Jul 12 07:15:32 PM PDT 24
Finished	Jul 12 07:16:44 PM PDT 24
Peak memory	268680 kb
Host	smart-7c67dd71-a83b-4ea3-b8db-8eb08b7d9b12
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473092387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_rw_evict.1473092387
Directory	/workspace/9.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.2956055035
Short name	T551
Test name
Test status
Simulation time	43031600 ps
CPU time	28.52 seconds
Started	Jul 12 07:15:29 PM PDT 24
Finished	Jul 12 07:16:45 PM PDT 24
Peak memory	275592 kb
Host	smart-33868010-9a63-4cbe-8b6c-583a2b9ad7a3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956055035 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.2956055035
Directory	/workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_serr.1444891949
Short name	T553
Test name
Test status
Simulation time	20140786600 ps
CPU time	696.84 seconds
Started	Jul 12 07:15:34 PM PDT 24
Finished	Jul 12 07:27:57 PM PDT 24
Peak memory	312948 kb
Host	smart-42886375-3242-4cf5-9212-b22418c8eae4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444891949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s err.1444891949
Directory	/workspace/9.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_sec_info_access.4065670240
Short name	T363
Test name
Test status
Simulation time	851895000 ps
CPU time	74.56 seconds
Started	Jul 12 07:15:41 PM PDT 24
Finished	Jul 12 07:17:41 PM PDT 24
Peak memory	264868 kb
Host	smart-a3e8f0c3-18d6-4a12-8578-93f21de7d48c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065670240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.4065670240
Directory	/workspace/9.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/9.flash_ctrl_smoke.3232027381
Short name	T648
Test name
Test status
Simulation time	31205100 ps
CPU time	144.83 seconds
Started	Jul 12 07:15:21 PM PDT 24
Finished	Jul 12 07:18:30 PM PDT 24
Peak memory	279100 kb
Host	smart-d2947657-c757-4ad0-9ed9-ff6571fac20c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232027381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.3232027381
Directory	/workspace/9.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.flash_ctrl_wo.1498713858
Short name	T487
Test name
Test status
Simulation time	2544665800 ps
CPU time	95.14 seconds
Started	Jul 12 07:15:28 PM PDT 24
Finished	Jul 12 07:17:50 PM PDT 24
Peak memory	265316 kb
Host	smart-75453c9b-4a7d-4687-a9f5-0bcc7a50c3f8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498713858 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.flash_ctrl_wo.1498713858
Directory	/workspace/9.flash_ctrl_wo/latest

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