Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23707212	1		T1	61		T2	132338		T3	28329
full_word	7689188	1		T1	41		T2	16068		T3	19285

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31396100	1		T1	102		T2	148406		T3	47614
auto[TlIntgErrCmd]	99	1		T62	3		T107	9		T261	2
auto[TlIntgErrData]	103	1		T62	2		T107	7		T261	5
auto[TlIntgErrBoth]	98	1		T62	5		T107	4		T261	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26933093	1		T1	57		T2	131824		T3	33236
auto[1]	4463307	1		T1	45		T2	16582		T3	14378

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23028504	1		T1	57		T2	130899		T3	26518
auto[TlIntgErrNone]	partial	auto[1]	678429	1		T1	4		T2	1439		T3	1811
auto[TlIntgErrNone]	full_word	auto[0]	3904458	1		T2	925		T3	6718		T5	6078
auto[TlIntgErrNone]	full_word	auto[1]	3784709	1		T1	41		T2	15143		T3	12567
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T62	3		T107	4		T261	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T107	5		T261	1		T280	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T280	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T353	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1		T62	2		T261	3		T280	2
auto[TlIntgErrData]	partial	auto[1]	46	1		T107	5		T261	2		T280	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T107	1		T285	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	10	1		T107	1		T280	1		T276	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T62	3		T107	4		T261	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1		T62	1		T261	2		T280	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T280	1		T282	1		T353	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T62	1		T280	1		T282	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19374	1		T62	9		T106	70		T108	693
full_word	4140869	1		T5	16097		T4	16227		T15	16584

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4159969	1		T5	16097		T4	16227		T15	16584
auto[TlIntgErrCmd]	82	1		T62	2		T107	6		T280	7
auto[TlIntgErrData]	100	1		T62	3		T107	5		T261	3
auto[TlIntgErrBoth]	92	1		T62	4		T107	6		T261	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4135133	1		T5	16097		T4	16227		T15	16584
auto[1]	25110	1		T62	4		T106	99		T108	1173

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1117	1		T106	1		T108	6		T232	12
auto[TlIntgErrNone]	partial	auto[1]	18004	1		T106	69		T108	687		T232	430
auto[TlIntgErrNone]	full_word	auto[0]	4133905	1		T5	16097		T4	16227		T15	16584
auto[TlIntgErrNone]	full_word	auto[1]	6943	1		T106	30		T108	486		T232	215
auto[TlIntgErrCmd]	partial	auto[0]	23	1		T62	1		T107	1		T280	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T62	1		T107	5		T280	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T276	1		T351	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T283	1		T352	1		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1		T62	3		T107	2		T261	1
auto[TlIntgErrData]	partial	auto[1]	46	1		T107	2		T261	1		T280	5
auto[TlIntgErrData]	full_word	auto[0]	4	1		T275	1		T349	1		T354	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T107	1		T261	1		T275	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T62	1		T107	2		T261	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T62	3		T107	3		T261	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T107	1		T285	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T261	1		T275	1		T271	1