Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1494803392	1491409252	0	0
CheckNGreaterZero_A	4184	4184	0	0
GntImpliesReady_A	1494803392	398214480	0	0
GntImpliesValid_A	1494803392	398214480	0	0
GrantKnown_A	1494803392	1491409252	0	0
IdxKnown_A	1494803392	1491409252	0	0
IndexIsCorrect_A	1494803392	398214480	0	0
NoReadyValidNoGrant_A	1494803392	172175962	0	0
Priority_A	1494803392	422352454	0	0
ReadyAndValidImplyGrant_A	1494803392	398214480	0	0
ReqAndReadyImplyGrant_A	1494803392	398214480	0	0
ReqImpliesValid_A	1494803392	422352454	0	0
ValidKnown_A	1494803392	1491409252	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	1491409252	0	0
T1	1944	1548	0	0
T2	1190372	1190160	0	0
T3	1865500	1791412	0	0
T4	3410844	3410308	0	0
T5	188148	187840	0	0
T9	1602688	1602628	0	0
T10	5100	4172	0	0
T15	2303624	2302916	0	0
T16	264412	264096	0	0
T17	4800	4564	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4184	4184	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	398214480	0	0
T1	972	64	0	0
T2	1190372	528628	0	0
T3	1865500	336556	0	0
T4	3410844	59912	0	0
T5	188148	41410	0	0
T9	1602688	514650	0	0
T10	5100	134	0	0
T15	2303624	33250	0	0
T16	264412	43842	0	0
T17	4800	64	0	0
T18	60018	12356	0	0
T20	0	23340	0	0
T21	0	16908	0	0
T50	0	208830	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	398214480	0	0
T1	972	64	0	0
T2	1190372	528628	0	0
T3	1865500	336556	0	0
T4	3410844	59912	0	0
T5	188148	41410	0	0
T9	1602688	514650	0	0
T10	5100	134	0	0
T15	2303624	33250	0	0
T16	264412	43842	0	0
T17	4800	64	0	0
T18	60018	12356	0	0
T20	0	23340	0	0
T21	0	16908	0	0
T50	0	208830	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	1491409252	0	0
T1	1944	1548	0	0
T2	1190372	1190160	0	0
T3	1865500	1791412	0	0
T4	3410844	3410308	0	0
T5	188148	187840	0	0
T9	1602688	1602628	0	0
T10	5100	4172	0	0
T15	2303624	2302916	0	0
T16	264412	264096	0	0
T17	4800	4564	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	1491409252	0	0
T1	1944	1548	0	0
T2	1190372	1190160	0	0
T3	1865500	1791412	0	0
T4	3410844	3410308	0	0
T5	188148	187840	0	0
T9	1602688	1602628	0	0
T10	5100	4172	0	0
T15	2303624	2302916	0	0
T16	264412	264096	0	0
T17	4800	4564	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	398214480	0	0
T1	972	64	0	0
T2	1190372	528628	0	0
T3	1865500	336556	0	0
T4	3410844	59912	0	0
T5	188148	41410	0	0
T9	1602688	514650	0	0
T10	5100	134	0	0
T15	2303624	33250	0	0
T16	264412	43842	0	0
T17	4800	64	0	0
T18	60018	12356	0	0
T20	0	23340	0	0
T21	0	16908	0	0
T50	0	208830	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	172175962	0	0
T1	972	256	0	0
T2	595186	256	0	0
T3	932750	92704	0	0
T4	3410844	1867802	0	0
T5	188148	53114	0	0
T9	1602688	2109952	0	0
T10	5100	536	0	0
T15	2303624	1206316	0	0
T16	264412	125020	0	0
T17	4800	256	0	0
T18	60018	1212	0	0
T20	0	28582	0	0
T21	0	25972	0	0
T29	398292	0	0	0
T36	0	572	0	0
T50	364614	0	0	0
T52	0	1048744	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	422352454	0	0
T1	972	64	0	0
T2	1190372	528628	0	0
T3	1865500	336556	0	0
T4	3410844	621056	0	0
T5	188148	52124	0	0
T9	1602688	514650	0	0
T10	5100	134	0	0
T15	2303624	508436	0	0
T16	264412	46954	0	0
T17	4800	64	0	0
T18	60018	12356	0	0
T20	0	38308	0	0
T21	0	21326	0	0
T50	0	208830	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	398214480	0	0
T1	972	64	0	0
T2	1190372	528628	0	0
T3	1865500	336556	0	0
T4	3410844	59912	0	0
T5	188148	41410	0	0
T9	1602688	514650	0	0
T10	5100	134	0	0
T15	2303624	33250	0	0
T16	264412	43842	0	0
T17	4800	64	0	0
T18	60018	12356	0	0
T20	0	23340	0	0
T21	0	16908	0	0
T50	0	208830	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	398214480	0	0
T1	972	64	0	0
T2	1190372	528628	0	0
T3	1865500	336556	0	0
T4	3410844	59912	0	0
T5	188148	41410	0	0
T9	1602688	514650	0	0
T10	5100	134	0	0
T15	2303624	33250	0	0
T16	264412	43842	0	0
T17	4800	64	0	0
T18	60018	12356	0	0
T20	0	23340	0	0
T21	0	16908	0	0
T50	0	208830	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	422352454	0	0
T1	972	64	0	0
T2	1190372	528628	0	0
T3	1865500	336556	0	0
T4	3410844	621056	0	0
T5	188148	52124	0	0
T9	1602688	514650	0	0
T10	5100	134	0	0
T15	2303624	508436	0	0
T16	264412	46954	0	0
T17	4800	64	0	0
T18	60018	12356	0	0
T20	0	38308	0	0
T21	0	21326	0	0
T50	0	208830	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1494803392	1491409252	0	0
T1	1944	1548	0	0
T2	1190372	1190160	0	0
T3	1865500	1791412	0	0
T4	3410844	3410308	0	0
T5	188148	187840	0	0
T9	1602688	1602628	0	0
T10	5100	4172	0	0
T15	2303624	2302916	0	0
T16	264412	264096	0	0
T17	4800	4564	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373700848	372852313	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	373700848	102231153	0	0
GntImpliesValid_A	373700848	102231153	0	0
GrantKnown_A	373700848	372852313	0	0
IdxKnown_A	373700848	372852313	0	0
IndexIsCorrect_A	373700848	102231153	0	0
NoReadyValidNoGrant_A	373700848	44664226	0	0
Priority_A	373700848	108352997	0	0
ReadyAndValidImplyGrant_A	373700848	102231153	0	0
ReqAndReadyImplyGrant_A	373700848	102231153	0	0
ReqImpliesValid_A	373700848	108352997	0	0
ValidKnown_A	373700848	372852313	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102231153	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	14960	0	0
T5	47037	10224	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	8397	0	0
T16	66103	10855	0	0
T17	1200	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102231153	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	14960	0	0
T5	47037	10224	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	8397	0	0
T16	66103	10855	0	0
T17	1200	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102231153	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	14960	0	0
T5	47037	10224	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	8397	0	0
T16	66103	10855	0	0
T17	1200	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	44664226	0	0
T1	486	128	0	0
T2	297593	128	0	0
T3	466375	46352	0	0
T4	852711	471459	0	0
T5	47037	12901	0	0
T9	400672	530688	0	0
T10	1275	268	0	0
T15	575906	303131	0	0
T16	66103	30928	0	0
T17	1200	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	108352997	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	143076	0	0
T5	47037	13053	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	129935	0	0
T16	66103	11667	0	0
T17	1200	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102231153	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	14960	0	0
T5	47037	10224	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	8397	0	0
T16	66103	10855	0	0
T17	1200	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102231153	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	14960	0	0
T5	47037	10224	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	8397	0	0
T16	66103	10855	0	0
T17	1200	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	108352997	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	143076	0	0
T5	47037	13053	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	129935	0	0
T16	66103	11667	0	0
T17	1200	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373700848	372852313	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	373700848	102231087	0	0
GntImpliesValid_A	373700848	102231087	0	0
GrantKnown_A	373700848	372852313	0	0
IdxKnown_A	373700848	372852313	0	0
IndexIsCorrect_A	373700848	102231087	0	0
NoReadyValidNoGrant_A	373700848	44664227	0	0
Priority_A	373700848	108352930	0	0
ReadyAndValidImplyGrant_A	373700848	102231087	0	0
ReqAndReadyImplyGrant_A	373700848	102231087	0	0
ReqImpliesValid_A	373700848	108352930	0	0
ValidKnown_A	373700848	372852313	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102231087	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	14960	0	0
T5	47037	10224	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	8397	0	0
T16	66103	10855	0	0
T17	1200	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102231087	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	14960	0	0
T5	47037	10224	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	8397	0	0
T16	66103	10855	0	0
T17	1200	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102231087	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	14960	0	0
T5	47037	10224	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	8397	0	0
T16	66103	10855	0	0
T17	1200	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	44664227	0	0
T1	486	128	0	0
T2	297593	128	0	0
T3	466375	46352	0	0
T4	852711	471459	0	0
T5	47037	12901	0	0
T9	400672	530688	0	0
T10	1275	268	0	0
T15	575906	303131	0	0
T16	66103	30928	0	0
T17	1200	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	108352930	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	143076	0	0
T5	47037	13053	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	129935	0	0
T16	66103	11667	0	0
T17	1200	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102231087	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	14960	0	0
T5	47037	10224	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	8397	0	0
T16	66103	10855	0	0
T17	1200	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102231087	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	14960	0	0
T5	47037	10224	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	8397	0	0
T16	66103	10855	0	0
T17	1200	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	108352930	0	0
T1	486	32	0	0
T2	297593	158588	0	0
T3	466375	168278	0	0
T4	852711	143076	0	0
T5	47037	13053	0	0
T9	400672	129428	0	0
T10	1275	67	0	0
T15	575906	129935	0	0
T16	66103	11667	0	0
T17	1200	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T4
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T2,T5,T4
1	1	Covered	T1,T5,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T2,T5,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373700848	372852313	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	373700848	96876194	0	0
GntImpliesValid_A	373700848	96876194	0	0
GrantKnown_A	373700848	372852313	0	0
IdxKnown_A	373700848	372852313	0	0
IndexIsCorrect_A	373700848	96876194	0	0
NoReadyValidNoGrant_A	373700848	41423754	0	0
Priority_A	373700848	102823338	0	0
ReadyAndValidImplyGrant_A	373700848	96876194	0	0
ReqAndReadyImplyGrant_A	373700848	96876194	0	0
ReqImpliesValid_A	373700848	102823338	0	0
ValidKnown_A	373700848	372852313	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	96876194	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	14996	0	0
T5	47037	10481	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	8228	0	0
T16	66103	11066	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	11670	0	0
T21	0	8454	0	0
T50	0	104415	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	96876194	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	14996	0	0
T5	47037	10481	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	8228	0	0
T16	66103	11066	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	11670	0	0
T21	0	8454	0	0
T50	0	104415	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	96876194	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	14996	0	0
T5	47037	10481	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	8228	0	0
T16	66103	11066	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	11670	0	0
T21	0	8454	0	0
T50	0	104415	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	41423754	0	0
T4	852711	462442	0	0
T5	47037	13656	0	0
T9	400672	524288	0	0
T10	1275	0	0	0
T15	575906	300027	0	0
T16	66103	31582	0	0
T17	1200	0	0	0
T18	30009	606	0	0
T20	0	14291	0	0
T21	0	12986	0	0
T29	199146	0	0	0
T36	0	286	0	0
T50	182307	0	0	0
T52	0	524372	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102823338	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	167452	0	0
T5	47037	13009	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	124283	0	0
T16	66103	11810	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	19154	0	0
T21	0	10663	0	0
T50	0	104415	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	96876194	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	14996	0	0
T5	47037	10481	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	8228	0	0
T16	66103	11066	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	11670	0	0
T21	0	8454	0	0
T50	0	104415	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	96876194	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	14996	0	0
T5	47037	10481	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	8228	0	0
T16	66103	11066	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	11670	0	0
T21	0	8454	0	0
T50	0	104415	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102823338	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	167452	0	0
T5	47037	13009	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	124283	0	0
T16	66103	11810	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	19154	0	0
T21	0	10663	0	0
T50	0	104415	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T4
1	0	Covered	T1,T5,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T2,T5,T4
1	1	Covered	T1,T5,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T2,T5,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373700848	372852313	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	373700848	96876046	0	0
GntImpliesValid_A	373700848	96876046	0	0
GrantKnown_A	373700848	372852313	0	0
IdxKnown_A	373700848	372852313	0	0
IndexIsCorrect_A	373700848	96876046	0	0
NoReadyValidNoGrant_A	373700848	41423755	0	0
Priority_A	373700848	102823189	0	0
ReadyAndValidImplyGrant_A	373700848	96876046	0	0
ReqAndReadyImplyGrant_A	373700848	96876046	0	0
ReqImpliesValid_A	373700848	102823189	0	0
ValidKnown_A	373700848	372852313	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	96876046	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	14996	0	0
T5	47037	10481	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	8228	0	0
T16	66103	11066	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	11670	0	0
T21	0	8454	0	0
T50	0	104415	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	96876046	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	14996	0	0
T5	47037	10481	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	8228	0	0
T16	66103	11066	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	11670	0	0
T21	0	8454	0	0
T50	0	104415	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	96876046	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	14996	0	0
T5	47037	10481	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	8228	0	0
T16	66103	11066	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	11670	0	0
T21	0	8454	0	0
T50	0	104415	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	41423755	0	0
T4	852711	462442	0	0
T5	47037	13656	0	0
T9	400672	524288	0	0
T10	1275	0	0	0
T15	575906	300027	0	0
T16	66103	31582	0	0
T17	1200	0	0	0
T18	30009	606	0	0
T20	0	14291	0	0
T21	0	12986	0	0
T29	199146	0	0	0
T36	0	286	0	0
T50	182307	0	0	0
T52	0	524372	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102823189	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	167452	0	0
T5	47037	13009	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	124283	0	0
T16	66103	11810	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	19154	0	0
T21	0	10663	0	0
T50	0	104415	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	96876046	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	14996	0	0
T5	47037	10481	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	8228	0	0
T16	66103	11066	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	11670	0	0
T21	0	8454	0	0
T50	0	104415	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	96876046	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	14996	0	0
T5	47037	10481	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	8228	0	0
T16	66103	11066	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	11670	0	0
T21	0	8454	0	0
T50	0	104415	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	102823189	0	0
T2	297593	105726	0	0
T3	466375	0	0	0
T4	852711	167452	0	0
T5	47037	13009	0	0
T9	400672	127897	0	0
T10	1275	0	0	0
T15	575906	124283	0	0
T16	66103	11810	0	0
T17	1200	0	0	0
T18	30009	6178	0	0
T20	0	19154	0	0
T21	0	10663	0	0
T50	0	104415	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373700848	372852313	0	0
T1	486	387	0	0
T2	297593	297540	0	0
T3	466375	447853	0	0
T4	852711	852577	0	0
T5	47037	46960	0	0
T9	400672	400657	0	0
T10	1275	1043	0	0
T15	575906	575729	0	0
T16	66103	66024	0	0
T17	1200	1141	0	0