Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
2147483647 |
2147483647 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
5964 |
4776 |
0 |
0 |
T2 |
3571116 |
3570480 |
0 |
0 |
T3 |
5596500 |
5374236 |
0 |
0 |
T4 |
10232532 |
10230924 |
0 |
0 |
T5 |
564444 |
563520 |
0 |
0 |
T9 |
4808064 |
4807884 |
0 |
0 |
T10 |
15300 |
12516 |
0 |
0 |
T15 |
6910872 |
6908748 |
0 |
0 |
T16 |
793236 |
792288 |
0 |
0 |
T17 |
14400 |
13692 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
373700924 |
372852389 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
373700924 |
372852389 |
0 |
0 |
T1 |
497 |
398 |
0 |
0 |
T2 |
297593 |
297540 |
0 |
0 |
T3 |
466375 |
447853 |
0 |
0 |
T4 |
852711 |
852577 |
0 |
0 |
T5 |
47037 |
46960 |
0 |
0 |
T9 |
400672 |
400657 |
0 |
0 |
T10 |
1275 |
1043 |
0 |
0 |
T15 |
575906 |
575729 |
0 |
0 |
T16 |
66103 |
66024 |
0 |
0 |
T17 |
1200 |
1141 |
0 |
0 |