SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.69 | 97.12 | 93.60 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.75 | 100.00 | 92.71 | 92.11 | 98.94 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.37 | 100.00 | 88.89 | 57.14 | 95.83 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.69 | 97.12 | 93.60 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
80.60 | 100.00 | 100.00 | 57.14 | 95.83 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.56 | 97.67 | 86.00 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10460 | 10460 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 21714 |
gen_no_flops.OutputDelay_A | 735437362 | 733740292 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10460 | 10460 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T5 | 10 | 10 | 0 | 0 |
T9 | 10 | 10 | 0 | 0 |
T10 | 10 | 10 | 0 | 0 |
T15 | 10 | 10 | 0 | 0 |
T16 | 10 | 10 | 0 | 0 |
T17 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 4937 | 3947 | 0 | 0 |
T2 | 2975930 | 2975400 | 0 | 0 |
T3 | 4663750 | 4478530 | 0 | 0 |
T4 | 8527110 | 8525770 | 0 | 0 |
T5 | 470370 | 469600 | 0 | 0 |
T9 | 4006720 | 4006570 | 0 | 0 |
T10 | 12750 | 10430 | 0 | 0 |
T15 | 5759060 | 5757290 | 0 | 0 |
T16 | 661030 | 660240 | 0 | 0 |
T17 | 4810 | 4220 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 21714 |
T1 | 3965 | 3152 | 0 | 0 |
T2 | 2380744 | 2380296 | 0 | 24 |
T3 | 3731000 | 3576872 | 0 | 24 |
T4 | 6821688 | 6820568 | 0 | 24 |
T5 | 376296 | 375656 | 0 | 24 |
T9 | 3205376 | 3205248 | 0 | 24 |
T10 | 10200 | 8272 | 0 | 24 |
T15 | 4607248 | 4605784 | 0 | 24 |
T16 | 528824 | 528168 | 0 | 24 |
T17 | 3848 | 3376 | 0 | 0 |
T18 | 0 | 0 | 0 | 24 |
T50 | 0 | 0 | 0 | 24 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 735437362 | 733740292 | 0 | 0 |
T1 | 972 | 774 | 0 | 0 |
T2 | 595186 | 595080 | 0 | 0 |
T3 | 932750 | 895706 | 0 | 0 |
T4 | 1705422 | 1705154 | 0 | 0 |
T5 | 94074 | 93920 | 0 | 0 |
T9 | 801344 | 801314 | 0 | 0 |
T10 | 2550 | 2086 | 0 | 0 |
T15 | 1151812 | 1151458 | 0 | 0 |
T16 | 132206 | 132048 | 0 | 0 |
T17 | 962 | 844 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1046 | 1046 | 0 | 0 |
OutputsKnown_A | 367718757 | 366870222 | 0 | 0 |
gen_flops.OutputDelay_A | 367718757 | 366836730 | 0 | 2733 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366870222 | 0 | 0 |
T1 | 497 | 398 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366836730 | 0 | 2733 |
T1 | 497 | 395 | 0 | 0 |
T2 | 297593 | 297537 | 0 | 3 |
T3 | 466375 | 447109 | 0 | 3 |
T4 | 852711 | 852571 | 0 | 3 |
T5 | 47037 | 46957 | 0 | 3 |
T9 | 400672 | 400656 | 0 | 3 |
T10 | 1275 | 1034 | 0 | 3 |
T15 | 575906 | 575723 | 0 | 3 |
T16 | 66103 | 66021 | 0 | 3 |
T17 | 481 | 422 | 0 | 0 |
T18 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1046 | 1046 | 0 | 0 |
OutputsKnown_A | 367718757 | 366870222 | 0 | 0 |
gen_flops.OutputDelay_A | 367718757 | 366836730 | 0 | 2733 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366870222 | 0 | 0 |
T1 | 497 | 398 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366836730 | 0 | 2733 |
T1 | 497 | 395 | 0 | 0 |
T2 | 297593 | 297537 | 0 | 3 |
T3 | 466375 | 447109 | 0 | 3 |
T4 | 852711 | 852571 | 0 | 3 |
T5 | 47037 | 46957 | 0 | 3 |
T9 | 400672 | 400656 | 0 | 3 |
T10 | 1275 | 1034 | 0 | 3 |
T15 | 575906 | 575723 | 0 | 3 |
T16 | 66103 | 66021 | 0 | 3 |
T17 | 481 | 422 | 0 | 0 |
T18 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1046 | 1046 | 0 | 0 |
OutputsKnown_A | 367718757 | 366870222 | 0 | 0 |
gen_flops.OutputDelay_A | 367718757 | 366836730 | 0 | 2733 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366870222 | 0 | 0 |
T1 | 497 | 398 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366836730 | 0 | 2733 |
T1 | 497 | 395 | 0 | 0 |
T2 | 297593 | 297537 | 0 | 3 |
T3 | 466375 | 447109 | 0 | 3 |
T4 | 852711 | 852571 | 0 | 3 |
T5 | 47037 | 46957 | 0 | 3 |
T9 | 400672 | 400656 | 0 | 3 |
T10 | 1275 | 1034 | 0 | 3 |
T15 | 575906 | 575723 | 0 | 3 |
T16 | 66103 | 66021 | 0 | 3 |
T17 | 481 | 422 | 0 | 0 |
T18 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1046 | 1046 | 0 | 0 |
OutputsKnown_A | 367718757 | 366870222 | 0 | 0 |
gen_flops.OutputDelay_A | 367718757 | 366836730 | 0 | 2733 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366870222 | 0 | 0 |
T1 | 497 | 398 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366836730 | 0 | 2733 |
T1 | 497 | 395 | 0 | 0 |
T2 | 297593 | 297537 | 0 | 3 |
T3 | 466375 | 447109 | 0 | 3 |
T4 | 852711 | 852571 | 0 | 3 |
T5 | 47037 | 46957 | 0 | 3 |
T9 | 400672 | 400656 | 0 | 3 |
T10 | 1275 | 1034 | 0 | 3 |
T15 | 575906 | 575723 | 0 | 3 |
T16 | 66103 | 66021 | 0 | 3 |
T17 | 481 | 422 | 0 | 0 |
T18 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1046 | 1046 | 0 | 0 |
OutputsKnown_A | 367718757 | 366870222 | 0 | 0 |
gen_flops.OutputDelay_A | 367718757 | 366836730 | 0 | 2733 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366870222 | 0 | 0 |
T1 | 497 | 398 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366836730 | 0 | 2733 |
T1 | 497 | 395 | 0 | 0 |
T2 | 297593 | 297537 | 0 | 3 |
T3 | 466375 | 447109 | 0 | 3 |
T4 | 852711 | 852571 | 0 | 3 |
T5 | 47037 | 46957 | 0 | 3 |
T9 | 400672 | 400656 | 0 | 3 |
T10 | 1275 | 1034 | 0 | 3 |
T15 | 575906 | 575723 | 0 | 3 |
T16 | 66103 | 66021 | 0 | 3 |
T17 | 481 | 422 | 0 | 0 |
T18 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1046 | 1046 | 0 | 0 |
OutputsKnown_A | 367718757 | 366870222 | 0 | 0 |
gen_flops.OutputDelay_A | 367718757 | 366836730 | 0 | 2733 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366870222 | 0 | 0 |
T1 | 497 | 398 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718757 | 366836730 | 0 | 2733 |
T1 | 497 | 395 | 0 | 0 |
T2 | 297593 | 297537 | 0 | 3 |
T3 | 466375 | 447109 | 0 | 3 |
T4 | 852711 | 852571 | 0 | 3 |
T5 | 47037 | 46957 | 0 | 3 |
T9 | 400672 | 400656 | 0 | 3 |
T10 | 1275 | 1034 | 0 | 3 |
T15 | 575906 | 575723 | 0 | 3 |
T16 | 66103 | 66021 | 0 | 3 |
T17 | 481 | 422 | 0 | 0 |
T18 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1046 | 1046 | 0 | 0 |
OutputsKnown_A | 367718681 | 366870146 | 0 | 0 |
gen_no_flops.OutputDelay_A | 367718681 | 366870146 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718681 | 366870146 | 0 | 0 |
T1 | 486 | 387 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718681 | 366870146 | 0 | 0 |
T1 | 486 | 387 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1046 | 1046 | 0 | 0 |
OutputsKnown_A | 367697325 | 366848790 | 0 | 0 |
gen_flops.OutputDelay_A | 367697325 | 366815448 | 0 | 2583 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367697325 | 366848790 | 0 | 0 |
T1 | 497 | 398 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367697325 | 366815448 | 0 | 2583 |
T1 | 497 | 395 | 0 | 0 |
T2 | 297593 | 297537 | 0 | 3 |
T3 | 466375 | 447109 | 0 | 3 |
T4 | 852711 | 852571 | 0 | 3 |
T5 | 47037 | 46957 | 0 | 3 |
T9 | 400672 | 400656 | 0 | 3 |
T10 | 1275 | 1034 | 0 | 3 |
T15 | 575906 | 575723 | 0 | 3 |
T16 | 66103 | 66021 | 0 | 3 |
T17 | 481 | 422 | 0 | 0 |
T18 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1046 | 1046 | 0 | 0 |
OutputsKnown_A | 367718681 | 366870146 | 0 | 0 |
gen_no_flops.OutputDelay_A | 367718681 | 366870146 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718681 | 366870146 | 0 | 0 |
T1 | 486 | 387 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718681 | 366870146 | 0 | 0 |
T1 | 486 | 387 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1046 | 1046 | 0 | 0 |
OutputsKnown_A | 367718681 | 366870146 | 0 | 0 |
gen_flops.OutputDelay_A | 367718681 | 366836669 | 0 | 2733 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718681 | 366870146 | 0 | 0 |
T1 | 486 | 387 | 0 | 0 |
T2 | 297593 | 297540 | 0 | 0 |
T3 | 466375 | 447853 | 0 | 0 |
T4 | 852711 | 852577 | 0 | 0 |
T5 | 47037 | 46960 | 0 | 0 |
T9 | 400672 | 400657 | 0 | 0 |
T10 | 1275 | 1043 | 0 | 0 |
T15 | 575906 | 575729 | 0 | 0 |
T16 | 66103 | 66024 | 0 | 0 |
T17 | 481 | 422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 367718681 | 366836669 | 0 | 2733 |
T1 | 486 | 387 | 0 | 0 |
T2 | 297593 | 297537 | 0 | 3 |
T3 | 466375 | 447109 | 0 | 3 |
T4 | 852711 | 852571 | 0 | 3 |
T5 | 47037 | 46957 | 0 | 3 |
T9 | 400672 | 400656 | 0 | 3 |
T10 | 1275 | 1034 | 0 | 3 |
T15 | 575906 | 575723 | 0 | 3 |
T16 | 66103 | 66021 | 0 | 3 |
T17 | 481 | 422 | 0 | 0 |
T18 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |