SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 97.22 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] | 91.67 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
91.67 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 2 | 12 | 91.67 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 1 | 3 | 75.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | |||
auto[1] | 4001932 | 0 | T5 | 41477 | T7 | 16360 | T8 | 16034 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 1 | 3 | 75.00 |
NAME | COUNT | AT LEAST | NUMBER |
values[2] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4001774 | 1 | T5 | 41477 | T7 | 16360 | T8 | 16034 | |||
values[1] | 14 | 1 | T103 | 1 | T240 | 2 | T242 | 1 | |||
values[3] | 78 | 1 | T103 | 5 | T232 | 3 | T240 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4001752 | 1 | T5 | 41477 | T7 | 16360 | T8 | 16034 | |||
values[1] | 24 | 1 | T103 | 1 | T232 | 2 | T242 | 1 | |||
values[2] | 4 | 1 | T239 | 1 | T267 | 1 | T347 | 1 | |||
values[3] | 97 | 1 | T103 | 2 | T232 | 3 | T240 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4001676 | 1 | T5 | 41477 | T7 | 16360 | T8 | 16034 | |||
auto[TlIntgErrCmd] | 76 | 1 | T103 | 7 | T232 | 2 | T240 | 1 | |||
auto[TlIntgErrData] | 98 | 1 | T103 | 2 | T232 | 2 | T240 | 5 | |||
auto[TlIntgErrBoth] | 82 | 1 | T103 | 1 | T232 | 6 | T240 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 28608713 | 1 | T1 | 165 | T2 | 161 | T3 | 12569 | |||
auto[1] | 5588419 | 1 | T3 | 7996 | T4 | 21735 | T5 | 15917 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 34196964 | 1 | T1 | 165 | T2 | 161 | T3 | 20565 | |||
values[1] | 19 | 1 | T232 | 1 | T240 | 1 | T239 | 1 | |||
values[2] | 2 | 1 | T348 | 2 | - | - | - | - | |||
values[3] | 81 | 1 | T103 | 4 | T232 | 3 | T240 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 34196948 | 1 | T1 | 165 | T2 | 161 | T3 | 20565 | |||
values[1] | 19 | 1 | T103 | 2 | T240 | 2 | T239 | 2 | |||
values[2] | 6 | 1 | T232 | 1 | T243 | 1 | T241 | 1 | |||
values[3] | 98 | 1 | T103 | 4 | T232 | 5 | T240 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 34196862 | 1 | T1 | 165 | T2 | 161 | T3 | 20565 | |||
auto[TlIntgErrCmd] | 86 | 1 | T103 | 3 | T232 | 2 | T240 | 5 | |||
auto[TlIntgErrData] | 102 | 1 | T103 | 4 | T232 | 5 | T240 | 3 | |||
auto[TlIntgErrBoth] | 82 | 1 | T103 | 3 | T232 | 3 | T240 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 82813 | 0 | T69 | 621 | T100 | 1193 | T101 | 123 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 82636 | 1 | T69 | 621 | T100 | 1193 | T101 | 123 | |||
values[1] | 21 | 1 | T240 | 1 | T239 | 2 | T242 | 3 | |||
values[2] | 2 | 1 | T103 | 1 | T242 | 1 | - | - | |||
values[3] | 92 | 1 | T103 | 3 | T232 | 5 | T240 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 82633 | 1 | T69 | 621 | T100 | 1193 | T101 | 123 | |||
values[1] | 19 | 1 | T232 | 1 | T242 | 3 | T243 | 2 | |||
values[2] | 11 | 1 | T232 | 1 | T242 | 2 | T241 | 1 | |||
values[3] | 87 | 1 | T103 | 1 | T232 | 4 | T240 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 82543 | 1 | T69 | 621 | T100 | 1193 | T101 | 123 | |||
auto[TlIntgErrCmd] | 90 | 1 | T103 | 6 | T232 | 3 | T240 | 6 | |||
auto[TlIntgErrData] | 93 | 1 | T103 | 1 | T232 | 5 | T240 | 3 | |||
auto[TlIntgErrBoth] | 87 | 1 | T103 | 3 | T232 | 2 | T240 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |