SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 97.92 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] | 95.83 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
95.83 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
Crosses | 16 | 1 | 15 | 93.75 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_num_num_enable_bytes | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_write | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
cr_all | 16 | 1 | 15 | 93.75 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
Crosses | 16 | 0 | 16 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_num_num_enable_bytes | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_write | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
cr_all | 16 | 0 | 16 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
partial | 18177 | 1 | T69 | 222 | T100 | 1057 | T102 | 66 | |||
full_word | 3983755 | 1 | T5 | 41477 | T7 | 16360 | T8 | 16034 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4001676 | 1 | T5 | 41477 | T7 | 16360 | T8 | 16034 | |||
auto[TlIntgErrCmd] | 76 | 1 | T103 | 7 | T232 | 2 | T240 | 1 | |||
auto[TlIntgErrData] | 98 | 1 | T103 | 2 | T232 | 2 | T240 | 5 | |||
auto[TlIntgErrBoth] | 82 | 1 | T103 | 1 | T232 | 6 | T240 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 3979184 | 1 | T5 | 41477 | T7 | 16360 | T8 | 16034 | |||
auto[1] | 22748 | 1 | T69 | 393 | T100 | 1526 | T102 | 81 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 16 | 1 | 15 | 93.75 | 1 |
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | NUMBER |
[auto[TlIntgErrBoth]] | [full_word] | [auto[1]] | 0 | 1 | 1 |
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | partial | auto[0] | 1234 | 1 | T69 | 8 | T100 | 77 | T102 | 7 | |||
auto[TlIntgErrNone] | partial | auto[1] | 16709 | 1 | T69 | 214 | T100 | 980 | T102 | 59 | |||
auto[TlIntgErrNone] | full_word | auto[0] | 3977839 | 1 | T5 | 41477 | T7 | 16360 | T8 | 16034 | |||
auto[TlIntgErrNone] | full_word | auto[1] | 5894 | 1 | T69 | 179 | T100 | 546 | T102 | 22 | |||
auto[TlIntgErrCmd] | partial | auto[0] | 27 | 1 | T103 | 1 | T239 | 1 | T243 | 2 | |||
auto[TlIntgErrCmd] | partial | auto[1] | 39 | 1 | T103 | 6 | T232 | 2 | T239 | 3 | |||
auto[TlIntgErrCmd] | full_word | auto[0] | 4 | 1 | T267 | 1 | T349 | 1 | T348 | 1 | |||
auto[TlIntgErrCmd] | full_word | auto[1] | 6 | 1 | T240 | 1 | T241 | 1 | T350 | 2 | |||
auto[TlIntgErrData] | partial | auto[0] | 46 | 1 | T103 | 1 | T232 | 2 | T240 | 4 | |||
auto[TlIntgErrData] | partial | auto[1] | 44 | 1 | T103 | 1 | T240 | 1 | T239 | 3 | |||
auto[TlIntgErrData] | full_word | auto[0] | 3 | 1 | T239 | 1 | T351 | 1 | T352 | 1 | |||
auto[TlIntgErrData] | full_word | auto[1] | 5 | 1 | T241 | 1 | T353 | 1 | T347 | 1 | |||
auto[TlIntgErrBoth] | partial | auto[0] | 27 | 1 | T232 | 1 | T240 | 1 | T239 | 1 | |||
auto[TlIntgErrBoth] | partial | auto[1] | 51 | 1 | T103 | 1 | T232 | 5 | T240 | 2 | |||
auto[TlIntgErrBoth] | full_word | auto[0] | 4 | 1 | T241 | 1 | T353 | 1 | T348 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
partial | 25927287 | 1 | T1 | 162 | T2 | 122 | T3 | 5400 | |||
full_word | 8269845 | 1 | T1 | 3 | T2 | 39 | T3 | 15165 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 34196862 | 1 | T1 | 165 | T2 | 161 | T3 | 20565 | |||
auto[TlIntgErrCmd] | 86 | 1 | T103 | 3 | T232 | 2 | T240 | 5 | |||
auto[TlIntgErrData] | 102 | 1 | T103 | 4 | T232 | 5 | T240 | 3 | |||
auto[TlIntgErrBoth] | 82 | 1 | T103 | 3 | T232 | 3 | T240 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 29468297 | 1 | T1 | 156 | T2 | 115 | T3 | 4732 | |||
auto[1] | 4728835 | 1 | T1 | 9 | T2 | 46 | T3 | 15833 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 16 | 0 | 16 | 100.00 |
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | partial | auto[0] | 25090211 | 1 | T1 | 156 | T2 | 115 | T3 | 2457 | |||
auto[TlIntgErrNone] | partial | auto[1] | 836830 | 1 | T1 | 6 | T2 | 7 | T3 | 2943 | |||
auto[TlIntgErrNone] | full_word | auto[0] | 4377979 | 1 | T3 | 2275 | T4 | 11306 | T5 | 9046 | |||
auto[TlIntgErrNone] | full_word | auto[1] | 3891842 | 1 | T1 | 3 | T2 | 39 | T3 | 12890 | |||
auto[TlIntgErrCmd] | partial | auto[0] | 30 | 1 | T103 | 2 | T232 | 1 | T240 | 2 | |||
auto[TlIntgErrCmd] | partial | auto[1] | 46 | 1 | T103 | 1 | T232 | 1 | T240 | 3 | |||
auto[TlIntgErrCmd] | full_word | auto[0] | 1 | 1 | T354 | 1 | - | - | - | - | |||
auto[TlIntgErrCmd] | full_word | auto[1] | 9 | 1 | T242 | 1 | T241 | 1 | T355 | 1 | |||
auto[TlIntgErrData] | partial | auto[0] | 40 | 1 | T232 | 1 | T239 | 1 | T242 | 3 | |||
auto[TlIntgErrData] | partial | auto[1] | 53 | 1 | T103 | 4 | T232 | 3 | T240 | 3 | |||
auto[TlIntgErrData] | full_word | auto[0] | 6 | 1 | T232 | 1 | T242 | 1 | T267 | 1 | |||
auto[TlIntgErrData] | full_word | auto[1] | 3 | 1 | T239 | 2 | T348 | 1 | - | - | |||
auto[TlIntgErrBoth] | partial | auto[0] | 28 | 1 | T103 | 2 | T232 | 2 | T239 | 2 | |||
auto[TlIntgErrBoth] | partial | auto[1] | 49 | 1 | T103 | 1 | T232 | 1 | T240 | 2 | |||
auto[TlIntgErrBoth] | full_word | auto[0] | 2 | 1 | T242 | 1 | T348 | 1 | - | - | |||
auto[TlIntgErrBoth] | full_word | auto[1] | 3 | 1 | T241 | 1 | T349 | 1 | T276 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |