Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1501874668	1498445028	0	0
CheckNGreaterZero_A	4164	4164	0	0
GntImpliesReady_A	1501874668	395134710	0	0
GntImpliesValid_A	1501874668	395134710	0	0
GrantKnown_A	1501874668	1498445028	0	0
IdxKnown_A	1501874668	1498445028	0	0
IndexIsCorrect_A	1501874668	395134710	0	0
NoReadyValidNoGrant_A	1501874668	190147591	0	0
Priority_A	1501874668	418820135	0	0
ReadyAndValidImplyGrant_A	1501874668	395134710	0	0
ReqAndReadyImplyGrant_A	1501874668	395134710	0	0
ReqImpliesValid_A	1501874668	418820135	0	0
ValidKnown_A	1501874668	1498445028	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	1498445028	0	0
T1	16268	13604	0	0
T2	642312	641676	0	0
T3	898304	898272	0	0
T4	3988148	3987924	0	0
T5	1309600	1309344	0	0
T6	8992	8768	0	0
T7	204544	204344	0	0
T12	15776	12872	0	0
T21	9120	8748	0	0
T22	3772	3540	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4164	4164	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T12	4	4	0	0
T21	4	4	0	0
T22	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	395134710	0	0
T1	8134	478	0	0
T2	321156	756	0	0
T3	898304	2227160	0	0
T4	3988148	1039312	0	0
T5	1309600	399288	0	0
T6	8992	564	0	0
T7	204544	42146	0	0
T8	106686	21638	0	0
T12	15776	364	0	0
T21	9120	64	0	0
T22	3772	64	0	0
T23	0	2186	0	0
T52	0	700	0	0
T57	0	30	0	0
T60	3940	0	0	0
T63	0	20724	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	395134710	0	0
T1	8134	478	0	0
T2	321156	756	0	0
T3	898304	2227160	0	0
T4	3988148	1039312	0	0
T5	1309600	399288	0	0
T6	8992	564	0	0
T7	204544	42146	0	0
T8	106686	21638	0	0
T12	15776	364	0	0
T21	9120	64	0	0
T22	3772	64	0	0
T23	0	2186	0	0
T52	0	700	0	0
T57	0	30	0	0
T60	3940	0	0	0
T63	0	20724	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	1498445028	0	0
T1	16268	13604	0	0
T2	642312	641676	0	0
T3	898304	898272	0	0
T4	3988148	3987924	0	0
T5	1309600	1309344	0	0
T6	8992	8768	0	0
T7	204544	204344	0	0
T12	15776	12872	0	0
T21	9120	8748	0	0
T22	3772	3540	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	1498445028	0	0
T1	16268	13604	0	0
T2	642312	641676	0	0
T3	898304	898272	0	0
T4	3988148	3987924	0	0
T5	1309600	1309344	0	0
T6	8992	8768	0	0
T7	204544	204344	0	0
T12	15776	12872	0	0
T21	9120	8748	0	0
T22	3772	3540	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	395134710	0	0
T1	8134	478	0	0
T2	321156	756	0	0
T3	898304	2227160	0	0
T4	3988148	1039312	0	0
T5	1309600	399288	0	0
T6	8992	564	0	0
T7	204544	42146	0	0
T8	106686	21638	0	0
T12	15776	364	0	0
T21	9120	64	0	0
T22	3772	64	0	0
T23	0	2186	0	0
T52	0	700	0	0
T57	0	30	0	0
T60	3940	0	0	0
T63	0	20724	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	190147591	0	0
T1	8134	1792	0	0
T2	321156	256	0	0
T3	449152	3392	0	0
T4	3988148	13182	0	0
T5	1309600	177522	0	0
T6	8992	256	0	0
T7	204544	55212	0	0
T8	106686	27754	0	0
T12	15776	1354	0	0
T21	9120	256	0	0
T22	3772	256	0	0
T23	8792	82	0	0
T27	0	1231870	0	0
T42	0	64224	0	0
T52	0	1056	0	0
T57	0	34	0	0
T58	0	1366	0	0
T60	3940	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	418820135	0	0
T1	8134	478	0	0
T2	321156	756	0	0
T3	898304	2227160	0	0
T4	3988148	1039312	0	0
T5	1309600	518300	0	0
T6	8992	564	0	0
T7	204544	53082	0	0
T8	106686	26994	0	0
T12	15776	364	0	0
T21	9120	64	0	0
T22	3772	64	0	0
T23	0	2186	0	0
T52	0	700	0	0
T57	0	38	0	0
T60	3940	0	0	0
T63	0	20724	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	395134710	0	0
T1	8134	478	0	0
T2	321156	756	0	0
T3	898304	2227160	0	0
T4	3988148	1039312	0	0
T5	1309600	399288	0	0
T6	8992	564	0	0
T7	204544	42146	0	0
T8	106686	21638	0	0
T12	15776	364	0	0
T21	9120	64	0	0
T22	3772	64	0	0
T23	0	2186	0	0
T52	0	700	0	0
T57	0	30	0	0
T60	3940	0	0	0
T63	0	20724	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	395134710	0	0
T1	8134	478	0	0
T2	321156	756	0	0
T3	898304	2227160	0	0
T4	3988148	1039312	0	0
T5	1309600	399288	0	0
T6	8992	564	0	0
T7	204544	42146	0	0
T8	106686	21638	0	0
T12	15776	364	0	0
T21	9120	64	0	0
T22	3772	64	0	0
T23	0	2186	0	0
T52	0	700	0	0
T57	0	30	0	0
T60	3940	0	0	0
T63	0	20724	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	418820135	0	0
T1	8134	478	0	0
T2	321156	756	0	0
T3	898304	2227160	0	0
T4	3988148	1039312	0	0
T5	1309600	518300	0	0
T6	8992	564	0	0
T7	204544	53082	0	0
T8	106686	26994	0	0
T12	15776	364	0	0
T21	9120	64	0	0
T22	3772	64	0	0
T23	0	2186	0	0
T52	0	700	0	0
T57	0	38	0	0
T60	3940	0	0	0
T63	0	20724	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501874668	1498445028	0	0
T1	16268	13604	0	0
T2	642312	641676	0	0
T3	898304	898272	0	0
T4	3988148	3987924	0	0
T5	1309600	1309344	0	0
T6	8992	8768	0	0
T7	204544	204344	0	0
T12	15776	12872	0	0
T21	9120	8748	0	0
T22	3772	3540	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375468667	374611257	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	375468667	106040403	0	0
GntImpliesValid_A	375468667	106040403	0	0
GrantKnown_A	375468667	374611257	0	0
IdxKnown_A	375468667	374611257	0	0
IndexIsCorrect_A	375468667	106040403	0	0
NoReadyValidNoGrant_A	375468667	48897620	0	0
Priority_A	375468667	112005784	0	0
ReadyAndValidImplyGrant_A	375468667	106040403	0	0
ReqAndReadyImplyGrant_A	375468667	106040403	0	0
ReqImpliesValid_A	375468667	112005784	0	0
ValidKnown_A	375468667	374611257	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	106040403	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	128797	0	0
T6	2248	32	0	0
T7	51136	10679	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	106040403	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	128797	0	0
T6	2248	32	0	0
T7	51136	10679	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	106040403	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	128797	0	0
T6	2248	32	0	0
T7	51136	10679	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	48897620	0	0
T1	4067	896	0	0
T2	160578	128	0	0
T3	224576	1696	0	0
T4	997037	1829	0	0
T5	327400	53987	0	0
T6	2248	128	0	0
T7	51136	14864	0	0
T12	3944	677	0	0
T21	2280	128	0	0
T22	943	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	112005784	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	166902	0	0
T6	2248	32	0	0
T7	51136	13126	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	106040403	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	128797	0	0
T6	2248	32	0	0
T7	51136	10679	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	106040403	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	128797	0	0
T6	2248	32	0	0
T7	51136	10679	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	112005784	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	166902	0	0
T6	2248	32	0	0
T7	51136	13126	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375468667	374611257	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	375468667	106040332	0	0
GntImpliesValid_A	375468667	106040332	0	0
GrantKnown_A	375468667	374611257	0	0
IdxKnown_A	375468667	374611257	0	0
IndexIsCorrect_A	375468667	106040332	0	0
NoReadyValidNoGrant_A	375468667	48897621	0	0
Priority_A	375468667	112005712	0	0
ReadyAndValidImplyGrant_A	375468667	106040332	0	0
ReqAndReadyImplyGrant_A	375468667	106040332	0	0
ReqImpliesValid_A	375468667	112005712	0	0
ValidKnown_A	375468667	374611257	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	106040332	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	128797	0	0
T6	2248	32	0	0
T7	51136	10679	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	106040332	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	128797	0	0
T6	2248	32	0	0
T7	51136	10679	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	106040332	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	128797	0	0
T6	2248	32	0	0
T7	51136	10679	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	48897621	0	0
T1	4067	896	0	0
T2	160578	128	0	0
T3	224576	1696	0	0
T4	997037	1829	0	0
T5	327400	53987	0	0
T6	2248	128	0	0
T7	51136	14864	0	0
T12	3944	677	0	0
T21	2280	128	0	0
T22	943	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	112005712	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	166902	0	0
T6	2248	32	0	0
T7	51136	13126	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	106040332	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	128797	0	0
T6	2248	32	0	0
T7	51136	10679	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	106040332	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	128797	0	0
T6	2248	32	0	0
T7	51136	10679	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	112005712	0	0
T1	4067	239	0	0
T2	160578	378	0	0
T3	224576	122520	0	0
T4	997037	503200	0	0
T5	327400	166902	0	0
T6	2248	32	0	0
T7	51136	13126	0	0
T12	3944	182	0	0
T21	2280	32	0	0
T22	943	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T5,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375468667	374611257	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	375468667	91527026	0	0
GntImpliesValid_A	375468667	91527026	0	0
GrantKnown_A	375468667	374611257	0	0
IdxKnown_A	375468667	374611257	0	0
IndexIsCorrect_A	375468667	91527026	0	0
NoReadyValidNoGrant_A	375468667	46176175	0	0
Priority_A	375468667	97404358	0	0
ReadyAndValidImplyGrant_A	375468667	91527026	0	0
ReqAndReadyImplyGrant_A	375468667	91527026	0	0
ReqImpliesValid_A	375468667	97404358	0	0
ValidKnown_A	375468667	374611257	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	91527026	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	70847	0	0
T6	2248	250	0	0
T7	51136	10394	0	0
T8	53343	10819	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	15	0	0
T60	1970	0	0	0
T63	0	10362	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	91527026	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	70847	0	0
T6	2248	250	0	0
T7	51136	10394	0	0
T8	53343	10819	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	15	0	0
T60	1970	0	0	0
T63	0	10362	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	91527026	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	70847	0	0
T6	2248	250	0	0
T7	51136	10394	0	0
T8	53343	10819	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	15	0	0
T60	1970	0	0	0
T63	0	10362	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	46176175	0	0
T4	997037	4762	0	0
T5	327400	34774	0	0
T6	2248	0	0	0
T7	51136	12742	0	0
T8	53343	13877	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	4396	41	0	0
T27	0	615935	0	0
T42	0	32112	0	0
T52	0	528	0	0
T57	0	17	0	0
T58	0	683	0	0
T60	1970	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	97404358	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	92248	0	0
T6	2248	250	0	0
T7	51136	13415	0	0
T8	53343	13497	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	19	0	0
T60	1970	0	0	0
T63	0	10362	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	91527026	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	70847	0	0
T6	2248	250	0	0
T7	51136	10394	0	0
T8	53343	10819	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	15	0	0
T60	1970	0	0	0
T63	0	10362	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	91527026	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	70847	0	0
T6	2248	250	0	0
T7	51136	10394	0	0
T8	53343	10819	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	15	0	0
T60	1970	0	0	0
T63	0	10362	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	97404358	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	92248	0	0
T6	2248	250	0	0
T7	51136	13415	0	0
T8	53343	13497	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	19	0	0
T60	1970	0	0	0
T63	0	10362	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T5,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375468667	374611257	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	375468667	91526949	0	0
GntImpliesValid_A	375468667	91526949	0	0
GrantKnown_A	375468667	374611257	0	0
IdxKnown_A	375468667	374611257	0	0
IndexIsCorrect_A	375468667	91526949	0	0
NoReadyValidNoGrant_A	375468667	46176175	0	0
Priority_A	375468667	97404281	0	0
ReadyAndValidImplyGrant_A	375468667	91526949	0	0
ReqAndReadyImplyGrant_A	375468667	91526949	0	0
ReqImpliesValid_A	375468667	97404281	0	0
ValidKnown_A	375468667	374611257	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	91526949	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	70847	0	0
T6	2248	250	0	0
T7	51136	10394	0	0
T8	53343	10819	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	15	0	0
T60	1970	0	0	0
T63	0	10362	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	91526949	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	70847	0	0
T6	2248	250	0	0
T7	51136	10394	0	0
T8	53343	10819	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	15	0	0
T60	1970	0	0	0
T63	0	10362	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	91526949	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	70847	0	0
T6	2248	250	0	0
T7	51136	10394	0	0
T8	53343	10819	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	15	0	0
T60	1970	0	0	0
T63	0	10362	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	46176175	0	0
T4	997037	4762	0	0
T5	327400	34774	0	0
T6	2248	0	0	0
T7	51136	12742	0	0
T8	53343	13877	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	4396	41	0	0
T27	0	615935	0	0
T42	0	32112	0	0
T52	0	528	0	0
T57	0	17	0	0
T58	0	683	0	0
T60	1970	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	97404281	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	92248	0	0
T6	2248	250	0	0
T7	51136	13415	0	0
T8	53343	13497	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	19	0	0
T60	1970	0	0	0
T63	0	10362	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	91526949	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	70847	0	0
T6	2248	250	0	0
T7	51136	10394	0	0
T8	53343	10819	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	15	0	0
T60	1970	0	0	0
T63	0	10362	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	91526949	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	70847	0	0
T6	2248	250	0	0
T7	51136	10394	0	0
T8	53343	10819	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	15	0	0
T60	1970	0	0	0
T63	0	10362	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	97404281	0	0
T3	224576	991060	0	0
T4	997037	16456	0	0
T5	327400	92248	0	0
T6	2248	250	0	0
T7	51136	13415	0	0
T8	53343	13497	0	0
T12	3944	0	0	0
T21	2280	0	0	0
T22	943	0	0	0
T23	0	1093	0	0
T52	0	350	0	0
T57	0	19	0	0
T60	1970	0	0	0
T63	0	10362	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375468667	374611257	0	0
T1	4067	3401	0	0
T2	160578	160419	0	0
T3	224576	224568	0	0
T4	997037	996981	0	0
T5	327400	327336	0	0
T6	2248	2192	0	0
T7	51136	51086	0	0
T12	3944	3218	0	0
T21	2280	2187	0	0
T22	943	885	0	0