Line Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
flash_phy_rd_buffers
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T17,T43,T78 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T58,T44 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
Branch Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T17,T43,T78 |
0 |
0 |
1 |
- |
- |
Covered |
T4,T58,T44 |
0 |
0 |
0 |
1 |
- |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buffers
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5407736 |
0 |
0 |
T4 |
7976296 |
2162 |
0 |
0 |
T5 |
2619200 |
45169 |
0 |
0 |
T6 |
17984 |
0 |
0 |
0 |
T7 |
409088 |
19063 |
0 |
0 |
T8 |
426744 |
19558 |
0 |
0 |
T12 |
31552 |
0 |
0 |
0 |
T21 |
18240 |
0 |
0 |
0 |
T22 |
7544 |
0 |
0 |
0 |
T23 |
35168 |
26 |
0 |
0 |
T27 |
0 |
30657 |
0 |
0 |
T34 |
0 |
512 |
0 |
0 |
T42 |
0 |
17937 |
0 |
0 |
T52 |
0 |
365 |
0 |
0 |
T57 |
0 |
10 |
0 |
0 |
T58 |
0 |
508 |
0 |
0 |
T60 |
15760 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5407730 |
0 |
0 |
T4 |
7976296 |
2162 |
0 |
0 |
T5 |
2619200 |
45169 |
0 |
0 |
T6 |
17984 |
0 |
0 |
0 |
T7 |
409088 |
19063 |
0 |
0 |
T8 |
426744 |
19558 |
0 |
0 |
T12 |
31552 |
0 |
0 |
0 |
T21 |
18240 |
0 |
0 |
0 |
T22 |
7544 |
0 |
0 |
0 |
T23 |
35168 |
26 |
0 |
0 |
T27 |
0 |
30657 |
0 |
0 |
T34 |
0 |
512 |
0 |
0 |
T42 |
0 |
17937 |
0 |
0 |
T52 |
0 |
365 |
0 |
0 |
T57 |
0 |
10 |
0 |
0 |
T58 |
0 |
508 |
0 |
0 |
T60 |
15760 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T43,T79,T80 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T58,T44 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T43,T79,T80 |
0 |
0 |
1 |
- |
- |
Covered |
T4,T58,T44 |
0 |
0 |
0 |
1 |
- |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
682924 |
0 |
0 |
T4 |
997037 |
143 |
0 |
0 |
T5 |
327400 |
5759 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2368 |
0 |
0 |
T8 |
53343 |
2467 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
3 |
0 |
0 |
T27 |
0 |
4022 |
0 |
0 |
T34 |
0 |
128 |
0 |
0 |
T42 |
0 |
2266 |
0 |
0 |
T52 |
0 |
43 |
0 |
0 |
T58 |
0 |
68 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
682922 |
0 |
0 |
T4 |
997037 |
143 |
0 |
0 |
T5 |
327400 |
5759 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2368 |
0 |
0 |
T8 |
53343 |
2467 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
3 |
0 |
0 |
T27 |
0 |
4022 |
0 |
0 |
T34 |
0 |
128 |
0 |
0 |
T42 |
0 |
2266 |
0 |
0 |
T52 |
0 |
43 |
0 |
0 |
T58 |
0 |
68 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T43,T79,T80 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T58,T44 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T43,T79,T80 |
0 |
0 |
1 |
- |
- |
Covered |
T4,T58,T44 |
0 |
0 |
0 |
1 |
- |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
682684 |
0 |
0 |
T4 |
997037 |
143 |
0 |
0 |
T5 |
327400 |
5756 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2363 |
0 |
0 |
T8 |
53343 |
2459 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
3 |
0 |
0 |
T27 |
0 |
4027 |
0 |
0 |
T34 |
0 |
128 |
0 |
0 |
T42 |
0 |
2272 |
0 |
0 |
T52 |
0 |
42 |
0 |
0 |
T58 |
0 |
67 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
682684 |
0 |
0 |
T4 |
997037 |
143 |
0 |
0 |
T5 |
327400 |
5756 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2363 |
0 |
0 |
T8 |
53343 |
2459 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
3 |
0 |
0 |
T27 |
0 |
4027 |
0 |
0 |
T34 |
0 |
128 |
0 |
0 |
T42 |
0 |
2272 |
0 |
0 |
T52 |
0 |
42 |
0 |
0 |
T58 |
0 |
67 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T43,T79,T81 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T58,T44 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T43,T79,T81 |
0 |
0 |
1 |
- |
- |
Covered |
T4,T58,T44 |
0 |
0 |
0 |
1 |
- |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
682952 |
0 |
0 |
T4 |
997037 |
143 |
0 |
0 |
T5 |
327400 |
5758 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2374 |
0 |
0 |
T8 |
53343 |
2472 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
2 |
0 |
0 |
T27 |
0 |
4024 |
0 |
0 |
T34 |
0 |
128 |
0 |
0 |
T42 |
0 |
2265 |
0 |
0 |
T52 |
0 |
42 |
0 |
0 |
T58 |
0 |
67 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
682951 |
0 |
0 |
T4 |
997037 |
143 |
0 |
0 |
T5 |
327400 |
5758 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2374 |
0 |
0 |
T8 |
53343 |
2472 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
2 |
0 |
0 |
T27 |
0 |
4024 |
0 |
0 |
T34 |
0 |
128 |
0 |
0 |
T42 |
0 |
2265 |
0 |
0 |
T52 |
0 |
42 |
0 |
0 |
T58 |
0 |
67 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T43,T79,T81 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T58,T44 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T43,T79,T81 |
0 |
0 |
1 |
- |
- |
Covered |
T4,T58,T44 |
0 |
0 |
0 |
1 |
- |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
682203 |
0 |
0 |
T4 |
997037 |
142 |
0 |
0 |
T5 |
327400 |
5756 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2357 |
0 |
0 |
T8 |
53343 |
2478 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
2 |
0 |
0 |
T27 |
0 |
4038 |
0 |
0 |
T34 |
0 |
128 |
0 |
0 |
T42 |
0 |
2271 |
0 |
0 |
T52 |
0 |
42 |
0 |
0 |
T58 |
0 |
66 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
682203 |
0 |
0 |
T4 |
997037 |
142 |
0 |
0 |
T5 |
327400 |
5756 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2357 |
0 |
0 |
T8 |
53343 |
2478 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
2 |
0 |
0 |
T27 |
0 |
4038 |
0 |
0 |
T34 |
0 |
128 |
0 |
0 |
T42 |
0 |
2271 |
0 |
0 |
T52 |
0 |
42 |
0 |
0 |
T58 |
0 |
66 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T17,T78,T82 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T59,T83,T25 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T17,T78,T82 |
0 |
0 |
1 |
- |
- |
Covered |
T59,T83,T25 |
0 |
0 |
0 |
1 |
- |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
669386 |
0 |
0 |
T4 |
997037 |
398 |
0 |
0 |
T5 |
327400 |
5536 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2404 |
0 |
0 |
T8 |
53343 |
2418 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
4 |
0 |
0 |
T27 |
0 |
3636 |
0 |
0 |
T42 |
0 |
2215 |
0 |
0 |
T52 |
0 |
49 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
60 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
669386 |
0 |
0 |
T4 |
997037 |
398 |
0 |
0 |
T5 |
327400 |
5536 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2404 |
0 |
0 |
T8 |
53343 |
2418 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
4 |
0 |
0 |
T27 |
0 |
3636 |
0 |
0 |
T42 |
0 |
2215 |
0 |
0 |
T52 |
0 |
49 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
60 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T17,T78,T82 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T59,T83,T25 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T17,T78,T82 |
0 |
0 |
1 |
- |
- |
Covered |
T59,T83,T25 |
0 |
0 |
0 |
1 |
- |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
669291 |
0 |
0 |
T4 |
997037 |
398 |
0 |
0 |
T5 |
327400 |
5528 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2399 |
0 |
0 |
T8 |
53343 |
2420 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
4 |
0 |
0 |
T27 |
0 |
3631 |
0 |
0 |
T42 |
0 |
2213 |
0 |
0 |
T52 |
0 |
49 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
60 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
669290 |
0 |
0 |
T4 |
997037 |
398 |
0 |
0 |
T5 |
327400 |
5528 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2399 |
0 |
0 |
T8 |
53343 |
2420 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
4 |
0 |
0 |
T27 |
0 |
3631 |
0 |
0 |
T42 |
0 |
2213 |
0 |
0 |
T52 |
0 |
49 |
0 |
0 |
T57 |
0 |
3 |
0 |
0 |
T58 |
0 |
60 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T17,T78,T82 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T59,T83,T25 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T17,T78,T82 |
0 |
0 |
1 |
- |
- |
Covered |
T59,T83,T25 |
0 |
0 |
0 |
1 |
- |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
669545 |
0 |
0 |
T4 |
997037 |
398 |
0 |
0 |
T5 |
327400 |
5543 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2400 |
0 |
0 |
T8 |
53343 |
2418 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
4 |
0 |
0 |
T27 |
0 |
3639 |
0 |
0 |
T42 |
0 |
2218 |
0 |
0 |
T52 |
0 |
49 |
0 |
0 |
T57 |
0 |
2 |
0 |
0 |
T58 |
0 |
60 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
669543 |
0 |
0 |
T4 |
997037 |
398 |
0 |
0 |
T5 |
327400 |
5543 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2400 |
0 |
0 |
T8 |
53343 |
2418 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
4 |
0 |
0 |
T27 |
0 |
3639 |
0 |
0 |
T42 |
0 |
2218 |
0 |
0 |
T52 |
0 |
49 |
0 |
0 |
T57 |
0 |
2 |
0 |
0 |
T58 |
0 |
60 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T17,T78,T82 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T7 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T59,T83,T25 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T17,T78,T82 |
0 |
0 |
1 |
- |
- |
Covered |
T59,T83,T25 |
0 |
0 |
0 |
1 |
- |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
1 |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
668751 |
0 |
0 |
T4 |
997037 |
397 |
0 |
0 |
T5 |
327400 |
5533 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2398 |
0 |
0 |
T8 |
53343 |
2426 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
4 |
0 |
0 |
T27 |
0 |
3640 |
0 |
0 |
T42 |
0 |
2217 |
0 |
0 |
T52 |
0 |
49 |
0 |
0 |
T57 |
0 |
2 |
0 |
0 |
T58 |
0 |
60 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375468667 |
668751 |
0 |
0 |
T4 |
997037 |
397 |
0 |
0 |
T5 |
327400 |
5533 |
0 |
0 |
T6 |
2248 |
0 |
0 |
0 |
T7 |
51136 |
2398 |
0 |
0 |
T8 |
53343 |
2426 |
0 |
0 |
T12 |
3944 |
0 |
0 |
0 |
T21 |
2280 |
0 |
0 |
0 |
T22 |
943 |
0 |
0 |
0 |
T23 |
4396 |
4 |
0 |
0 |
T27 |
0 |
3640 |
0 |
0 |
T42 |
0 |
2217 |
0 |
0 |
T52 |
0 |
49 |
0 |
0 |
T57 |
0 |
2 |
0 |
0 |
T58 |
0 |
60 |
0 |
0 |
T60 |
1970 |
0 |
0 |
0 |