SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.85 | 97.12 | 94.40 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.17 | 100.00 | 94.79 | 92.11 | 98.94 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.37 | 100.00 | 88.89 | 57.14 | 95.83 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.85 | 97.12 | 94.40 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
80.60 | 100.00 | 100.00 | 57.14 | 95.83 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.56 | 97.67 | 86.00 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10410 | 10410 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 21594 |
gen_no_flops.OutputDelay_A | 736776408 | 735061588 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10410 | 10410 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T5 | 10 | 10 | 0 | 0 |
T6 | 10 | 10 | 0 | 0 |
T7 | 10 | 10 | 0 | 0 |
T12 | 10 | 10 | 0 | 0 |
T21 | 10 | 10 | 0 | 0 |
T22 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 40670 | 34010 | 0 | 0 |
T2 | 1605780 | 1604190 | 0 | 0 |
T3 | 2245760 | 2245680 | 0 | 0 |
T4 | 9970370 | 9969810 | 0 | 0 |
T5 | 3274000 | 3273360 | 0 | 0 |
T6 | 22480 | 21920 | 0 | 0 |
T7 | 511360 | 510860 | 0 | 0 |
T12 | 39440 | 32180 | 0 | 0 |
T21 | 22800 | 21870 | 0 | 0 |
T22 | 3830 | 3250 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 21594 |
T1 | 32536 | 26992 | 0 | 24 |
T2 | 1284624 | 1283304 | 0 | 24 |
T3 | 1796608 | 1796536 | 0 | 24 |
T4 | 7976296 | 7975824 | 0 | 24 |
T5 | 2619200 | 2618664 | 0 | 24 |
T6 | 17984 | 17512 | 0 | 24 |
T7 | 409088 | 408664 | 0 | 24 |
T12 | 31552 | 25528 | 0 | 24 |
T21 | 18240 | 17472 | 0 | 24 |
T22 | 3064 | 2600 | 0 | 0 |
T60 | 0 | 0 | 0 | 24 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 736776408 | 735061588 | 0 | 0 |
T1 | 8134 | 6802 | 0 | 0 |
T2 | 321156 | 320838 | 0 | 0 |
T3 | 449152 | 449136 | 0 | 0 |
T4 | 1994074 | 1993962 | 0 | 0 |
T5 | 654800 | 654672 | 0 | 0 |
T6 | 4496 | 4384 | 0 | 0 |
T7 | 102272 | 102172 | 0 | 0 |
T12 | 7888 | 6436 | 0 | 0 |
T21 | 4560 | 4374 | 0 | 0 |
T22 | 766 | 650 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 368388282 | 367530872 | 0 | 0 |
gen_flops.OutputDelay_A | 368388282 | 367496954 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367530872 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367496954 | 0 | 2718 |
T1 | 4067 | 3374 | 0 | 3 |
T2 | 160578 | 160413 | 0 | 3 |
T3 | 224576 | 224567 | 0 | 3 |
T4 | 997037 | 996978 | 0 | 3 |
T5 | 327400 | 327333 | 0 | 3 |
T6 | 2248 | 2189 | 0 | 3 |
T7 | 51136 | 51083 | 0 | 3 |
T12 | 3944 | 3191 | 0 | 3 |
T21 | 2280 | 2184 | 0 | 3 |
T22 | 383 | 325 | 0 | 0 |
T60 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 368388282 | 367530872 | 0 | 0 |
gen_flops.OutputDelay_A | 368388282 | 367496954 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367530872 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367496954 | 0 | 2718 |
T1 | 4067 | 3374 | 0 | 3 |
T2 | 160578 | 160413 | 0 | 3 |
T3 | 224576 | 224567 | 0 | 3 |
T4 | 997037 | 996978 | 0 | 3 |
T5 | 327400 | 327333 | 0 | 3 |
T6 | 2248 | 2189 | 0 | 3 |
T7 | 51136 | 51083 | 0 | 3 |
T12 | 3944 | 3191 | 0 | 3 |
T21 | 2280 | 2184 | 0 | 3 |
T22 | 383 | 325 | 0 | 0 |
T60 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 368388282 | 367530872 | 0 | 0 |
gen_flops.OutputDelay_A | 368388282 | 367496954 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367530872 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367496954 | 0 | 2718 |
T1 | 4067 | 3374 | 0 | 3 |
T2 | 160578 | 160413 | 0 | 3 |
T3 | 224576 | 224567 | 0 | 3 |
T4 | 997037 | 996978 | 0 | 3 |
T5 | 327400 | 327333 | 0 | 3 |
T6 | 2248 | 2189 | 0 | 3 |
T7 | 51136 | 51083 | 0 | 3 |
T12 | 3944 | 3191 | 0 | 3 |
T21 | 2280 | 2184 | 0 | 3 |
T22 | 383 | 325 | 0 | 0 |
T60 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 368388282 | 367530872 | 0 | 0 |
gen_flops.OutputDelay_A | 368388282 | 367496954 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367530872 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367496954 | 0 | 2718 |
T1 | 4067 | 3374 | 0 | 3 |
T2 | 160578 | 160413 | 0 | 3 |
T3 | 224576 | 224567 | 0 | 3 |
T4 | 997037 | 996978 | 0 | 3 |
T5 | 327400 | 327333 | 0 | 3 |
T6 | 2248 | 2189 | 0 | 3 |
T7 | 51136 | 51083 | 0 | 3 |
T12 | 3944 | 3191 | 0 | 3 |
T21 | 2280 | 2184 | 0 | 3 |
T22 | 383 | 325 | 0 | 0 |
T60 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 368388282 | 367530872 | 0 | 0 |
gen_flops.OutputDelay_A | 368388282 | 367496954 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367530872 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367496954 | 0 | 2718 |
T1 | 4067 | 3374 | 0 | 3 |
T2 | 160578 | 160413 | 0 | 3 |
T3 | 224576 | 224567 | 0 | 3 |
T4 | 997037 | 996978 | 0 | 3 |
T5 | 327400 | 327333 | 0 | 3 |
T6 | 2248 | 2189 | 0 | 3 |
T7 | 51136 | 51083 | 0 | 3 |
T12 | 3944 | 3191 | 0 | 3 |
T21 | 2280 | 2184 | 0 | 3 |
T22 | 383 | 325 | 0 | 0 |
T60 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 368388282 | 367530872 | 0 | 0 |
gen_flops.OutputDelay_A | 368388282 | 367496954 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367530872 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388282 | 367496954 | 0 | 2718 |
T1 | 4067 | 3374 | 0 | 3 |
T2 | 160578 | 160413 | 0 | 3 |
T3 | 224576 | 224567 | 0 | 3 |
T4 | 997037 | 996978 | 0 | 3 |
T5 | 327400 | 327333 | 0 | 3 |
T6 | 2248 | 2189 | 0 | 3 |
T7 | 51136 | 51083 | 0 | 3 |
T12 | 3944 | 3191 | 0 | 3 |
T21 | 2280 | 2184 | 0 | 3 |
T22 | 383 | 325 | 0 | 0 |
T60 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 368388204 | 367530794 | 0 | 0 |
gen_no_flops.OutputDelay_A | 368388204 | 367530794 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388204 | 367530794 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388204 | 367530794 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 368367665 | 367510255 | 0 | 0 |
gen_flops.OutputDelay_A | 368367665 | 367476487 | 0 | 2568 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368367665 | 367510255 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368367665 | 367476487 | 0 | 2568 |
T1 | 4067 | 3374 | 0 | 3 |
T2 | 160578 | 160413 | 0 | 3 |
T3 | 224576 | 224567 | 0 | 3 |
T4 | 997037 | 996978 | 0 | 3 |
T5 | 327400 | 327333 | 0 | 3 |
T6 | 2248 | 2189 | 0 | 3 |
T7 | 51136 | 51083 | 0 | 3 |
T12 | 3944 | 3191 | 0 | 3 |
T21 | 2280 | 2184 | 0 | 3 |
T22 | 383 | 325 | 0 | 0 |
T60 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 368388204 | 367530794 | 0 | 0 |
gen_no_flops.OutputDelay_A | 368388204 | 367530794 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388204 | 367530794 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388204 | 367530794 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 368388204 | 367530794 | 0 | 0 |
gen_flops.OutputDelay_A | 368388204 | 367496891 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388204 | 367530794 | 0 | 0 |
T1 | 4067 | 3401 | 0 | 0 |
T2 | 160578 | 160419 | 0 | 0 |
T3 | 224576 | 224568 | 0 | 0 |
T4 | 997037 | 996981 | 0 | 0 |
T5 | 327400 | 327336 | 0 | 0 |
T6 | 2248 | 2192 | 0 | 0 |
T7 | 51136 | 51086 | 0 | 0 |
T12 | 3944 | 3218 | 0 | 0 |
T21 | 2280 | 2187 | 0 | 0 |
T22 | 383 | 325 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 368388204 | 367496891 | 0 | 2718 |
T1 | 4067 | 3374 | 0 | 3 |
T2 | 160578 | 160413 | 0 | 3 |
T3 | 224576 | 224567 | 0 | 3 |
T4 | 997037 | 996978 | 0 | 3 |
T5 | 327400 | 327333 | 0 | 3 |
T6 | 2248 | 2189 | 0 | 3 |
T7 | 51136 | 51083 | 0 | 3 |
T12 | 3944 | 3191 | 0 | 3 |
T21 | 2280 | 2184 | 0 | 3 |
T22 | 383 | 325 | 0 | 0 |
T60 | 0 | 0 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |