Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26655369	1		T1	947		T2	65		T3	34674
full_word	8110142	1		T1	42		T2	41		T3	18877

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34765221	1		T1	989		T2	106		T3	53551
auto[TlIntgErrCmd]	100	1		T106	1		T241	4		T254	6
auto[TlIntgErrData]	87	1		T106	3		T241	10		T254	1
auto[TlIntgErrBoth]	103	1		T106	6		T241	6		T254	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30123944	1		T1	942		T2	59		T3	39429
auto[1]	4641567	1		T1	47		T2	47		T3	14122

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25902797	1		T1	941		T2	59		T3	32873
auto[TlIntgErrNone]	partial	auto[1]	752307	1		T1	6		T2	6		T3	1801
auto[TlIntgErrNone]	full_word	auto[0]	4221014	1		T1	1		T3	6556		T4	114
auto[TlIntgErrNone]	full_word	auto[1]	3889103	1		T1	41		T2	41		T3	12321
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T241	2		T254	3		T270	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1		T106	1		T241	2		T254	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T254	1		T270	1		T386	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T254	1		T262	1		T382	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T106	2		T241	5		T313	2
auto[TlIntgErrData]	partial	auto[1]	38	1		T106	1		T241	4		T254	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T241	1		T272	1		T382	2
auto[TlIntgErrData]	full_word	auto[1]	1	1		T385	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T106	2		T241	3		T254	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1		T106	3		T241	3		T254	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T387	1		T388	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T106	1		T270	1		T313	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	17794	1		T63	19		T108	1031		T109	320
full_word	4147358	1		T1	16305		T5	16355		T21	11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4164882	1		T1	16305		T5	16355		T21	11
auto[TlIntgErrCmd]	90	1		T106	2		T241	2		T254	3
auto[TlIntgErrData]	99	1		T106	5		T241	6		T254	5
auto[TlIntgErrBoth]	81	1		T106	3		T241	11		T254	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4142709	1		T1	16305		T5	16355		T21	11
auto[1]	22443	1		T63	23		T108	1111		T109	443

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1103	1		T63	2		T108	70		T109	52
auto[TlIntgErrNone]	partial	auto[1]	16440	1		T63	17		T108	961		T109	268
auto[TlIntgErrNone]	full_word	auto[0]	4141476	1		T1	16305		T5	16355		T21	11
auto[TlIntgErrNone]	full_word	auto[1]	5863	1		T63	6		T108	150		T109	175
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T106	1		T241	1		T254	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T106	1		T254	2		T270	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T241	1		T275	1		T389	2
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T272	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1		T106	2		T241	3		T254	3
auto[TlIntgErrData]	partial	auto[1]	43	1		T106	3		T241	3		T254	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T254	1		T313	1		T272	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T313	1		T387	1		T385	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T241	4		T254	1		T270	2
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T106	3		T241	6		T270	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T241	1		T313	1		T387	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T384	1		T275	1		-	-