Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.82 100.00 91.27 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.61 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Module : flash_phy_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T3,T4

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT1,T3,T4

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T24
11CoveredT1,T3,T4

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT5,T6,T24
10CoveredT1,T2,T3
11CoveredT1,T3,T4

Branch Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T4
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T3,T4
0 - 0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 768681016 7089448 0 0
BufferDepRsp_A 768681016 767026258 0 0
BufferIncrOverFlow_A 768681016 7089454 0 0
DepBufferRspOrder_A 768681018 16932022 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 768681016 7089448 0 0
T1 1116650 16305 0 0
T2 2692 0 0 0
T3 811766 5808 0 0
T4 165136 42 0 0
T5 234586 33742 0 0
T6 0 45856 0 0
T17 1792 0 0 0
T18 2928 0 0 0
T19 96060 1024 0 0
T20 482374 0 0 0
T21 4176 86 0 0
T23 0 79 0 0
T26 0 64 0 0
T27 0 142 0 0
T28 0 87 0 0
T44 0 165 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 768681016 767026258 0 0
T1 1116650 1116324 0 0
T2 2692 2262 0 0
T3 811766 774946 0 0
T4 165136 164800 0 0
T5 234586 234260 0 0
T17 1792 1614 0 0
T18 2928 2642 0 0
T19 96060 95914 0 0
T20 482374 482068 0 0
T21 4176 3860 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 768681016 7089454 0 0
T1 1116650 16305 0 0
T2 2692 0 0 0
T3 811766 5808 0 0
T4 165136 42 0 0
T5 234586 33742 0 0
T6 0 45856 0 0
T17 1792 0 0 0
T18 2928 0 0 0
T19 96060 1024 0 0
T20 482374 0 0 0
T21 4176 86 0 0
T23 0 79 0 0
T26 0 64 0 0
T27 0 142 0 0
T28 0 87 0 0
T44 0 165 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 768681018 16932022 0 0
T1 1116650 16338 0 0
T2 2692 67 0 0
T3 811766 13616 0 0
T4 165136 74 0 0
T5 234586 33806 0 0
T6 0 23086 0 0
T10 0 131072 0 0
T17 1792 32 0 0
T18 2928 64 0 0
T19 96060 1056 0 0
T20 482374 32 0 0
T21 4176 150 0 0
T23 0 79 0 0
T26 0 9 0 0
T27 0 64 0 0
T28 0 34 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T3,T4

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT1,T3,T4

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T24,T39
11CoveredT1,T3,T4

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT5,T24,T39
10CoveredT1,T2,T3
11CoveredT1,T3,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T4
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T3,T4
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 384340508 4395526 0 0
BufferDepRsp_A 384340508 383513129 0 0
BufferIncrOverFlow_A 384340508 4395529 0 0
DepBufferRspOrder_A 384340509 9677444 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 4395526 0 0
T1 558325 7966 0 0
T2 1346 0 0 0
T3 405883 5808 0 0
T4 82568 20 0 0
T5 117293 16875 0 0
T6 0 22770 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 1024 0 0
T20 241187 0 0 0
T21 2088 71 0 0
T26 0 55 0 0
T27 0 78 0 0
T28 0 53 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 383513129 0 0
T1 558325 558162 0 0
T2 1346 1131 0 0
T3 405883 387473 0 0
T4 82568 82400 0 0
T5 117293 117130 0 0
T17 896 807 0 0
T18 1464 1321 0 0
T19 48030 47957 0 0
T20 241187 241034 0 0
T21 2088 1930 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 4395529 0 0
T1 558325 7966 0 0
T2 1346 0 0 0
T3 405883 5808 0 0
T4 82568 20 0 0
T5 117293 16875 0 0
T6 0 22770 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 1024 0 0
T20 241187 0 0 0
T21 2088 71 0 0
T26 0 55 0 0
T27 0 78 0 0
T28 0 53 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340509 9677444 0 0
T1 558325 7999 0 0
T2 1346 67 0 0
T3 405883 13616 0 0
T4 82568 52 0 0
T5 117293 16939 0 0
T17 896 32 0 0
T18 1464 64 0 0
T19 48030 1056 0 0
T20 241187 32 0 0
T21 2088 135 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT10,T112,T116
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T4,T5

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T4,T5
110Not Covered
111CoveredT1,T4,T5

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T24,T58
11CoveredT1,T4,T5

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT6,T24,T58
10CoveredT1,T2,T3
11CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T4,T5
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T4,T5
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 384340508 2693922 0 0
BufferDepRsp_A 384340508 383513129 0 0
BufferIncrOverFlow_A 384340508 2693925 0 0
DepBufferRspOrder_A 384340509 7254578 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 2693922 0 0
T1 558325 8339 0 0
T2 1346 0 0 0
T3 405883 0 0 0
T4 82568 22 0 0
T5 117293 16867 0 0
T6 0 23086 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 0 0 0
T20 241187 0 0 0
T21 2088 15 0 0
T23 0 79 0 0
T26 0 9 0 0
T27 0 64 0 0
T28 0 34 0 0
T44 0 165 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 383513129 0 0
T1 558325 558162 0 0
T2 1346 1131 0 0
T3 405883 387473 0 0
T4 82568 82400 0 0
T5 117293 117130 0 0
T17 896 807 0 0
T18 1464 1321 0 0
T19 48030 47957 0 0
T20 241187 241034 0 0
T21 2088 1930 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 2693925 0 0
T1 558325 8339 0 0
T2 1346 0 0 0
T3 405883 0 0 0
T4 82568 22 0 0
T5 117293 16867 0 0
T6 0 23086 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 0 0 0
T20 241187 0 0 0
T21 2088 15 0 0
T23 0 79 0 0
T26 0 9 0 0
T27 0 64 0 0
T28 0 34 0 0
T44 0 165 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340509 7254578 0 0
T1 558325 8339 0 0
T2 1346 0 0 0
T3 405883 0 0 0
T4 82568 22 0 0
T5 117293 16867 0 0
T6 0 23086 0 0
T10 0 131072 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 0 0 0
T20 241187 0 0 0
T21 2088 15 0 0
T23 0 79 0 0
T26 0 9 0 0
T27 0 64 0 0
T28 0 34 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%