Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_to_rd_fifo.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.91 76.92 65.71 25.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.91 76.92 65.71 25.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.89 100.00 75.00 96.55 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_adapter_eflash.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.07 100.00 74.29 50.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.07 100.00 74.29 50.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.45 100.00 81.25 96.55 100.00 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_prog_fifo.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.32 100.00 74.29 75.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.32 100.00 74.29 75.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.96 100.00 65.52 85.71 84.62 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_reg_if.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.96 100.00 91.84 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.91 100.00 95.65 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : tlul_err
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5411100.00
ALWAYS571717100.00
CONT_ASSIGN9611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
42 1 1
54 1 1
57 1 1
58 1 1
59 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
70 1 1
72 1 1
74 1 1
78 1 1
79 1 1
80 1 1
90 1 1
91 1 1
92 1 1
96 1 1


Cond Coverage for Module : tlul_err
TotalCoveredPercent
Conditions3535100.00
Logical3535100.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT24,T46,T47
010CoveredT63,T108,T109
100CoveredT1,T2,T3

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01CoveredT108,T109,T223
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000CoveredT25,T63,T108
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T19

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T19

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT108,T109,T223
101CoveredT63,T108,T109
110CoveredT25,T63,T108
111CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

Branch Coverage for Module : tlul_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 61 8 8 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 61 if (tl_i.a_valid) -2-: 62 case (tl_i.a_size) -3-: 72 (tl_i.a_address[1]) ? -4-: 74 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T1,T2,T3
1 'h1 1 - Covered T3,T4,T19
1 'h1 0 - Covered T1,T2,T3
1 'h1 - 1 Covered T3,T4,T19
1 'h1 - 0 Covered T1,T2,T3
1 'h00000002 - - Covered T1,T2,T3
1 default - - Covered T12,T63,T108
0 - - - Covered T1,T2,T3


Assert Coverage for Module : tlul_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 5690 5690 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5690 5690 0 0
T1 5 5 0 0
T2 5 5 0 0
T3 5 5 0 0
T4 5 5 0 0
T5 5 5 0 0
T17 5 5 0 0
T18 5 5 0 0
T19 5 5 0 0
T20 5 5 0 0
T21 5 5 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_err
Line No.TotalCoveredPercent
TOTAL262076.92
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5411100.00
ALWAYS57171164.71
CONT_ASSIGN9611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
42 1 1
54 1 1
57 1 1
58 1 1
59 1 1
61 1 1
62 1 1
64 0 1
65 0 1
66 0 1
70 0 1
72 0 1
74 0 1
78 1 1
79 1 1
80 1 1
90 1 1
91 1 1
92 1 1
96 1 1


Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_err
TotalCoveredPercent
Conditions352365.71
Logical352365.71
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT3,T4,T19
001Not Covered
010Not Covered
100CoveredT1,T2,T3

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T4,T19

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000Not Covered
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT3,T4,T19

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T2,T3
100CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_err
Line No.TotalCoveredPercent
Branches 8 2 25.00
IF 61 8 2 25.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 61 if (tl_i.a_valid) -2-: 62 case (tl_i.a_size) -3-: 72 (tl_i.a_address[1]) ? -4-: 74 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Not Covered
1 'h1 1 - Not Covered
1 'h1 0 - Not Covered
1 'h1 - 1 Not Covered
1 'h1 - 0 Not Covered
1 'h00000002 - - Covered T3,T4,T19
1 default - - Not Covered
0 - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 1052 1052 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5411100.00
ALWAYS571717100.00
CONT_ASSIGN9611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
42 1 1
54 1 1
57 1 1
58 1 1
59 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
70 1 1
72 1 1
74 1 1
78 1 1
79 1 1
80 1 1
90 1 1
91 1 1
92 1 1
96 1 1


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err
TotalCoveredPercent
Conditions352674.29
Logical352674.29
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T21,T26

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T20

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T5,T21
001CoveredT24,T46,T47
010Not Covered
100CoveredT1,T20,T21

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T5,T21

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000CoveredT25
001CoveredT1,T5,T20
010CoveredT1,T21,T26
100CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T21,T26

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T20

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT25
111CoveredT1,T5,T21

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T21,T26
100CoveredT1,T20,T21

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err
Line No.TotalCoveredPercent
Branches 8 4 50.00
IF 61 8 4 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 61 if (tl_i.a_valid) -2-: 62 case (tl_i.a_size) -3-: 72 (tl_i.a_address[1]) ? -4-: 74 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T12
1 'h1 1 - Not Covered
1 'h1 0 - Not Covered
1 'h1 - 1 Not Covered
1 'h1 - 0 Not Covered
1 'h00000002 - - Covered T1,T5,T21
1 default - - Covered T12
0 - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 1052 1052 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_err
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5411100.00
ALWAYS571717100.00
CONT_ASSIGN9611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
42 1 1
54 1 1
57 1 1
58 1 1
59 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
70 1 1
72 1 1
74 1 1
78 1 1
79 1 1
80 1 1
90 1 1
91 1 1
92 1 1
96 1 1


Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_err
TotalCoveredPercent
Conditions352674.29
Logical352674.29
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT3,T4,T18
001Not Covered
010Not Covered
100CoveredT1,T2,T3

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T4,T18

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000Not Covered
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT12
1Not Covered

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT12
1Not Covered

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT3,T4,T18

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT3,T4,T18
010CoveredT1,T2,T3
100CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_err
Line No.TotalCoveredPercent
Branches 8 6 75.00
IF 61 8 6 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 61 if (tl_i.a_valid) -2-: 62 case (tl_i.a_size) -3-: 72 (tl_i.a_address[1]) ? -4-: 74 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T12
1 'h1 1 - Not Covered
1 'h1 0 - Covered T12
1 'h1 - 1 Not Covered
1 'h1 - 0 Covered T12
1 'h00000002 - - Covered T3,T4,T18
1 default - - Covered T12
0 - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 1052 1052 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1052 1052 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5411100.00
ALWAYS571717100.00
CONT_ASSIGN9611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
42 1 1
54 1 1
57 1 1
58 1 1
59 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
70 1 1
72 1 1
74 1 1
78 1 1
79 1 1
80 1 1
90 1 1
91 1 1
92 1 1
96 1 1


Cond Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
TotalCoveredPercent
Conditions3535100.00
Logical3535100.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT63,T108,T109
010CoveredT63,T108,T109
100CoveredT3,T4,T18

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01CoveredT108,T109,T223
10CoveredT3,T4,T18
11CoveredT1,T2,T3

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000CoveredT63,T108,T109
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T19

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T19

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT108,T109,T223
101CoveredT108,T109,T223
110CoveredT63,T108,T109
111CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT3,T4,T18
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 61 8 8 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 61 if (tl_i.a_valid) -2-: 62 case (tl_i.a_size) -3-: 72 (tl_i.a_address[1]) ? -4-: 74 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T1,T2,T3
1 'h1 1 - Covered T3,T4,T19
1 'h1 0 - Covered T1,T2,T3
1 'h1 - 1 Covered T3,T4,T19
1 'h1 - 0 Covered T1,T2,T3
1 'h00000002 - - Covered T1,T2,T3
1 default - - Covered T63,T108,T109
0 - - - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 1267 1267 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1267 1267 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5411100.00
ALWAYS571717100.00
CONT_ASSIGN9611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
42 1 1
54 1 1
57 1 1
58 1 1
59 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
70 1 1
72 1 1
74 1 1
78 1 1
79 1 1
80 1 1
90 1 1
91 1 1
92 1 1
96 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err
TotalCoveredPercent
Conditions3535100.00
Logical3535100.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T18,T19

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T17

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT63,T64,T65
001CoveredT63,T108,T109
010CoveredT63,T108,T109
100CoveredT3,T4,T17

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01CoveredT108,T109,T223
10CoveredT3,T4,T17
11CoveredT63,T64,T65

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000CoveredT63,T108,T109
001CoveredT3,T4,T5
010CoveredT3,T4,T17
100CoveredT3,T18,T19

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T18,T19

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T17

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT63,T64,T65
1CoveredT63,T64,T65

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT63,T64,T65
1CoveredT63,T64,T65

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT108,T109,T223
101CoveredT63,T108,T109
110CoveredT63,T108,T109
111CoveredT63,T64,T65

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT3,T18,T19
001CoveredT63,T64,T65
010CoveredT3,T4,T17
100CoveredT3,T4,T5

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 61 8 8 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 61 if (tl_i.a_valid) -2-: 62 case (tl_i.a_size) -3-: 72 (tl_i.a_address[1]) ? -4-: 74 (tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T63,T64,T65
1 'h1 1 - Covered T63,T64,T65
1 'h1 0 - Covered T63,T64,T65
1 'h1 - 1 Covered T63,T64,T65
1 'h1 - 0 Covered T63,T64,T65
1 'h00000002 - - Covered T63,T64,T65
1 default - - Covered T63,T108,T109
0 - - - Covered T3,T4,T17


Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 1267 1267 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1267 1267 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%