Module Definition
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Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.28 100.00 85.19 91.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.28 100.00 85.19 91.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.65 100.00 92.86 93.75 100.00 gen_prim_flash_banks[1].u_prim_flash_bank


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.52 100.00 88.89 91.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.52 100.00 88.89 91.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.09 100.00 92.86 87.50 100.00 gen_prim_flash_banks[0].u_prim_flash_bank


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_ctrl_phy_cov_if
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN2411100.00
CONT_ASSIGN2611100.00
ALWAYS3288100.00
ALWAYS4344100.00
ALWAYS5633100.00
CONT_ASSIGN6311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1
26 1 1
32 1 1
33 1 1
34 2 2
35 2 2
36 2 2
MISSING_ELSE
MISSING_ELSE
43 1 1
44 1 1
46 1 1
47 1 1
MISSING_ELSE
56 2 2
57 1 1
63 1 1


Cond Coverage for Module : flash_ctrl_phy_cov_if
TotalCoveredPercent
Conditions272488.89
Logical272488.89
Non-Logical00
Event00

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT44,T66,T37
0010CoveredT3,T4,T19
0100CoveredT3,T4,T18
1000CoveredT1,T2,T3

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T19
11CoveredT1,T2,T3

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT12
01CoveredT44,T66,T37
10CoveredT3,T4,T19

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : flash_ctrl_phy_cov_if
Line No.TotalCoveredPercent
Branches 12 11 91.67
IF 33 5 5 100.00
IF 43 3 3 100.00
IF 56 4 3 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 33 if (any_vld_req) -2-: 34 if (rd_req) -3-: 35 if (prog_req) -4-: 36 if ((pg_erase_req || bk_erase_req))

Branches:
-1--2--3--4-StatusTests
1 1 - - Covered T1,T2,T3
1 0 1 - Covered T3,T4,T18
1 0 0 1 Covered T3,T4,T19
1 0 0 0 Covered T12
0 - - - Covered T1,T2,T3


LineNo. Expression -1-: 43 if ((!rst_ni)) -2-: 46 if (any_vld_req)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if (((!rst_ni) || (!rd_buf_en))) -2-: 57 (any_vld_req) ? -3-: 57 ((idle_cnt == 32'hffffffff)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T4
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN2411100.00
CONT_ASSIGN2611100.00
ALWAYS3288100.00
ALWAYS4344100.00
ALWAYS5633100.00
CONT_ASSIGN6311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1
26 1 1
32 1 1
33 1 1
34 2 2
35 2 2
36 2 2
MISSING_ELSE
MISSING_ELSE
43 1 1
44 1 1
46 1 1
47 1 1
MISSING_ELSE
56 2 2
57 1 1
63 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if
TotalCoveredPercent
Conditions272385.19
Logical272385.19
Non-Logical00
Event00

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT44,T66,T37
0010CoveredT4,T10,T27
0100CoveredT4,T18,T10
1000CoveredT1,T4,T5

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T44
11CoveredT1,T4,T18

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----
-1--2-StatusTests
00Not Covered
01CoveredT44,T66,T37
10CoveredT4,T10,T27

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T4,T5
11CoveredT1,T5,T21

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if
Line No.TotalCoveredPercent
Branches 12 11 91.67
IF 33 5 5 100.00
IF 43 3 3 100.00
IF 56 4 3 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 33 if (any_vld_req) -2-: 34 if (rd_req) -3-: 35 if (prog_req) -4-: 36 if ((pg_erase_req || bk_erase_req))

Branches:
-1--2--3--4-StatusTests
1 1 - - Covered T1,T4,T5
1 0 1 - Covered T4,T18,T10
1 0 0 1 Covered T4,T10,T27
1 0 0 0 Covered T12
0 - - - Covered T1,T2,T3


LineNo. Expression -1-: 43 if ((!rst_ni)) -2-: 46 if (any_vld_req)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if (((!rst_ni) || (!rd_buf_en))) -2-: 57 (any_vld_req) ? -3-: 57 ((idle_cnt == 32'hffffffff)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T4,T5
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN2411100.00
CONT_ASSIGN2611100.00
ALWAYS3288100.00
ALWAYS4344100.00
ALWAYS5633100.00
CONT_ASSIGN6311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
24 1 1
26 1 1
32 1 1
33 1 1
34 2 2
35 2 2
36 2 2
MISSING_ELSE
MISSING_ELSE
43 1 1
44 1 1
46 1 1
47 1 1
MISSING_ELSE
56 2 2
57 1 1
63 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if
TotalCoveredPercent
Conditions272488.89
Logical272488.89
Non-Logical00
Event00

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT37,T67,T68
0010CoveredT3,T4,T19
0100CoveredT3,T4,T19
1000CoveredT1,T2,T3

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T4,T19
11CoveredT1,T2,T3

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT12
01CoveredT37,T67,T68
10CoveredT3,T4,T19

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if
Line No.TotalCoveredPercent
Branches 12 11 91.67
IF 33 5 5 100.00
IF 43 3 3 100.00
IF 56 4 3 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 33 if (any_vld_req) -2-: 34 if (rd_req) -3-: 35 if (prog_req) -4-: 36 if ((pg_erase_req || bk_erase_req))

Branches:
-1--2--3--4-StatusTests
1 1 - - Covered T1,T2,T3
1 0 1 - Covered T3,T4,T19
1 0 0 1 Covered T3,T4,T19
1 0 0 0 Covered T12
0 - - - Covered T1,T2,T3


LineNo. Expression -1-: 43 if ((!rst_ni)) -2-: 46 if (any_vld_req)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if (((!rst_ni) || (!rd_buf_en))) -2-: 57 (any_vld_req) ? -3-: 57 ((idle_cnt == 32'hffffffff)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T4
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%