Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T21

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1537362032	1534052516	0	0
CheckNGreaterZero_A	4208	4208	0	0
GntImpliesReady_A	1537362032	404634688	0	0
GntImpliesValid_A	1537362032	404634688	0	0
GrantKnown_A	1537362032	1534052516	0	0
IdxKnown_A	1537362032	1534052516	0	0
IndexIsCorrect_A	1537362032	404634688	0	0
NoReadyValidNoGrant_A	1537362032	180249175	0	0
Priority_A	1537362032	429037499	0	0
ReadyAndValidImplyGrant_A	1537362032	404634688	0	0
ReqAndReadyImplyGrant_A	1537362032	404634688	0	0
ReqImpliesValid_A	1537362032	429037499	0	0
ValidKnown_A	1537362032	1534052516	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	1534052516	0	0
T1	2233300	2232648	0	0
T2	5384	4524	0	0
T3	1623532	1549892	0	0
T4	330272	329600	0	0
T5	469172	468520	0	0
T17	3584	3228	0	0
T18	5856	5284	0	0
T19	192120	191828	0	0
T20	964748	964136	0	0
T21	8352	7720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4208	4208	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	404634688	0	0
T1	2233300	32676	0	0
T2	5384	134	0	0
T3	1623532	352440	0	0
T4	330272	43190	0	0
T5	469172	67612	0	0
T6	0	266368	0	0
T10	0	255794	0	0
T17	3584	64	0	0
T18	5856	150	0	0
T19	192120	30728	0	0
T20	964748	838	0	0
T21	8352	432	0	0
T26	0	18	0	0
T27	0	2728	0	0
T28	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	404634688	0	0
T1	2233300	32676	0	0
T2	5384	134	0	0
T3	1623532	352440	0	0
T4	330272	43190	0	0
T5	469172	67612	0	0
T6	0	266368	0	0
T10	0	255794	0	0
T17	3584	64	0	0
T18	5856	150	0	0
T19	192120	30728	0	0
T20	964748	838	0	0
T21	8352	432	0	0
T26	0	18	0	0
T27	0	2728	0	0
T28	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	1534052516	0	0
T1	2233300	2232648	0	0
T2	5384	4524	0	0
T3	1623532	1549892	0	0
T4	330272	329600	0	0
T5	469172	468520	0	0
T17	3584	3228	0	0
T18	5856	5284	0	0
T19	192120	191828	0	0
T20	964748	964136	0	0
T21	8352	7720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	1534052516	0	0
T1	2233300	2232648	0	0
T2	5384	4524	0	0
T3	1623532	1549892	0	0
T4	330272	329600	0	0
T5	469172	468520	0	0
T17	3584	3228	0	0
T18	5856	5284	0	0
T19	192120	191828	0	0
T20	964748	964136	0	0
T21	8352	7720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	404634688	0	0
T1	2233300	32676	0	0
T2	5384	134	0	0
T3	1623532	352440	0	0
T4	330272	43190	0	0
T5	469172	67612	0	0
T6	0	266368	0	0
T10	0	255794	0	0
T17	3584	64	0	0
T18	5856	150	0	0
T19	192120	30728	0	0
T20	964748	838	0	0
T21	8352	432	0	0
T26	0	18	0	0
T27	0	2728	0	0
T28	0	200	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	180249175	0	0
T1	2233300	1207590	0	0
T2	5384	536	0	0
T3	1623532	90736	0	0
T4	330272	424	0	0
T5	469172	186168	0	0
T6	0	96446	0	0
T10	0	1048576	0	0
T17	3584	256	0	0
T18	5856	512	0	0
T19	192120	4224	0	0
T20	964748	256	0	0
T21	8352	978	0	0
T23	0	252	0	0
T26	0	60	0	0
T27	0	228	0	0
T28	0	110	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	429037499	0	0
T1	2233300	477890	0	0
T2	5384	134	0	0
T3	1623532	352440	0	0
T4	330272	43190	0	0
T5	469172	71234	0	0
T6	0	327430	0	0
T10	0	255794	0	0
T17	3584	64	0	0
T18	5856	150	0	0
T19	192120	30728	0	0
T20	964748	838	0	0
T21	8352	432	0	0
T26	0	18	0	0
T27	0	2728	0	0
T28	0	200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	404634688	0	0
T1	2233300	32676	0	0
T2	5384	134	0	0
T3	1623532	352440	0	0
T4	330272	43190	0	0
T5	469172	67612	0	0
T6	0	266368	0	0
T10	0	255794	0	0
T17	3584	64	0	0
T18	5856	150	0	0
T19	192120	30728	0	0
T20	964748	838	0	0
T21	8352	432	0	0
T26	0	18	0	0
T27	0	2728	0	0
T28	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	404634688	0	0
T1	2233300	32676	0	0
T2	5384	134	0	0
T3	1623532	352440	0	0
T4	330272	43190	0	0
T5	469172	67612	0	0
T6	0	266368	0	0
T10	0	255794	0	0
T17	3584	64	0	0
T18	5856	150	0	0
T19	192120	30728	0	0
T20	964748	838	0	0
T21	8352	432	0	0
T26	0	18	0	0
T27	0	2728	0	0
T28	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	429037499	0	0
T1	2233300	477890	0	0
T2	5384	134	0	0
T3	1623532	352440	0	0
T4	330272	43190	0	0
T5	469172	71234	0	0
T6	0	327430	0	0
T10	0	255794	0	0
T17	3584	64	0	0
T18	5856	150	0	0
T19	192120	30728	0	0
T20	964748	838	0	0
T21	8352	432	0	0
T26	0	18	0	0
T27	0	2728	0	0
T28	0	200	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1537362032	1534052516	0	0
T1	2233300	2232648	0	0
T2	5384	4524	0	0
T3	1623532	1549892	0	0
T4	330272	329600	0	0
T5	469172	468520	0	0
T17	3584	3228	0	0
T18	5856	5284	0	0
T19	192120	191828	0	0
T20	964748	964136	0	0
T21	8352	7720	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384340508	383513129	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	384340508	111567198	0	0
GntImpliesValid_A	384340508	111567198	0	0
GrantKnown_A	384340508	383513129	0	0
IdxKnown_A	384340508	383513129	0	0
IndexIsCorrect_A	384340508	111567198	0	0
NoReadyValidNoGrant_A	384340508	47510367	0	0
Priority_A	384340508	117534091	0	0
ReadyAndValidImplyGrant_A	384340508	111567198	0	0
ReqAndReadyImplyGrant_A	384340508	111567198	0	0
ReqImpliesValid_A	384340508	117534091	0	0
ValidKnown_A	384340508	383513129	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	111567198	0	0
T1	558325	7999	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	16939	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	111567198	0	0
T1	558325	7999	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	16939	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	111567198	0	0
T1	558325	7999	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	16939	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	47510367	0	0
T1	558325	301357	0	0
T2	1346	268	0	0
T3	405883	45368	0	0
T4	82568	168	0	0
T5	117293	46601	0	0
T17	896	128	0	0
T18	1464	256	0	0
T19	48030	2112	0	0
T20	241187	128	0	0
T21	2088	444	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	117534091	0	0
T1	558325	111328	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	18287	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	111567198	0	0
T1	558325	7999	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	16939	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	111567198	0	0
T1	558325	7999	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	16939	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	117534091	0	0
T1	558325	111328	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	18287	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384340508	383513129	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	384340508	111567135	0	0
GntImpliesValid_A	384340508	111567135	0	0
GrantKnown_A	384340508	383513129	0	0
IdxKnown_A	384340508	383513129	0	0
IndexIsCorrect_A	384340508	111567135	0	0
NoReadyValidNoGrant_A	384340508	47510368	0	0
Priority_A	384340508	117534027	0	0
ReadyAndValidImplyGrant_A	384340508	111567135	0	0
ReqAndReadyImplyGrant_A	384340508	111567135	0	0
ReqImpliesValid_A	384340508	117534027	0	0
ValidKnown_A	384340508	383513129	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	111567135	0	0
T1	558325	7999	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	16939	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	111567135	0	0
T1	558325	7999	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	16939	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	111567135	0	0
T1	558325	7999	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	16939	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	47510368	0	0
T1	558325	301357	0	0
T2	1346	268	0	0
T3	405883	45368	0	0
T4	82568	168	0	0
T5	117293	46601	0	0
T17	896	128	0	0
T18	1464	256	0	0
T19	48030	2112	0	0
T20	241187	128	0	0
T21	2088	444	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	117534027	0	0
T1	558325	111328	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	18287	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	111567135	0	0
T1	558325	7999	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	16939	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	111567135	0	0
T1	558325	7999	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	16939	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	117534027	0	0
T1	558325	111328	0	0
T2	1346	67	0	0
T3	405883	176220	0	0
T4	82568	10550	0	0
T5	117293	18287	0	0
T17	896	32	0	0
T18	1464	64	0	0
T19	48030	15364	0	0
T20	241187	419	0	0
T21	2088	201	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18,T5
1	0	Covered	T1,T5,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T21
1	0	Covered	T4,T18,T5
1	1	Covered	T1,T5,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21
1	1	Covered	T4,T18,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21
1	1	Covered	T1,T4,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384340508	383513129	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	384340508	90750155	0	0
GntImpliesValid_A	384340508	90750155	0	0
GrantKnown_A	384340508	383513129	0	0
IdxKnown_A	384340508	383513129	0	0
IndexIsCorrect_A	384340508	90750155	0	0
NoReadyValidNoGrant_A	384340508	42614229	0	0
Priority_A	384340508	96984659	0	0
ReadyAndValidImplyGrant_A	384340508	90750155	0	0
ReqAndReadyImplyGrant_A	384340508	90750155	0	0
ReqImpliesValid_A	384340508	96984659	0	0
ValidKnown_A	384340508	383513129	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	90750155	0	0
T1	558325	8339	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	16867	0	0
T6	0	133184	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	90750155	0	0
T1	558325	8339	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	16867	0	0
T6	0	133184	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	90750155	0	0
T1	558325	8339	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	16867	0	0
T6	0	133184	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	42614229	0	0
T1	558325	302438	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	44	0	0
T5	117293	46483	0	0
T6	0	48223	0	0
T10	0	524288	0	0
T17	896	0	0	0
T18	1464	0	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	45	0	0
T23	0	126	0	0
T26	0	30	0	0
T27	0	114	0	0
T28	0	55	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	96984659	0	0
T1	558325	127617	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	17330	0	0
T6	0	163715	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	90750155	0	0
T1	558325	8339	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	16867	0	0
T6	0	133184	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	90750155	0	0
T1	558325	8339	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	16867	0	0
T6	0	133184	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	96984659	0	0
T1	558325	127617	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	17330	0	0
T6	0	163715	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18,T5
1	0	Covered	T1,T5,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T21
1	0	Covered	T4,T18,T5
1	1	Covered	T1,T5,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21
1	1	Covered	T4,T18,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T21
1	1	Covered	T1,T4,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384340508	383513129	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	384340508	90750200	0	0
GntImpliesValid_A	384340508	90750200	0	0
GrantKnown_A	384340508	383513129	0	0
IdxKnown_A	384340508	383513129	0	0
IndexIsCorrect_A	384340508	90750200	0	0
NoReadyValidNoGrant_A	384340508	42614211	0	0
Priority_A	384340508	96984722	0	0
ReadyAndValidImplyGrant_A	384340508	90750200	0	0
ReqAndReadyImplyGrant_A	384340508	90750200	0	0
ReqImpliesValid_A	384340508	96984722	0	0
ValidKnown_A	384340508	383513129	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	90750200	0	0
T1	558325	8339	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	16867	0	0
T6	0	133184	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	90750200	0	0
T1	558325	8339	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	16867	0	0
T6	0	133184	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	90750200	0	0
T1	558325	8339	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	16867	0	0
T6	0	133184	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	42614211	0	0
T1	558325	302438	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	44	0	0
T5	117293	46483	0	0
T6	0	48223	0	0
T10	0	524288	0	0
T17	896	0	0	0
T18	1464	0	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	45	0	0
T23	0	126	0	0
T26	0	30	0	0
T27	0	114	0	0
T28	0	55	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	96984722	0	0
T1	558325	127617	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	17330	0	0
T6	0	163715	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	90750200	0	0
T1	558325	8339	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	16867	0	0
T6	0	133184	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	90750200	0	0
T1	558325	8339	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	16867	0	0
T6	0	133184	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	96984722	0	0
T1	558325	127617	0	0
T2	1346	0	0	0
T3	405883	0	0	0
T4	82568	11045	0	0
T5	117293	17330	0	0
T6	0	163715	0	0
T10	0	127897	0	0
T17	896	0	0	0
T18	1464	11	0	0
T19	48030	0	0	0
T20	241187	0	0	0
T21	2088	15	0	0
T26	0	9	0	0
T27	0	1364	0	0
T28	0	100	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384340508	383513129	0	0
T1	558325	558162	0	0
T2	1346	1131	0	0
T3	405883	387473	0	0
T4	82568	82400	0	0
T5	117293	117130	0	0
T17	896	807	0	0
T18	1464	1321	0	0
T19	48030	47957	0	0
T20	241187	241034	0	0
T21	2088	1930	0	0