Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.82 100.00 91.27 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.82 100.00 91.27 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.82 100.00 91.27 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.82 100.00 91.27 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.61 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.61 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.61 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.61 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Module : flash_phy_rd_buffers
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT45,T79,T80

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T19

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

Branch Coverage for Module : flash_phy_rd_buffers
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T45,T79,T80
0 0 1 - - Covered T3,T4,T19
0 0 0 1 - Covered T1,T3,T4
0 0 0 0 1 Covered T1,T3,T4
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd_buffers
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 2147483647 5467308 0 0
UpdateCheck_A 2147483647 5467302 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5467308 0 0
T1 4466600 16305 0 0
T2 10768 0 0 0
T3 3247064 2776 0 0
T4 660544 42 0 0
T5 938344 25614 0 0
T6 0 43671 0 0
T17 7168 0 0 0
T18 11712 0 0 0
T19 384240 512 0 0
T20 1929496 0 0 0
T21 16704 49 0 0
T23 0 79 0 0
T26 0 37 0 0
T27 0 82 0 0
T28 0 48 0 0
T44 0 92 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5467302 0 0
T1 4466600 16305 0 0
T2 10768 0 0 0
T3 3247064 2776 0 0
T4 660544 42 0 0
T5 938344 25614 0 0
T6 0 43671 0 0
T17 7168 0 0 0
T18 11712 0 0 0
T19 384240 512 0 0
T20 1929496 0 0 0
T21 16704 49 0 0
T23 0 79 0 0
T26 0 37 0 0
T27 0 82 0 0
T28 0 48 0 0
T44 0 92 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT45,T79,T80

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T19,T21

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T45,T79,T80
0 0 1 - - Covered T3,T19,T21
0 0 0 1 - Covered T1,T3,T4
0 0 0 0 1 Covered T1,T3,T4
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 384340508 790784 0 0
UpdateCheck_A 384340508 790783 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 790784 0 0
T1 558325 1992 0 0
T2 1346 0 0 0
T3 405883 694 0 0
T4 82568 5 0 0
T5 117293 3205 0 0
T6 0 5389 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 128 0 0
T20 241187 0 0 0
T21 2088 11 0 0
T26 0 8 0 0
T27 0 12 0 0
T28 0 7 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 790783 0 0
T1 558325 1992 0 0
T2 1346 0 0 0
T3 405883 694 0 0
T4 82568 5 0 0
T5 117293 3205 0 0
T6 0 5389 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 128 0 0
T20 241187 0 0 0
T21 2088 11 0 0
T26 0 8 0 0
T27 0 12 0 0
T28 0 7 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT45,T79,T80

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T19,T27

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T45,T79,T80
0 0 1 - - Covered T3,T19,T27
0 0 0 1 - Covered T1,T3,T4
0 0 0 0 1 Covered T1,T3,T4
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 384340508 790563 0 0
UpdateCheck_A 384340508 790562 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 790563 0 0
T1 558325 1992 0 0
T2 1346 0 0 0
T3 405883 694 0 0
T4 82568 5 0 0
T5 117293 3200 0 0
T6 0 5390 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 128 0 0
T20 241187 0 0 0
T21 2088 10 0 0
T26 0 8 0 0
T27 0 12 0 0
T28 0 7 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 790562 0 0
T1 558325 1992 0 0
T2 1346 0 0 0
T3 405883 694 0 0
T4 82568 5 0 0
T5 117293 3200 0 0
T6 0 5390 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 128 0 0
T20 241187 0 0 0
T21 2088 10 0 0
T26 0 8 0 0
T27 0 12 0 0
T28 0 7 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT45,T79,T80

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T19

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T45,T79,T80
0 0 1 - - Covered T3,T4,T19
0 0 0 1 - Covered T1,T3,T4
0 0 0 0 1 Covered T1,T3,T4
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 384340508 790038 0 0
UpdateCheck_A 384340508 790038 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 790038 0 0
T1 558325 1991 0 0
T2 1346 0 0 0
T3 405883 694 0 0
T4 82568 5 0 0
T5 117293 3207 0 0
T6 0 5394 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 128 0 0
T20 241187 0 0 0
T21 2088 9 0 0
T26 0 7 0 0
T27 0 10 0 0
T28 0 8 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 790038 0 0
T1 558325 1991 0 0
T2 1346 0 0 0
T3 405883 694 0 0
T4 82568 5 0 0
T5 117293 3207 0 0
T6 0 5394 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 128 0 0
T20 241187 0 0 0
T21 2088 9 0 0
T26 0 7 0 0
T27 0 10 0 0
T28 0 8 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT45,T79,T80

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T19,T81

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T45,T79,T80
0 0 1 - - Covered T3,T19,T81
0 0 0 1 - Covered T1,T3,T4
0 0 0 0 1 Covered T1,T3,T4
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 384340508 789858 0 0
UpdateCheck_A 384340508 789857 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 789858 0 0
T1 558325 1991 0 0
T2 1346 0 0 0
T3 405883 694 0 0
T4 82568 5 0 0
T5 117293 3207 0 0
T6 0 5393 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 128 0 0
T20 241187 0 0 0
T21 2088 9 0 0
T26 0 7 0 0
T27 0 10 0 0
T28 0 7 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 789857 0 0
T1 558325 1991 0 0
T2 1346 0 0 0
T3 405883 694 0 0
T4 82568 5 0 0
T5 117293 3207 0 0
T6 0 5393 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 128 0 0
T20 241187 0 0 0
T21 2088 9 0 0
T26 0 7 0 0
T27 0 10 0 0
T28 0 7 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT82,T83,T84

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT44,T81,T66

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T82,T83,T84
0 0 1 - - Covered T44,T81,T66
0 0 0 1 - Covered T1,T4,T5
0 0 0 0 1 Covered T1,T4,T5
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 384340508 577041 0 0
UpdateCheck_A 384340508 577039 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 577041 0 0
T1 558325 2085 0 0
T2 1346 0 0 0
T3 405883 0 0 0
T4 82568 6 0 0
T5 117293 3204 0 0
T6 0 5526 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 0 0 0
T20 241187 0 0 0
T21 2088 3 0 0
T23 0 20 0 0
T26 0 2 0 0
T27 0 10 0 0
T28 0 5 0 0
T44 0 23 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 577039 0 0
T1 558325 2085 0 0
T2 1346 0 0 0
T3 405883 0 0 0
T4 82568 6 0 0
T5 117293 3204 0 0
T6 0 5526 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 0 0 0
T20 241187 0 0 0
T21 2088 3 0 0
T23 0 20 0 0
T26 0 2 0 0
T27 0 10 0 0
T28 0 5 0 0
T44 0 23 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT82,T83,T84

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT44,T81,T66

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T82,T83,T84
0 0 1 - - Covered T44,T81,T66
0 0 0 1 - Covered T1,T4,T5
0 0 0 0 1 Covered T1,T4,T5
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 384340508 576707 0 0
UpdateCheck_A 384340508 576706 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 576707 0 0
T1 558325 2085 0 0
T2 1346 0 0 0
T3 405883 0 0 0
T4 82568 6 0 0
T5 117293 3199 0 0
T6 0 5528 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 0 0 0
T20 241187 0 0 0
T21 2088 3 0 0
T23 0 20 0 0
T26 0 2 0 0
T27 0 9 0 0
T28 0 5 0 0
T44 0 23 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 576706 0 0
T1 558325 2085 0 0
T2 1346 0 0 0
T3 405883 0 0 0
T4 82568 6 0 0
T5 117293 3199 0 0
T6 0 5528 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 0 0 0
T20 241187 0 0 0
T21 2088 3 0 0
T23 0 20 0 0
T26 0 2 0 0
T27 0 9 0 0
T28 0 5 0 0
T44 0 23 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT82,T83,T84

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T44,T81

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T82,T83,T84
0 0 1 - - Covered T4,T44,T81
0 0 0 1 - Covered T1,T4,T5
0 0 0 0 1 Covered T1,T4,T5
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 384340508 576262 0 0
UpdateCheck_A 384340508 576262 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 576262 0 0
T1 558325 2085 0 0
T2 1346 0 0 0
T3 405883 0 0 0
T4 82568 5 0 0
T5 117293 3197 0 0
T6 0 5524 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 0 0 0
T20 241187 0 0 0
T21 2088 2 0 0
T23 0 20 0 0
T26 0 2 0 0
T27 0 9 0 0
T28 0 5 0 0
T44 0 23 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 576262 0 0
T1 558325 2085 0 0
T2 1346 0 0 0
T3 405883 0 0 0
T4 82568 5 0 0
T5 117293 3197 0 0
T6 0 5524 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 0 0 0
T20 241187 0 0 0
T21 2088 2 0 0
T23 0 20 0 0
T26 0 2 0 0
T27 0 9 0 0
T28 0 5 0 0
T44 0 23 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT82,T83,T84

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT27,T44,T81

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T82,T83,T84
0 0 1 - - Covered T27,T44,T81
0 0 0 1 - Covered T1,T4,T5
0 0 0 0 1 Covered T1,T4,T5
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 384340508 576055 0 0
UpdateCheck_A 384340508 576055 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 576055 0 0
T1 558325 2084 0 0
T2 1346 0 0 0
T3 405883 0 0 0
T4 82568 5 0 0
T5 117293 3195 0 0
T6 0 5527 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 0 0 0
T20 241187 0 0 0
T21 2088 2 0 0
T23 0 19 0 0
T26 0 1 0 0
T27 0 10 0 0
T28 0 4 0 0
T44 0 23 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384340508 576055 0 0
T1 558325 2084 0 0
T2 1346 0 0 0
T3 405883 0 0 0
T4 82568 5 0 0
T5 117293 3195 0 0
T6 0 5527 0 0
T17 896 0 0 0
T18 1464 0 0 0
T19 48030 0 0 0
T20 241187 0 0 0
T21 2088 2 0 0
T23 0 19 0 0
T26 0 1 0 0
T27 0 10 0 0
T28 0 4 0 0
T44 0 23 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%