Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_plain_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.82 100.00 91.27 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_plain_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.69 100.00 98.46 100.00 100.00 100.00 gen_prog_data.u_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_plain_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.61 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_plain_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.38 100.00 96.92 100.00 100.00 100.00 gen_prog_data.u_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_secded_hamming_72_64_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_plain_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_plain_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_plain_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_plain_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%