Line Coverage for Module :
prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Line Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
2 |
2 |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 43 | 42 | 97.67 |
Logical | 43 | 42 | 97.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T21,T26 |
1 | 1 | Covered | T18,T5,T21 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T5,T6,T58 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Unreachable | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T5,T6,T58 |
1 | 1 | 0 | Covered | T18,T5,T21 |
1 | 1 | 1 | Unreachable | T18,T5,T21 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Unreachable | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T5,T21 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T18,T5,T21 |
1 | 1 | Covered | T18,T5,T21 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T58 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T58 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T18,T5,T21 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T5,T21 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Cond Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 51 | 44 | 86.27 |
Logical | 51 | 44 | 86.27 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T21,T26 |
1 | 1 | Covered | T18,T5,T21 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T18,T5,T21 |
1 | 1 | 1 | Covered | T18,T5,T21 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T5,T21 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T5,T21 |
1 | 1 | Covered | T18,T5,T21 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T18,T5,T21 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T5,T21 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Cond Coverage for Module :
prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T52,T157,T158 |
1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T23 |
1 | 0 | Covered | T5,T6,T23 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T23 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T27 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T28 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
Branch Coverage for Module :
prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_arbiter_tree
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
3349950 |
3348972 |
0 |
0 |
T2 |
8076 |
6786 |
0 |
0 |
T3 |
2435298 |
2324838 |
0 |
0 |
T4 |
495408 |
494400 |
0 |
0 |
T5 |
703758 |
702780 |
0 |
0 |
T17 |
5376 |
4842 |
0 |
0 |
T18 |
8784 |
7926 |
0 |
0 |
T19 |
288180 |
287742 |
0 |
0 |
T20 |
1447122 |
1446204 |
0 |
0 |
T21 |
12528 |
11580 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6312 |
6312 |
0 |
0 |
T1 |
6 |
6 |
0 |
0 |
T2 |
6 |
6 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
6 |
6 |
0 |
0 |
T5 |
6 |
6 |
0 |
0 |
T17 |
6 |
6 |
0 |
0 |
T18 |
6 |
6 |
0 |
0 |
T19 |
6 |
6 |
0 |
0 |
T20 |
6 |
6 |
0 |
0 |
T21 |
6 |
6 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
71580510 |
0 |
0 |
T1 |
3349950 |
16427 |
0 |
0 |
T2 |
8076 |
268 |
0 |
0 |
T3 |
2435298 |
49296 |
0 |
0 |
T4 |
495408 |
161 |
0 |
0 |
T5 |
703758 |
128318 |
0 |
0 |
T6 |
0 |
43663 |
0 |
0 |
T17 |
5376 |
128 |
0 |
0 |
T18 |
8784 |
260 |
0 |
0 |
T19 |
288180 |
1528 |
0 |
0 |
T20 |
1447122 |
128 |
0 |
0 |
T21 |
12528 |
496 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T26 |
0 |
29 |
0 |
0 |
T27 |
0 |
71 |
0 |
0 |
T28 |
0 |
39 |
0 |
0 |
T44 |
0 |
80 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
71580510 |
0 |
0 |
T1 |
3349950 |
16427 |
0 |
0 |
T2 |
8076 |
268 |
0 |
0 |
T3 |
2435298 |
49296 |
0 |
0 |
T4 |
495408 |
161 |
0 |
0 |
T5 |
703758 |
128318 |
0 |
0 |
T6 |
0 |
43663 |
0 |
0 |
T17 |
5376 |
128 |
0 |
0 |
T18 |
8784 |
260 |
0 |
0 |
T19 |
288180 |
1528 |
0 |
0 |
T20 |
1447122 |
128 |
0 |
0 |
T21 |
12528 |
496 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T26 |
0 |
29 |
0 |
0 |
T27 |
0 |
71 |
0 |
0 |
T28 |
0 |
39 |
0 |
0 |
T44 |
0 |
80 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
3349950 |
3348972 |
0 |
0 |
T2 |
8076 |
6786 |
0 |
0 |
T3 |
2435298 |
2324838 |
0 |
0 |
T4 |
495408 |
494400 |
0 |
0 |
T5 |
703758 |
702780 |
0 |
0 |
T17 |
5376 |
4842 |
0 |
0 |
T18 |
8784 |
7926 |
0 |
0 |
T19 |
288180 |
287742 |
0 |
0 |
T20 |
1447122 |
1446204 |
0 |
0 |
T21 |
12528 |
11580 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
3349950 |
3348972 |
0 |
0 |
T2 |
8076 |
6786 |
0 |
0 |
T3 |
2435298 |
2324838 |
0 |
0 |
T4 |
495408 |
494400 |
0 |
0 |
T5 |
703758 |
702780 |
0 |
0 |
T17 |
5376 |
4842 |
0 |
0 |
T18 |
8784 |
7926 |
0 |
0 |
T19 |
288180 |
287742 |
0 |
0 |
T20 |
1447122 |
1446204 |
0 |
0 |
T21 |
12528 |
11580 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
71580510 |
0 |
0 |
T1 |
3349950 |
16427 |
0 |
0 |
T2 |
8076 |
268 |
0 |
0 |
T3 |
2435298 |
49296 |
0 |
0 |
T4 |
495408 |
161 |
0 |
0 |
T5 |
703758 |
128318 |
0 |
0 |
T6 |
0 |
43663 |
0 |
0 |
T17 |
5376 |
128 |
0 |
0 |
T18 |
8784 |
260 |
0 |
0 |
T19 |
288180 |
1528 |
0 |
0 |
T20 |
1447122 |
128 |
0 |
0 |
T21 |
12528 |
496 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T26 |
0 |
29 |
0 |
0 |
T27 |
0 |
71 |
0 |
0 |
T28 |
0 |
39 |
0 |
0 |
T44 |
0 |
80 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
66360818 |
0 |
0 |
T1 |
2233300 |
130 |
0 |
0 |
T2 |
5384 |
268 |
0 |
0 |
T3 |
1623532 |
48208 |
0 |
0 |
T4 |
330272 |
128 |
0 |
0 |
T5 |
469172 |
102712 |
0 |
0 |
T17 |
3584 |
128 |
0 |
0 |
T18 |
5856 |
260 |
0 |
0 |
T19 |
192120 |
1024 |
0 |
0 |
T20 |
964748 |
128 |
0 |
0 |
T21 |
8352 |
456 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1954896122 |
0 |
0 |
T1 |
3349950 |
2236816 |
0 |
0 |
T2 |
8076 |
6183 |
0 |
0 |
T3 |
2435298 |
2066237 |
0 |
0 |
T4 |
495408 |
366639 |
0 |
0 |
T5 |
703758 |
264717 |
0 |
0 |
T17 |
5376 |
4554 |
0 |
0 |
T18 |
8784 |
7342 |
0 |
0 |
T19 |
288180 |
259209 |
0 |
0 |
T20 |
1447122 |
1445916 |
0 |
0 |
T21 |
12528 |
8903 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
71580510 |
0 |
0 |
T1 |
3349950 |
16427 |
0 |
0 |
T2 |
8076 |
268 |
0 |
0 |
T3 |
2435298 |
49296 |
0 |
0 |
T4 |
495408 |
161 |
0 |
0 |
T5 |
703758 |
128318 |
0 |
0 |
T6 |
0 |
43663 |
0 |
0 |
T17 |
5376 |
128 |
0 |
0 |
T18 |
8784 |
260 |
0 |
0 |
T19 |
288180 |
1528 |
0 |
0 |
T20 |
1447122 |
128 |
0 |
0 |
T21 |
12528 |
496 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T26 |
0 |
29 |
0 |
0 |
T27 |
0 |
71 |
0 |
0 |
T28 |
0 |
39 |
0 |
0 |
T44 |
0 |
80 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
71580510 |
0 |
0 |
T1 |
3349950 |
16427 |
0 |
0 |
T2 |
8076 |
268 |
0 |
0 |
T3 |
2435298 |
49296 |
0 |
0 |
T4 |
495408 |
161 |
0 |
0 |
T5 |
703758 |
128318 |
0 |
0 |
T6 |
0 |
43663 |
0 |
0 |
T17 |
5376 |
128 |
0 |
0 |
T18 |
8784 |
260 |
0 |
0 |
T19 |
288180 |
1528 |
0 |
0 |
T20 |
1447122 |
128 |
0 |
0 |
T21 |
12528 |
496 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T26 |
0 |
29 |
0 |
0 |
T27 |
0 |
71 |
0 |
0 |
T28 |
0 |
39 |
0 |
0 |
T44 |
0 |
80 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
336092463 |
0 |
0 |
T1 |
3349950 |
1112115 |
0 |
0 |
T2 |
8076 |
536 |
0 |
0 |
T3 |
2435298 |
249105 |
0 |
0 |
T4 |
495408 |
127720 |
0 |
0 |
T5 |
703758 |
437991 |
0 |
0 |
T6 |
0 |
777386 |
0 |
0 |
T17 |
5376 |
256 |
0 |
0 |
T18 |
8784 |
520 |
0 |
0 |
T19 |
288180 |
28493 |
0 |
0 |
T20 |
1447122 |
256 |
0 |
0 |
T21 |
12528 |
2604 |
0 |
0 |
T23 |
0 |
6444 |
0 |
0 |
T26 |
0 |
882 |
0 |
0 |
T27 |
0 |
8919 |
0 |
0 |
T28 |
0 |
2548 |
0 |
0 |
T44 |
0 |
14541 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
66360590 |
0 |
0 |
T1 |
2233300 |
130 |
0 |
0 |
T2 |
5384 |
268 |
0 |
0 |
T3 |
1623532 |
48208 |
0 |
0 |
T4 |
330272 |
128 |
0 |
0 |
T5 |
469172 |
102712 |
0 |
0 |
T17 |
3584 |
128 |
0 |
0 |
T18 |
5856 |
260 |
0 |
0 |
T19 |
192120 |
1024 |
0 |
0 |
T20 |
964748 |
128 |
0 |
0 |
T21 |
8352 |
456 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
6282 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
3349950 |
3348972 |
0 |
0 |
T2 |
8076 |
6786 |
0 |
0 |
T3 |
2435298 |
2324838 |
0 |
0 |
T4 |
495408 |
494400 |
0 |
0 |
T5 |
703758 |
702780 |
0 |
0 |
T17 |
5376 |
4842 |
0 |
0 |
T18 |
8784 |
7926 |
0 |
0 |
T19 |
288180 |
287742 |
0 |
0 |
T20 |
1447122 |
1446204 |
0 |
0 |
T21 |
12528 |
11580 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1537362032 |
66360816 |
0 |
0 |
T1 |
2233300 |
130 |
0 |
0 |
T2 |
5384 |
268 |
0 |
0 |
T3 |
1623532 |
48208 |
0 |
0 |
T4 |
330272 |
128 |
0 |
0 |
T5 |
469172 |
102712 |
0 |
0 |
T17 |
3584 |
128 |
0 |
0 |
T18 |
5856 |
260 |
0 |
0 |
T19 |
192120 |
1024 |
0 |
0 |
T20 |
964748 |
128 |
0 |
0 |
T21 |
8352 |
456 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T19 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T157,T158,T159 |
1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T1,T3,T4 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T4 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T23 |
1 | 0 | Covered | T5,T6,T23 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T23 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T27 |
1 | 0 | Covered | T1,T3,T4 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T28 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1052 |
1052 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
3010899 |
0 |
0 |
T1 |
558325 |
7962 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
1088 |
0 |
0 |
T4 |
82568 |
16 |
0 |
0 |
T5 |
117293 |
12815 |
0 |
0 |
T6 |
0 |
21562 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
504 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
34 |
0 |
0 |
T26 |
0 |
26 |
0 |
0 |
T27 |
0 |
38 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
3010899 |
0 |
0 |
T1 |
558325 |
7962 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
1088 |
0 |
0 |
T4 |
82568 |
16 |
0 |
0 |
T5 |
117293 |
12815 |
0 |
0 |
T6 |
0 |
21562 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
504 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
34 |
0 |
0 |
T26 |
0 |
26 |
0 |
0 |
T27 |
0 |
38 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
3010899 |
0 |
0 |
T1 |
558325 |
7962 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
1088 |
0 |
0 |
T4 |
82568 |
16 |
0 |
0 |
T5 |
117293 |
12815 |
0 |
0 |
T6 |
0 |
21562 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
504 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
34 |
0 |
0 |
T26 |
0 |
26 |
0 |
0 |
T27 |
0 |
38 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
262230833 |
0 |
0 |
T1 |
558325 |
2249 |
0 |
0 |
T2 |
1346 |
1064 |
0 |
0 |
T3 |
405883 |
225288 |
0 |
0 |
T4 |
82568 |
16952 |
0 |
0 |
T5 |
117293 |
780 |
0 |
0 |
T17 |
896 |
775 |
0 |
0 |
T18 |
1464 |
1257 |
0 |
0 |
T19 |
48030 |
21472 |
0 |
0 |
T20 |
241187 |
241002 |
0 |
0 |
T21 |
2088 |
918 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
3010899 |
0 |
0 |
T1 |
558325 |
7962 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
1088 |
0 |
0 |
T4 |
82568 |
16 |
0 |
0 |
T5 |
117293 |
12815 |
0 |
0 |
T6 |
0 |
21562 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
504 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
34 |
0 |
0 |
T26 |
0 |
26 |
0 |
0 |
T27 |
0 |
38 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
3010899 |
0 |
0 |
T1 |
558325 |
7962 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
1088 |
0 |
0 |
T4 |
82568 |
16 |
0 |
0 |
T5 |
117293 |
12815 |
0 |
0 |
T6 |
0 |
21562 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
504 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
34 |
0 |
0 |
T26 |
0 |
26 |
0 |
0 |
T27 |
0 |
38 |
0 |
0 |
T28 |
0 |
24 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
115850033 |
0 |
0 |
T1 |
558325 |
555876 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
152689 |
0 |
0 |
T4 |
82568 |
65412 |
0 |
0 |
T5 |
117293 |
116282 |
0 |
0 |
T6 |
0 |
388702 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
26445 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
943 |
0 |
0 |
T26 |
0 |
433 |
0 |
0 |
T27 |
0 |
4358 |
0 |
0 |
T28 |
0 |
1276 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
0 |
0 |
1047 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T27 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T27 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T52,T157,T158 |
1 | 1 | Covered | T1,T4,T5 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T5 |
1 | 0 | 1 | Covered | T1,T4,T5 |
1 | 1 | 0 | Covered | T1,T4,T5 |
1 | 1 | 1 | Covered | T1,T4,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T38 |
1 | 0 | Covered | T5,T6,T58 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T58 |
1 | 0 | Covered | T1,T4,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T58 |
1 | 0 | Covered | T1,T4,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T58 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1052 |
1052 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
2208795 |
0 |
0 |
T1 |
558325 |
8335 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
0 |
0 |
0 |
T4 |
82568 |
17 |
0 |
0 |
T5 |
117293 |
12791 |
0 |
0 |
T6 |
0 |
22101 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
0 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
6 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T27 |
0 |
33 |
0 |
0 |
T28 |
0 |
15 |
0 |
0 |
T44 |
0 |
80 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
2208795 |
0 |
0 |
T1 |
558325 |
8335 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
0 |
0 |
0 |
T4 |
82568 |
17 |
0 |
0 |
T5 |
117293 |
12791 |
0 |
0 |
T6 |
0 |
22101 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
0 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
6 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T27 |
0 |
33 |
0 |
0 |
T28 |
0 |
15 |
0 |
0 |
T44 |
0 |
80 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
2208795 |
0 |
0 |
T1 |
558325 |
8335 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
0 |
0 |
0 |
T4 |
82568 |
17 |
0 |
0 |
T5 |
117293 |
12791 |
0 |
0 |
T6 |
0 |
22101 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
0 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
6 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T27 |
0 |
33 |
0 |
0 |
T28 |
0 |
15 |
0 |
0 |
T44 |
0 |
80 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
291334537 |
0 |
0 |
T1 |
558325 |
2179 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
20343 |
0 |
0 |
T5 |
117293 |
841 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1177 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
2208795 |
0 |
0 |
T1 |
558325 |
8335 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
0 |
0 |
0 |
T4 |
82568 |
17 |
0 |
0 |
T5 |
117293 |
12791 |
0 |
0 |
T6 |
0 |
22101 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
0 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
6 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T27 |
0 |
33 |
0 |
0 |
T28 |
0 |
15 |
0 |
0 |
T44 |
0 |
80 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
2208795 |
0 |
0 |
T1 |
558325 |
8335 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
0 |
0 |
0 |
T4 |
82568 |
17 |
0 |
0 |
T5 |
117293 |
12791 |
0 |
0 |
T6 |
0 |
22101 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
0 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
6 |
0 |
0 |
T23 |
0 |
75 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T27 |
0 |
33 |
0 |
0 |
T28 |
0 |
15 |
0 |
0 |
T44 |
0 |
80 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
87520666 |
0 |
0 |
T1 |
558325 |
555979 |
0 |
0 |
T2 |
1346 |
0 |
0 |
0 |
T3 |
405883 |
0 |
0 |
0 |
T4 |
82568 |
62052 |
0 |
0 |
T5 |
117293 |
116285 |
0 |
0 |
T6 |
0 |
388684 |
0 |
0 |
T17 |
896 |
0 |
0 |
0 |
T18 |
1464 |
0 |
0 |
0 |
T19 |
48030 |
0 |
0 |
0 |
T20 |
241187 |
0 |
0 |
0 |
T21 |
2088 |
749 |
0 |
0 |
T23 |
0 |
6444 |
0 |
0 |
T26 |
0 |
449 |
0 |
0 |
T27 |
0 |
4561 |
0 |
0 |
T28 |
0 |
1272 |
0 |
0 |
T44 |
0 |
14541 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
0 |
0 |
1047 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
2 |
2 |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 51 | 44 | 86.27 |
Logical | 51 | 44 | 86.27 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T21,T26 |
1 | 1 | Covered | T18,T5,T21 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T18,T5,T21 |
1 | 1 | 1 | Covered | T18,T5,T21 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T5,T21 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T5,T21 |
1 | 1 | Covered | T18,T5,T21 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T18,T5,T21 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T5,T21 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1052 |
1052 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
351879294 |
0 |
0 |
T1 |
558325 |
558098 |
0 |
0 |
T2 |
1346 |
997 |
0 |
0 |
T3 |
405883 |
363369 |
0 |
0 |
T4 |
82568 |
82336 |
0 |
0 |
T5 |
117293 |
65774 |
0 |
0 |
T17 |
896 |
743 |
0 |
0 |
T18 |
1464 |
1191 |
0 |
0 |
T19 |
48030 |
47445 |
0 |
0 |
T20 |
241187 |
240970 |
0 |
0 |
T21 |
2088 |
1702 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
31633835 |
0 |
0 |
T1 |
558325 |
64 |
0 |
0 |
T2 |
1346 |
134 |
0 |
0 |
T3 |
405883 |
24104 |
0 |
0 |
T4 |
82568 |
64 |
0 |
0 |
T5 |
117293 |
51356 |
0 |
0 |
T17 |
896 |
64 |
0 |
0 |
T18 |
1464 |
130 |
0 |
0 |
T19 |
48030 |
512 |
0 |
0 |
T20 |
241187 |
64 |
0 |
0 |
T21 |
2088 |
228 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
0 |
0 |
1047 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
2 |
2 |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 51 | 44 | 86.27 |
Logical | 51 | 44 | 86.27 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T21,T26 |
1 | 1 | Covered | T18,T5,T21 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T18,T5,T21 |
1 | 1 | 1 | Covered | T18,T5,T21 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T5,T21 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T5,T21 |
1 | 1 | Covered | T18,T5,T21 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T18,T5,T21 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T5,T21 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1052 |
1052 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
351879294 |
0 |
0 |
T1 |
558325 |
558098 |
0 |
0 |
T2 |
1346 |
997 |
0 |
0 |
T3 |
405883 |
363369 |
0 |
0 |
T4 |
82568 |
82336 |
0 |
0 |
T5 |
117293 |
65774 |
0 |
0 |
T17 |
896 |
743 |
0 |
0 |
T18 |
1464 |
1191 |
0 |
0 |
T19 |
48030 |
47445 |
0 |
0 |
T20 |
241187 |
240970 |
0 |
0 |
T21 |
2088 |
1702 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
31633835 |
0 |
0 |
T1 |
558325 |
64 |
0 |
0 |
T2 |
1346 |
134 |
0 |
0 |
T3 |
405883 |
24104 |
0 |
0 |
T4 |
82568 |
64 |
0 |
0 |
T5 |
117293 |
51356 |
0 |
0 |
T17 |
896 |
64 |
0 |
0 |
T18 |
1464 |
130 |
0 |
0 |
T19 |
48030 |
512 |
0 |
0 |
T20 |
241187 |
64 |
0 |
0 |
T21 |
2088 |
228 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
0 |
0 |
1047 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
15816913 |
0 |
0 |
T1 |
558325 |
32 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
|
unreachable |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 43 | 42 | 97.67 |
Logical | 43 | 42 | 97.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T21,T26 |
1 | 1 | Covered | T18,T5,T21 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T5,T6,T58 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Unreachable | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T5,T6,T58 |
1 | 1 | 0 | Covered | T18,T5,T21 |
1 | 1 | 1 | Unreachable | T18,T5,T21 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Unreachable | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T5,T21 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T18,T5,T21 |
1 | 1 | Covered | T18,T5,T21 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T58 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T58 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T18,T5,T21 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T5,T21 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1052 |
1052 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340423 |
17363496 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
348786040 |
0 |
0 |
T1 |
558325 |
558096 |
0 |
0 |
T2 |
1346 |
997 |
0 |
0 |
T3 |
405883 |
363369 |
0 |
0 |
T4 |
82568 |
82336 |
0 |
0 |
T5 |
117293 |
65774 |
0 |
0 |
T17 |
896 |
743 |
0 |
0 |
T18 |
1464 |
1191 |
0 |
0 |
T19 |
48030 |
47445 |
0 |
0 |
T20 |
241187 |
240970 |
0 |
0 |
T21 |
2088 |
1702 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
34727089 |
0 |
0 |
T1 |
558325 |
66 |
0 |
0 |
T2 |
1346 |
134 |
0 |
0 |
T3 |
405883 |
24104 |
0 |
0 |
T4 |
82568 |
64 |
0 |
0 |
T5 |
117293 |
51356 |
0 |
0 |
T17 |
896 |
64 |
0 |
0 |
T18 |
1464 |
130 |
0 |
0 |
T19 |
48030 |
512 |
0 |
0 |
T20 |
241187 |
64 |
0 |
0 |
T21 |
2088 |
228 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384303912 |
17363382 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
0 |
0 |
1047 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
|
unreachable |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 43 | 42 | 97.67 |
Logical | 43 | 42 | 97.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T21,T26 |
1 | 1 | Covered | T18,T5,T21 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T5,T6,T58 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Unreachable | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T5,T6,T58 |
1 | 1 | 0 | Covered | T18,T5,T21 |
1 | 1 | 1 | Unreachable | T18,T5,T21 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Unreachable | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T18,T5,T21 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T18,T5,T21 |
1 | 1 | Covered | T18,T5,T21 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T58 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T58 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T18,T5,T21 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T18,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T5,T21 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1052 |
1052 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340423 |
17363496 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
348786124 |
0 |
0 |
T1 |
558325 |
558096 |
0 |
0 |
T2 |
1346 |
997 |
0 |
0 |
T3 |
405883 |
363369 |
0 |
0 |
T4 |
82568 |
82336 |
0 |
0 |
T5 |
117293 |
65774 |
0 |
0 |
T17 |
896 |
743 |
0 |
0 |
T18 |
1464 |
1191 |
0 |
0 |
T19 |
48030 |
47445 |
0 |
0 |
T20 |
241187 |
240970 |
0 |
0 |
T21 |
2088 |
1702 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
34727005 |
0 |
0 |
T1 |
558325 |
66 |
0 |
0 |
T2 |
1346 |
134 |
0 |
0 |
T3 |
405883 |
24104 |
0 |
0 |
T4 |
82568 |
64 |
0 |
0 |
T5 |
117293 |
51356 |
0 |
0 |
T17 |
896 |
64 |
0 |
0 |
T18 |
1464 |
130 |
0 |
0 |
T19 |
48030 |
512 |
0 |
0 |
T20 |
241187 |
64 |
0 |
0 |
T21 |
2088 |
228 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384303912 |
17363382 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
0 |
0 |
1047 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
383513129 |
0 |
0 |
T1 |
558325 |
558162 |
0 |
0 |
T2 |
1346 |
1131 |
0 |
0 |
T3 |
405883 |
387473 |
0 |
0 |
T4 |
82568 |
82400 |
0 |
0 |
T5 |
117293 |
117130 |
0 |
0 |
T17 |
896 |
807 |
0 |
0 |
T18 |
1464 |
1321 |
0 |
0 |
T19 |
48030 |
47957 |
0 |
0 |
T20 |
241187 |
241034 |
0 |
0 |
T21 |
2088 |
1930 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
384340508 |
17363495 |
0 |
0 |
T1 |
558325 |
33 |
0 |
0 |
T2 |
1346 |
67 |
0 |
0 |
T3 |
405883 |
12052 |
0 |
0 |
T4 |
82568 |
32 |
0 |
0 |
T5 |
117293 |
25678 |
0 |
0 |
T17 |
896 |
32 |
0 |
0 |
T18 |
1464 |
65 |
0 |
0 |
T19 |
48030 |
256 |
0 |
0 |
T20 |
241187 |
32 |
0 |
0 |
T21 |
2088 |
114 |
0 |
0 |