Module Definition
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Module Instance : tb.dut.gen_alert_senders[4].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.78 77.78


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.78 77.78


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.69 97.12 93.60 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_senders[0].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.69 97.12 93.60 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_senders[1].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.69 97.12 93.60 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_senders[2].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.69 97.12 93.60 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_senders[3].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.69 97.12 93.60 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
alert_req_i Yes Yes T2,T18,T19 Yes T2,T18,T19 INPUT
alert_ack_o Yes Yes T18,T19,T5 Yes T18,T19,T5 OUTPUT
alert_state_o Yes Yes T2,T18,T19 Yes T2,T18,T19 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T2,T18,T19 Yes T2,T18,T19 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T2,T18,T19 Yes T2,T18,T19 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[4].u_alert_sender
TotalCoveredPercent
Totals 9 7 77.78
Total Bits 18 14 77.78
Total Bits 0->1 9 7 77.78
Total Bits 1->0 9 7 77.78

Ports 9 7 77.78
Port Bits 18 14 77.78
Port Bits 0->1 9 7 77.78
Port Bits 1->0 9 7 77.78

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
alert_req_i Unreachable Unreachable Unreachable INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T95,T96,T97 Yes T95,T96,T97 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[0].u_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
alert_req_i Yes Yes T18,T19,T5 Yes T18,T19,T5 INPUT
alert_ack_o Yes Yes T18,T19,T5 Yes T18,T19,T5 OUTPUT
alert_state_o Yes Yes T18,T19,T5 Yes T18,T19,T5 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T18,T19,T5 Yes T18,T19,T5 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T18,T19,T5 Yes T18,T19,T5 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[1].u_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
alert_req_i Yes Yes T2,T13,T119 Yes T2,T13,T119 INPUT
alert_ack_o Yes Yes T119,T176,T14 Yes T119,T176,T14 OUTPUT
alert_state_o Yes Yes T2,T13,T119 Yes T2,T13,T119 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T2,T13,T119 Yes T2,T13,T119 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T2,T13,T119 Yes T2,T13,T119 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[2].u_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
alert_req_i Yes Yes T2,T20,T21 Yes T2,T20,T21 INPUT
alert_ack_o Yes Yes T20,T21,T26 Yes T20,T21,T26 OUTPUT
alert_state_o Yes Yes T20,T21,T26 Yes T20,T21,T26 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T20,T21,T26 Yes T20,T21,T26 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T20,T21,T26 Yes T20,T21,T26 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[3].u_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
alert_req_i Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
alert_ack_o Yes Yes T106,T241,T254 Yes T106,T241,T254 OUTPUT
alert_state_o Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T95,T96,T97 Yes T95,T96,T97 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T95,T96,T97 Yes T95,T96,T97 OUTPUT

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