Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 19104 1 T58 297 T59 17 T102 771
full_word 4105652 1 T2 9 T16 4 T4 41854


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 4124461 1 T2 9 T16 4 T4 41854
auto[TlIntgErrCmd] 90 1 T59 8 T101 2 T209 3
auto[TlIntgErrData] 97 1 T59 5 T101 6 T209 4
auto[TlIntgErrBoth] 108 1 T59 5 T101 5 T209 2


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4100281 1 T2 9 T16 4 T4 41854
auto[1] 24475 1 T58 386 T59 9 T102 1010


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrBoth]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1159 1 T102 50 T208 13 T220 51
auto[TlIntgErrNone] partial auto[1] 17666 1 T58 297 T102 721 T208 146
auto[TlIntgErrNone] full_word auto[0] 4099001 1 T2 9 T16 4 T4 41854
auto[TlIntgErrNone] full_word auto[1] 6635 1 T58 89 T102 289 T208 86
auto[TlIntgErrCmd] partial auto[0] 25 1 T59 3 T209 2 T228 3
auto[TlIntgErrCmd] partial auto[1] 60 1 T59 4 T101 2 T209 1
auto[TlIntgErrCmd] full_word auto[0] 3 1 T59 1 T228 1 T225 1
auto[TlIntgErrCmd] full_word auto[1] 2 1 T367 1 T363 1 - -
auto[TlIntgErrData] partial auto[0] 47 1 T59 3 T101 1 T209 2
auto[TlIntgErrData] partial auto[1] 45 1 T59 2 T101 5 T209 2
auto[TlIntgErrData] full_word auto[0] 4 1 T228 1 T222 1 T368 1
auto[TlIntgErrData] full_word auto[1] 1 1 T222 1 - - - -
auto[TlIntgErrBoth] partial auto[0] 42 1 T59 2 T101 1 T209 1
auto[TlIntgErrBoth] partial auto[1] 60 1 T59 3 T101 4 T209 1
auto[TlIntgErrBoth] full_word auto[1] 6 1 T228 1 T262 2 T367 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 23833336 1 T1 61 T2 321 T3 64
full_word 8289732 1 T1 83 T2 153 T3 47


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 32122748 1 T1 144 T2 474 T3 111
auto[TlIntgErrCmd] 102 1 T59 6 T101 7 T209 2
auto[TlIntgErrData] 117 1 T59 10 T101 5 T209 4
auto[TlIntgErrBoth] 101 1 T59 4 T101 8 T209 4


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27438517 1 T1 69 T2 390 T3 61
auto[1] 4684551 1 T1 75 T2 84 T3 50


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 23063990 1 T1 49 T2 303 T3 60
auto[TlIntgErrNone] partial auto[1] 769054 1 T1 12 T2 18 T3 4
auto[TlIntgErrNone] full_word auto[0] 4374359 1 T1 20 T2 87 T3 1
auto[TlIntgErrNone] full_word auto[1] 3915345 1 T1 63 T2 66 T3 46
auto[TlIntgErrCmd] partial auto[0] 48 1 T59 1 T101 5 T209 1
auto[TlIntgErrCmd] partial auto[1] 45 1 T59 5 T101 2 T209 1
auto[TlIntgErrCmd] full_word auto[0] 6 1 T228 1 T229 2 T368 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T221 1 T368 1 T365 1
auto[TlIntgErrData] partial auto[0] 54 1 T59 5 T101 4 T209 1
auto[TlIntgErrData] partial auto[1] 52 1 T59 4 T101 1 T209 1
auto[TlIntgErrData] full_word auto[0] 9 1 T59 1 T209 2 T228 1
auto[TlIntgErrData] full_word auto[1] 2 1 T221 1 T369 1 - -
auto[TlIntgErrBoth] partial auto[0] 48 1 T59 3 T101 4 T209 1
auto[TlIntgErrBoth] partial auto[1] 45 1 T59 1 T101 4 T209 1
auto[TlIntgErrBoth] full_word auto[0] 3 1 T369 1 T370 1 T371 1
auto[TlIntgErrBoth] full_word auto[1] 5 1 T209 2 T372 1 T364 1

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