Module Definition
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Module : flash_phy_rd_buf_dep
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.61 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.76 100.00 91.05 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Module : flash_phy_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T16 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T16
110Not Covered
111CoveredT1,T2,T16 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T16
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT1,T2,T16 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T16
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T16
Branch Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T16 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T16 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T16
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T16
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T16
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T16
0 - 0 Covered T1,T2,T3

Assert Coverage for Module : flash_phy_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 805191632 7228664 0 0
BufferDepRsp_A 805191632 803484554 0 0
BufferIncrOverFlow_A 805191632 7228669 0 0
DepBufferRspOrder_A 805191634 17102192 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805191632 7228664 0 0
T1 2531 16 0 0
T2 4266 88 0 0
T3 4178 0 0 0
T4 848070 48701 0 0
T5 0 211 0 0
T6 0 46256 0 0
T10 7886 0 0 0
T11 1671264 2560 0 0
T16 3186 65 0 0
T17 6410 0 0 0
T18 4614 17 0 0
T19 2636 0 0 0
T24 0 74 0 0
T28 114179 0 0 0
T38 0 192 0 0
T53 0 380 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805191632 803484554 0 0
T1 5062 4884 0 0
T2 4266 4048 0 0
T3 4178 3886 0 0
T4 848070 847928 0 0
T10 7886 6684 0 0
T11 1671264 1671218 0 0
T16 3186 2862 0 0
T17 6410 5200 0 0
T18 4614 4458 0 0
T19 2636 2504 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805191632 7228669 0 0
T1 2531 16 0 0
T2 4266 88 0 0
T3 4178 0 0 0
T4 848070 48701 0 0
T5 0 211 0 0
T6 0 46256 0 0
T10 7886 0 0 0
T11 1671264 2560 0 0
T16 3186 65 0 0
T17 6410 0 0 0
T18 4614 17 0 0
T19 2636 0 0 0
T24 0 74 0 0
T28 114179 0 0 0
T38 0 192 0 0
T53 0 380 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805191634 17102192 0 0
T1 5062 48 0 0
T2 4266 152 0 0
T3 4178 64 0 0
T4 848070 48733 0 0
T5 0 107 0 0
T6 0 24004 0 0
T10 7886 200 0 0
T11 1671264 537632 0 0
T16 3186 129 0 0
T17 6410 169 0 0
T18 4614 49 0 0
T19 2636 32 0 0
T24 0 6 0 0
T38 0 131 0 0
T53 0 223 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT2,T16,T18 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T16,T18
110Not Covered
111CoveredT2,T16,T18 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT2,T16,T18
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T131,T55
11CoveredT2,T16,T18 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT2,T16,T18
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT5,T131,T55
10CoveredT1,T2,T3
11CoveredT2,T16,T18
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T16,T18 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T16,T18 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T2,T16,T18
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T2,T16,T18
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T16,T18
0 0 - Covered T1,T2,T3
0 - 1 Covered T2,T16,T18
0 - 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 402595816 3969174 0 0
BufferDepRsp_A 402595816 401742277 0 0
BufferIncrOverFlow_A 402595816 3969176 0 0
DepBufferRspOrder_A 402595817 9227215 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402595816 3969174 0 0
T2 2133 83 0 0
T3 2089 0 0 0
T4 424035 25102 0 0
T5 0 104 0 0
T6 0 22252 0 0
T10 3943 0 0 0
T11 835632 2048 0 0
T16 1593 65 0 0
T17 3205 0 0 0
T18 2307 13 0 0
T19 1318 0 0 0
T24 0 68 0 0
T28 114179 0 0 0
T38 0 61 0 0
T53 0 157 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402595816 401742277 0 0
T1 2531 2442 0 0
T2 2133 2024 0 0
T3 2089 1943 0 0
T4 424035 423964 0 0
T10 3943 3342 0 0
T11 835632 835609 0 0
T16 1593 1431 0 0
T17 3205 2600 0 0
T18 2307 2229 0 0
T19 1318 1252 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402595816 3969176 0 0
T2 2133 83 0 0
T3 2089 0 0 0
T4 424035 25102 0 0
T5 0 104 0 0
T6 0 22252 0 0
T10 3943 0 0 0
T11 835632 2048 0 0
T16 1593 65 0 0
T17 3205 0 0 0
T18 2307 13 0 0
T19 1318 0 0 0
T24 0 68 0 0
T28 114179 0 0 0
T38 0 61 0 0
T53 0 157 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402595817 9227215 0 0
T1 2531 32 0 0
T2 2133 147 0 0
T3 2089 64 0 0
T4 424035 25134 0 0
T10 3943 200 0 0
T11 835632 273440 0 0
T16 1593 129 0 0
T17 3205 169 0 0
T18 2307 45 0 0
T19 1318 32 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT11,T13,T71
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T18 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T18
110Not Covered
111CoveredT1,T2,T18 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T18
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT1,T2,T18 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T18
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T18
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T18 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T18 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T18
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T18
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T18
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T18
0 - 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 402595816 3259490 0 0
BufferDepRsp_A 402595816 401742277 0 0
BufferIncrOverFlow_A 402595816 3259493 0 0
DepBufferRspOrder_A 402595817 7874977 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402595816 3259490 0 0
T1 2531 16 0 0
T2 2133 5 0 0
T3 2089 0 0 0
T4 424035 23599 0 0
T5 0 107 0 0
T6 0 24004 0 0
T10 3943 0 0 0
T11 835632 512 0 0
T16 1593 0 0 0
T17 3205 0 0 0
T18 2307 4 0 0
T19 1318 0 0 0
T24 0 6 0 0
T38 0 131 0 0
T53 0 223 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402595816 401742277 0 0
T1 2531 2442 0 0
T2 2133 2024 0 0
T3 2089 1943 0 0
T4 424035 423964 0 0
T10 3943 3342 0 0
T11 835632 835609 0 0
T16 1593 1431 0 0
T17 3205 2600 0 0
T18 2307 2229 0 0
T19 1318 1252 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402595816 3259493 0 0
T1 2531 16 0 0
T2 2133 5 0 0
T3 2089 0 0 0
T4 424035 23599 0 0
T5 0 107 0 0
T6 0 24004 0 0
T10 3943 0 0 0
T11 835632 512 0 0
T16 1593 0 0 0
T17 3205 0 0 0
T18 2307 4 0 0
T19 1318 0 0 0
T24 0 6 0 0
T38 0 131 0 0
T53 0 223 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402595817 7874977 0 0
T1 2531 16 0 0
T2 2133 5 0 0
T3 2089 0 0 0
T4 424035 23599 0 0
T5 0 107 0 0
T6 0 24004 0 0
T10 3943 0 0 0
T11 835632 264192 0 0
T16 1593 0 0 0
T17 3205 0 0 0
T18 2307 4 0 0
T19 1318 0 0 0
T24 0 6 0 0
T38 0 131 0 0
T53 0 223 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%