Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T16,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1610383264	1606969108	0	0
CheckNGreaterZero_A	4188	4188	0	0
GntImpliesReady_A	1610383264	403201153	0	0
GntImpliesValid_A	1610383264	403201153	0	0
GrantKnown_A	1610383264	1606969108	0	0
IdxKnown_A	1610383264	1606969108	0	0
IndexIsCorrect_A	1610383264	403201153	0	0
NoReadyValidNoGrant_A	1610383264	186299173	0	0
Priority_A	1610383264	427110282	0	0
ReadyAndValidImplyGrant_A	1610383264	403201153	0	0
ReqAndReadyImplyGrant_A	1610383264	403201153	0	0
ReqImpliesValid_A	1610383264	427110282	0	0
ValidKnown_A	1610383264	1606969108	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	1606969108	0	0
T1	10124	9768	0	0
T2	8532	8096	0	0
T3	8356	7772	0	0
T4	1696140	1695856	0	0
T10	15772	13368	0	0
T11	3342528	3342436	0	0
T16	6372	5724	0	0
T17	12820	10400	0	0
T18	9228	8916	0	0
T19	5272	5008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4188	4188	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	403201153	0	0
T1	10124	938	0	0
T2	8532	436	0	0
T3	8356	144	0	0
T4	1696140	537986	0	0
T5	0	2956	0	0
T6	0	295142	0	0
T10	15772	400	0	0
T11	3342528	1089028	0	0
T16	6372	390	0	0
T17	12820	364	0	0
T18	9228	1078	0	0
T19	5272	64	0	0
T24	0	12	0	0
T38	0	5434	0	0
T53	0	11040	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	403201153	0	0
T1	10124	938	0	0
T2	8532	436	0	0
T3	8356	144	0	0
T4	1696140	537986	0	0
T5	0	2956	0	0
T6	0	295142	0	0
T10	15772	400	0	0
T11	3342528	1089028	0	0
T16	6372	390	0	0
T17	12820	364	0	0
T18	9228	1078	0	0
T19	5272	64	0	0
T24	0	12	0	0
T38	0	5434	0	0
T53	0	11040	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	1606969108	0	0
T1	10124	9768	0	0
T2	8532	8096	0	0
T3	8356	7772	0	0
T4	1696140	1695856	0	0
T10	15772	13368	0	0
T11	3342528	3342436	0	0
T16	6372	5724	0	0
T17	12820	10400	0	0
T18	9228	8916	0	0
T19	5272	5008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	1606969108	0	0
T1	10124	9768	0	0
T2	8532	8096	0	0
T3	8356	7772	0	0
T4	1696140	1695856	0	0
T10	15772	13368	0	0
T11	3342528	3342436	0	0
T16	6372	5724	0	0
T17	12820	10400	0	0
T18	9228	8916	0	0
T19	5272	5008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	403201153	0	0
T1	10124	938	0	0
T2	8532	436	0	0
T3	8356	144	0	0
T4	1696140	537986	0	0
T5	0	2956	0	0
T6	0	295142	0	0
T10	15772	400	0	0
T11	3342528	1089028	0	0
T16	6372	390	0	0
T17	12820	364	0	0
T18	9228	1078	0	0
T19	5272	64	0	0
T24	0	12	0	0
T38	0	5434	0	0
T53	0	11040	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	186299173	0	0
T1	10124	308	0	0
T2	8532	982	0	0
T3	8356	512	0	0
T4	1696140	328206	0	0
T5	0	332	0	0
T6	0	82846	0	0
T10	15772	1596	0	0
T11	3342528	425752	0	0
T16	6372	852	0	0
T17	12820	1348	0	0
T18	9228	308	0	0
T19	5272	256	0	0
T24	0	22	0	0
T38	0	412	0	0
T53	0	692	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	427110282	0	0
T1	10124	938	0	0
T2	8532	436	0	0
T3	8356	144	0	0
T4	1696140	611790	0	0
T5	0	2956	0	0
T6	0	329250	0	0
T10	15772	400	0	0
T11	3342528	1089028	0	0
T16	6372	390	0	0
T17	12820	364	0	0
T18	9228	1078	0	0
T19	5272	64	0	0
T24	0	12	0	0
T38	0	5434	0	0
T53	0	11040	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	403201153	0	0
T1	10124	938	0	0
T2	8532	436	0	0
T3	8356	144	0	0
T4	1696140	537986	0	0
T5	0	2956	0	0
T6	0	295142	0	0
T10	15772	400	0	0
T11	3342528	1089028	0	0
T16	6372	390	0	0
T17	12820	364	0	0
T18	9228	1078	0	0
T19	5272	64	0	0
T24	0	12	0	0
T38	0	5434	0	0
T53	0	11040	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	403201153	0	0
T1	10124	938	0	0
T2	8532	436	0	0
T3	8356	144	0	0
T4	1696140	537986	0	0
T5	0	2956	0	0
T6	0	295142	0	0
T10	15772	400	0	0
T11	3342528	1089028	0	0
T16	6372	390	0	0
T17	12820	364	0	0
T18	9228	1078	0	0
T19	5272	64	0	0
T24	0	12	0	0
T38	0	5434	0	0
T53	0	11040	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	427110282	0	0
T1	10124	938	0	0
T2	8532	436	0	0
T3	8356	144	0	0
T4	1696140	611790	0	0
T5	0	2956	0	0
T6	0	329250	0	0
T10	15772	400	0	0
T11	3342528	1089028	0	0
T16	6372	390	0	0
T17	12820	364	0	0
T18	9228	1078	0	0
T19	5272	64	0	0
T24	0	12	0	0
T38	0	5434	0	0
T53	0	11040	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1610383264	1606969108	0	0
T1	10124	9768	0	0
T2	8532	8096	0	0
T3	8356	7772	0	0
T4	1696140	1695856	0	0
T10	15772	13368	0	0
T11	3342528	3342436	0	0
T16	6372	5724	0	0
T17	12820	10400	0	0
T18	9228	8916	0	0
T19	5272	5008	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T16,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402595816	401742277	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	402595816	105734842	0	0
GntImpliesValid_A	402595816	105734842	0	0
GrantKnown_A	402595816	401742277	0	0
IdxKnown_A	402595816	401742277	0	0
IndexIsCorrect_A	402595816	105734842	0	0
NoReadyValidNoGrant_A	402595816	48482995	0	0
Priority_A	402595816	111630865	0	0
ReadyAndValidImplyGrant_A	402595816	105734842	0	0
ReqAndReadyImplyGrant_A	402595816	105734842	0	0
ReqImpliesValid_A	402595816	111630865	0	0
ValidKnown_A	402595816	401742277	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	105734842	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	124029	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	105734842	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	124029	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	105734842	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	124029	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	48482995	0	0
T1	2531	128	0	0
T2	2133	471	0	0
T3	2089	256	0	0
T4	424035	82625	0	0
T10	3943	798	0	0
T11	835632	107635	0	0
T16	1593	426	0	0
T17	3205	674	0	0
T18	2307	148	0	0
T19	1318	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	111630865	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	139875	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	105734842	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	124029	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	105734842	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	124029	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	111630865	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	139875	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T16,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402595816	401742277	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	402595816	105734798	0	0
GntImpliesValid_A	402595816	105734798	0	0
GrantKnown_A	402595816	401742277	0	0
IdxKnown_A	402595816	401742277	0	0
IndexIsCorrect_A	402595816	105734798	0	0
NoReadyValidNoGrant_A	402595816	48483016	0	0
Priority_A	402595816	111630800	0	0
ReadyAndValidImplyGrant_A	402595816	105734798	0	0
ReqAndReadyImplyGrant_A	402595816	105734798	0	0
ReqImpliesValid_A	402595816	111630800	0	0
ValidKnown_A	402595816	401742277	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	105734798	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	124029	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	105734798	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	124029	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	105734798	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	124029	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	48483016	0	0
T1	2531	128	0	0
T2	2133	471	0	0
T3	2089	256	0	0
T4	424035	82625	0	0
T10	3943	798	0	0
T11	835632	107635	0	0
T16	1593	426	0	0
T17	3205	674	0	0
T18	2307	148	0	0
T19	1318	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	111630800	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	139875	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	105734798	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	124029	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	105734798	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	124029	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	111630800	0	0
T1	2531	139	0	0
T2	2133	213	0	0
T3	2089	72	0	0
T4	424035	139875	0	0
T10	3943	200	0	0
T11	835632	274901	0	0
T16	1593	195	0	0
T17	3205	182	0	0
T18	2307	275	0	0
T19	1318	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T18,T4
1	0	Covered	T2,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T18,T4
1	1	Covered	T2,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T18,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402595816	401742277	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	402595816	95865866	0	0
GntImpliesValid_A	402595816	95865866	0	0
GrantKnown_A	402595816	401742277	0	0
IdxKnown_A	402595816	401742277	0	0
IndexIsCorrect_A	402595816	95865866	0	0
NoReadyValidNoGrant_A	402595816	44666580	0	0
Priority_A	402595816	101924419	0	0
ReadyAndValidImplyGrant_A	402595816	95865866	0	0
ReqAndReadyImplyGrant_A	402595816	95865866	0	0
ReqImpliesValid_A	402595816	101924419	0	0
ValidKnown_A	402595816	401742277	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	95865866	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	144964	0	0
T5	0	1478	0	0
T6	0	147571	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	95865866	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	144964	0	0
T5	0	1478	0	0
T6	0	147571	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	95865866	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	144964	0	0
T5	0	1478	0	0
T6	0	147571	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	44666580	0	0
T1	2531	26	0	0
T2	2133	20	0	0
T3	2089	0	0	0
T4	424035	81478	0	0
T5	0	166	0	0
T6	0	41423	0	0
T10	3943	0	0	0
T11	835632	105241	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	6	0	0
T19	1318	0	0	0
T24	0	11	0	0
T38	0	206	0	0
T53	0	346	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	101924419	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	166020	0	0
T5	0	1478	0	0
T6	0	164625	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	95865866	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	144964	0	0
T5	0	1478	0	0
T6	0	147571	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	95865866	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	144964	0	0
T5	0	1478	0	0
T6	0	147571	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	101924419	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	166020	0	0
T5	0	1478	0	0
T6	0	164625	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T18,T4
1	0	Covered	T2,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T18,T4
1	1	Covered	T2,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T18,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402595816	401742277	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	402595816	95865647	0	0
GntImpliesValid_A	402595816	95865647	0	0
GrantKnown_A	402595816	401742277	0	0
IdxKnown_A	402595816	401742277	0	0
IndexIsCorrect_A	402595816	95865647	0	0
NoReadyValidNoGrant_A	402595816	44666582	0	0
Priority_A	402595816	101924198	0	0
ReadyAndValidImplyGrant_A	402595816	95865647	0	0
ReqAndReadyImplyGrant_A	402595816	95865647	0	0
ReqImpliesValid_A	402595816	101924198	0	0
ValidKnown_A	402595816	401742277	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	95865647	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	144964	0	0
T5	0	1478	0	0
T6	0	147571	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	95865647	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	144964	0	0
T5	0	1478	0	0
T6	0	147571	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	95865647	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	144964	0	0
T5	0	1478	0	0
T6	0	147571	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	44666582	0	0
T1	2531	26	0	0
T2	2133	20	0	0
T3	2089	0	0	0
T4	424035	81478	0	0
T5	0	166	0	0
T6	0	41423	0	0
T10	3943	0	0	0
T11	835632	105241	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	6	0	0
T19	1318	0	0	0
T24	0	11	0	0
T38	0	206	0	0
T53	0	346	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	101924198	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	166020	0	0
T5	0	1478	0	0
T6	0	164625	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	95865647	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	144964	0	0
T5	0	1478	0	0
T6	0	147571	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	95865647	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	144964	0	0
T5	0	1478	0	0
T6	0	147571	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	101924198	0	0
T1	2531	330	0	0
T2	2133	5	0	0
T3	2089	0	0	0
T4	424035	166020	0	0
T5	0	1478	0	0
T6	0	164625	0	0
T10	3943	0	0	0
T11	835632	269613	0	0
T16	1593	0	0	0
T17	3205	0	0	0
T18	2307	264	0	0
T19	1318	0	0	0
T24	0	6	0	0
T38	0	2717	0	0
T53	0	5520	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0