Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_to_prog_fifo.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.96	100.00	65.52			85.71	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	90.30	100.00	80.00			90.91

Module Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.47	85.71	38.46			85.71	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.63	94.44	54.84			81.25	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.96	100.00	65.52			85.71	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.48	100.00	66.67			77.78

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	405242445	5618457	0	0
DepthKnown_A	405242445	404298865	0	0
RvalidKnown_A	405242445	404298865	0	0
WreadyKnown_A	405242445	404298865	0	0
gen_passthru_fifo.paramCheckPass	1262	1262	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	5618457	0	0
T1	2531	53	0	0
T2	2133	80	0	0
T3	2089	0	0	0
T4	424035	8160	0	0
T5	0	34	0	0
T10	3943	0	0	0
T11	835632	10240	0	0
T12	0	12	0	0
T16	1593	60	0	0
T17	3205	0	0	0
T18	2307	17	0	0
T19	1318	0	0	0
T28	0	4608	0	0
T38	0	192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	404298865	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	404298865	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	404298865	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1262	1262	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	405242445	27174439	0	0
DepthKnown_A	405242445	404298865	0	0
RvalidKnown_A	405242445	404298865	0	0
WreadyKnown_A	405242445	404298865	0	0
gen_passthru_fifo.paramCheckPass	1262	1262	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	27174439	0	0
T1	2531	112	0	0
T2	2133	392	0	0
T3	2089	109	0	0
T4	424035	186393	0	0
T10	3943	110	0	0
T11	835632	159573	0	0
T16	1593	393	0	0
T17	3205	505	0	0
T18	2307	414	0	0
T19	1318	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	404298865	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	404298865	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	404298865	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1262	1262	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	405242445	36431783	0	0
DepthKnown_A	405242445	404298865	0	0
RvalidKnown_A	405242445	404298865	0	0
WreadyKnown_A	405242445	404298865	0	0
gen_passthru_fifo.paramCheckPass	1262	1262	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	36431783	0	0
T1	2531	384	0	0
T2	2133	392	0	0
T3	2089	109	0	0
T4	424035	186393	0	0
T10	3943	503	0	0
T11	835632	159573	0	0
T16	1593	393	0	0
T17	3205	505	0	0
T18	2307	414	0	0
T19	1318	58	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	404298865	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	404298865	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405242445	404298865	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1262	1262	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402595816	3968004	0	0
DepthKnown_A	402595816	401742277	0	0
RvalidKnown_A	402595816	401742277	0	0
WreadyKnown_A	402595816	401742277	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	402595816	3968004	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	3968004	0	0
T1	2531	40	0	0
T2	2133	2	0	0
T3	2089	2	0	0
T4	424035	9586	0	0
T10	3943	0	0	0
T11	835632	5120	0	0
T12	0	8	0	0
T16	1593	2	0	0
T17	3205	0	0	0
T18	2307	7	0	0
T19	1318	0	0	0
T28	0	5120	0	0
T38	0	159	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	3968004	0	0
T1	2531	40	0	0
T2	2133	2	0	0
T3	2089	2	0	0
T4	424035	9586	0	0
T10	3943	0	0	0
T11	835632	5120	0	0
T12	0	8	0	0
T16	1593	2	0	0
T17	3205	0	0	0
T18	2307	7	0	0
T19	1318	0	0	0
T28	0	5120	0	0
T38	0	159	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	0	0
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101		unreachable
108	0	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Total	Covered	Percent
Conditions	13	5	38.46
Logical	13	5	38.46
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Not Covered
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	6	85.71
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402595816	0	0	0
DepthKnown_A	402595816	401742277	0	0
RvalidKnown_A	402595816	401742277	0	0
WreadyKnown_A	402595816	401742277	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	402595816	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	401742277	0	0
T1	2531	2442	0	0
T2	2133	2024	0	0
T3	2089	1943	0	0
T4	424035	423964	0	0
T10	3943	3342	0	0
T11	835632	835609	0	0
T16	1593	1431	0	0
T17	3205	2600	0	0
T18	2307	2229	0	0
T19	1318	1252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	402595816	0	0	0