Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 13 | 12 | 92.31 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
|
unreachable |
101 |
1 |
1 |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
|
unreachable |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
| Total | Covered | Percent |
Conditions | 17 | 8 | 47.06 |
Logical | 17 | 8 | 47.06 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Unreachable | |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
6 |
85.71 |
TERNARY |
130 |
1 |
1 |
100.00 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Unreachable |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Unreachable |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prog_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prog_fifo
| Total | Covered | Percent |
Conditions | 24 | 20 | 83.33 |
Logical | 24 | 20 | 83.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T11,T38 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T18 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (39'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_prog_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prog_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
166908958 |
0 |
0 |
T1 |
2531 |
421 |
0 |
0 |
T2 |
2133 |
66 |
0 |
0 |
T3 |
2089 |
8 |
0 |
0 |
T4 |
424035 |
323523 |
0 |
0 |
T10 |
3943 |
0 |
0 |
0 |
T11 |
835632 |
437600 |
0 |
0 |
T12 |
0 |
240 |
0 |
0 |
T16 |
1593 |
66 |
0 |
0 |
T17 |
3205 |
0 |
0 |
0 |
T18 |
2307 |
230 |
0 |
0 |
T19 |
1318 |
0 |
0 |
0 |
T28 |
0 |
5440 |
0 |
0 |
T38 |
0 |
4975 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
166908958 |
0 |
0 |
T1 |
2531 |
421 |
0 |
0 |
T2 |
2133 |
66 |
0 |
0 |
T3 |
2089 |
8 |
0 |
0 |
T4 |
424035 |
323523 |
0 |
0 |
T10 |
3943 |
0 |
0 |
0 |
T11 |
835632 |
437600 |
0 |
0 |
T12 |
0 |
240 |
0 |
0 |
T16 |
1593 |
66 |
0 |
0 |
T17 |
3205 |
0 |
0 |
0 |
T18 |
2307 |
230 |
0 |
0 |
T19 |
1318 |
0 |
0 |
0 |
T28 |
0 |
5440 |
0 |
0 |
T38 |
0 |
4975 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T16 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T28 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T16 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T16 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T16 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
5614914 |
0 |
0 |
T1 |
2531 |
53 |
0 |
0 |
T2 |
2133 |
80 |
0 |
0 |
T3 |
2089 |
0 |
0 |
0 |
T4 |
424035 |
8160 |
0 |
0 |
T5 |
0 |
34 |
0 |
0 |
T10 |
3943 |
0 |
0 |
0 |
T11 |
835632 |
10240 |
0 |
0 |
T12 |
0 |
12 |
0 |
0 |
T16 |
1593 |
60 |
0 |
0 |
T17 |
3205 |
0 |
0 |
0 |
T18 |
2307 |
17 |
0 |
0 |
T19 |
1318 |
0 |
0 |
0 |
T28 |
0 |
4608 |
0 |
0 |
T38 |
0 |
192 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
5614914 |
0 |
0 |
T1 |
2531 |
53 |
0 |
0 |
T2 |
2133 |
80 |
0 |
0 |
T3 |
2089 |
0 |
0 |
0 |
T4 |
424035 |
8160 |
0 |
0 |
T5 |
0 |
34 |
0 |
0 |
T10 |
3943 |
0 |
0 |
0 |
T11 |
835632 |
10240 |
0 |
0 |
T12 |
0 |
12 |
0 |
0 |
T16 |
1593 |
60 |
0 |
0 |
T17 |
3205 |
0 |
0 |
0 |
T18 |
2307 |
17 |
0 |
0 |
T19 |
1318 |
0 |
0 |
0 |
T28 |
0 |
4608 |
0 |
0 |
T38 |
0 |
192 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 10 | 62.50 |
Logical | 16 | 10 | 62.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T16 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T16 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T16 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T16 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
3468133 |
0 |
0 |
T1 |
2531 |
16 |
0 |
0 |
T2 |
2133 |
80 |
0 |
0 |
T3 |
2089 |
0 |
0 |
0 |
T4 |
424035 |
8160 |
0 |
0 |
T5 |
0 |
34 |
0 |
0 |
T10 |
3943 |
0 |
0 |
0 |
T11 |
835632 |
10240 |
0 |
0 |
T12 |
0 |
12 |
0 |
0 |
T16 |
1593 |
60 |
0 |
0 |
T17 |
3205 |
0 |
0 |
0 |
T18 |
2307 |
17 |
0 |
0 |
T19 |
1318 |
0 |
0 |
0 |
T28 |
0 |
4608 |
0 |
0 |
T38 |
0 |
192 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
3468133 |
0 |
0 |
T1 |
2531 |
16 |
0 |
0 |
T2 |
2133 |
80 |
0 |
0 |
T3 |
2089 |
0 |
0 |
0 |
T4 |
424035 |
8160 |
0 |
0 |
T5 |
0 |
34 |
0 |
0 |
T10 |
3943 |
0 |
0 |
0 |
T11 |
835632 |
10240 |
0 |
0 |
T12 |
0 |
12 |
0 |
0 |
T16 |
1593 |
60 |
0 |
0 |
T17 |
3205 |
0 |
0 |
0 |
T18 |
2307 |
17 |
0 |
0 |
T19 |
1318 |
0 |
0 |
0 |
T28 |
0 |
4608 |
0 |
0 |
T38 |
0 |
192 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
| Total | Covered | Percent |
Conditions | 24 | 20 | 83.33 |
Logical | 24 | 20 | 83.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T13,T42 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T16 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T14,T15,T39 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T28 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T16 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T39 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T16 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T13,T42 |
1 | 0 | Covered | T1,T2,T16 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T16 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T16 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T16 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402362923 |
5601355 |
0 |
0 |
T1 |
2531 |
53 |
0 |
0 |
T2 |
2133 |
80 |
0 |
0 |
T3 |
2089 |
0 |
0 |
0 |
T4 |
424035 |
8160 |
0 |
0 |
T5 |
0 |
34 |
0 |
0 |
T10 |
3943 |
0 |
0 |
0 |
T11 |
835632 |
10240 |
0 |
0 |
T12 |
0 |
12 |
0 |
0 |
T16 |
1593 |
60 |
0 |
0 |
T17 |
3205 |
0 |
0 |
0 |
T18 |
2307 |
17 |
0 |
0 |
T19 |
1318 |
0 |
0 |
0 |
T28 |
0 |
4608 |
0 |
0 |
T38 |
0 |
192 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
401742277 |
0 |
0 |
T1 |
2531 |
2442 |
0 |
0 |
T2 |
2133 |
2024 |
0 |
0 |
T3 |
2089 |
1943 |
0 |
0 |
T4 |
424035 |
423964 |
0 |
0 |
T10 |
3943 |
3342 |
0 |
0 |
T11 |
835632 |
835609 |
0 |
0 |
T16 |
1593 |
1431 |
0 |
0 |
T17 |
3205 |
2600 |
0 |
0 |
T18 |
2307 |
2229 |
0 |
0 |
T19 |
1318 |
1252 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
402595816 |
5623732 |
0 |
0 |
T1 |
2531 |
53 |
0 |
0 |
T2 |
2133 |
80 |
0 |
0 |
T3 |
2089 |
0 |
0 |
0 |
T4 |
424035 |
8160 |
0 |
0 |
T5 |
0 |
34 |
0 |
0 |
T10 |
3943 |
0 |
0 |
0 |
T11 |
835632 |
10240 |
0 |
0 |
T12 |
0 |
12 |
0 |
0 |
T16 |
1593 |
60 |
0 |
0 |
T17 |
3205 |
0 |
0 |
0 |
T18 |
2307 |
17 |
0 |
0 |
T19 |
1318 |
0 |
0 |
0 |
T28 |
0 |
4608 |
0 |
0 |
T38 |
0 |
192 |
0 |
0 |