| T1074 |
/workspace/coverage/default/29.flash_ctrl_intr_rd.3204171840 |
|
|
Jul 16 05:35:21 PM PDT 24 |
Jul 16 05:39:17 PM PDT 24 |
4849281500 ps |
| T1075 |
/workspace/coverage/default/13.flash_ctrl_connect.1072565678 |
|
|
Jul 16 05:33:20 PM PDT 24 |
Jul 16 05:33:36 PM PDT 24 |
52610500 ps |
| T1076 |
/workspace/coverage/default/33.flash_ctrl_sec_info_access.755676019 |
|
|
Jul 16 05:36:48 PM PDT 24 |
Jul 16 05:37:56 PM PDT 24 |
1353951600 ps |
| T1077 |
/workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3481715090 |
|
|
Jul 16 05:33:29 PM PDT 24 |
Jul 16 05:38:33 PM PDT 24 |
13300707500 ps |
| T1078 |
/workspace/coverage/default/16.flash_ctrl_re_evict.3530050721 |
|
|
Jul 16 05:37:18 PM PDT 24 |
Jul 16 05:37:53 PM PDT 24 |
127152800 ps |
| T1079 |
/workspace/coverage/default/3.flash_ctrl_config_regwen.3690113260 |
|
|
Jul 16 05:31:40 PM PDT 24 |
Jul 16 05:31:55 PM PDT 24 |
22454600 ps |
| T1080 |
/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1432244822 |
|
|
Jul 16 05:30:18 PM PDT 24 |
Jul 16 05:30:33 PM PDT 24 |
95759000 ps |
| T1081 |
/workspace/coverage/default/4.flash_ctrl_error_prog_win.707203178 |
|
|
Jul 16 05:30:54 PM PDT 24 |
Jul 16 05:46:17 PM PDT 24 |
1643583400 ps |
| T1082 |
/workspace/coverage/default/16.flash_ctrl_hw_rma_reset.4136375584 |
|
|
Jul 16 05:37:21 PM PDT 24 |
Jul 16 05:51:24 PM PDT 24 |
40117227900 ps |
| T1083 |
/workspace/coverage/default/16.flash_ctrl_rand_ops.756509589 |
|
|
Jul 16 05:33:30 PM PDT 24 |
Jul 16 05:42:51 PM PDT 24 |
66461000 ps |
| T1084 |
/workspace/coverage/default/10.flash_ctrl_invalid_op.3493184637 |
|
|
Jul 16 05:32:34 PM PDT 24 |
Jul 16 05:33:39 PM PDT 24 |
3353940600 ps |
| T1085 |
/workspace/coverage/default/4.flash_ctrl_host_dir_rd.118988107 |
|
|
Jul 16 05:30:57 PM PDT 24 |
Jul 16 05:31:34 PM PDT 24 |
114900700 ps |
| T1086 |
/workspace/coverage/default/24.flash_ctrl_sec_info_access.3007450180 |
|
|
Jul 16 05:35:03 PM PDT 24 |
Jul 16 05:36:12 PM PDT 24 |
1463283300 ps |
| T1087 |
/workspace/coverage/default/7.flash_ctrl_error_prog_win.1383233111 |
|
|
Jul 16 05:36:39 PM PDT 24 |
Jul 16 05:51:03 PM PDT 24 |
432041900 ps |
| T1088 |
/workspace/coverage/default/8.flash_ctrl_rand_ops.3974090314 |
|
|
Jul 16 05:36:33 PM PDT 24 |
Jul 16 05:39:49 PM PDT 24 |
71857900 ps |
| T1089 |
/workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.1231545065 |
|
|
Jul 16 05:30:13 PM PDT 24 |
Jul 16 05:32:47 PM PDT 24 |
48197337200 ps |
| T1090 |
/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3684991050 |
|
|
Jul 16 05:34:31 PM PDT 24 |
Jul 16 05:35:46 PM PDT 24 |
10019568900 ps |
| T1091 |
/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.1815418502 |
|
|
Jul 16 05:36:23 PM PDT 24 |
Jul 16 05:36:55 PM PDT 24 |
43586300 ps |
| T1092 |
/workspace/coverage/default/24.flash_ctrl_rw_evict.1081902215 |
|
|
Jul 16 05:34:50 PM PDT 24 |
Jul 16 05:35:23 PM PDT 24 |
149690100 ps |
| T1093 |
/workspace/coverage/default/64.flash_ctrl_otp_reset.579754097 |
|
|
Jul 16 05:37:16 PM PDT 24 |
Jul 16 05:39:33 PM PDT 24 |
58541400 ps |
| T1094 |
/workspace/coverage/default/0.flash_ctrl_phy_arb.1585421616 |
|
|
Jul 16 05:29:22 PM PDT 24 |
Jul 16 05:36:22 PM PDT 24 |
918337300 ps |
| T1095 |
/workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2217106042 |
|
|
Jul 16 05:37:00 PM PDT 24 |
Jul 16 05:37:33 PM PDT 24 |
33024500 ps |
| T1096 |
/workspace/coverage/default/20.flash_ctrl_disable.3100033099 |
|
|
Jul 16 05:34:27 PM PDT 24 |
Jul 16 05:34:48 PM PDT 24 |
11756200 ps |
| T1097 |
/workspace/coverage/default/14.flash_ctrl_ro.851238317 |
|
|
Jul 16 05:33:20 PM PDT 24 |
Jul 16 05:35:16 PM PDT 24 |
567488200 ps |
| T1098 |
/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.4279778127 |
|
|
Jul 16 05:36:12 PM PDT 24 |
Jul 16 05:38:23 PM PDT 24 |
4518146200 ps |
| T1099 |
/workspace/coverage/default/1.flash_ctrl_hw_sec_otp.827327180 |
|
|
Jul 16 05:29:49 PM PDT 24 |
Jul 16 05:31:57 PM PDT 24 |
9069101500 ps |
| T1100 |
/workspace/coverage/default/47.flash_ctrl_otp_reset.99208731 |
|
|
Jul 16 05:36:56 PM PDT 24 |
Jul 16 05:39:07 PM PDT 24 |
269825800 ps |
| T1101 |
/workspace/coverage/default/31.flash_ctrl_intr_rd.3892911691 |
|
|
Jul 16 05:36:50 PM PDT 24 |
Jul 16 05:39:10 PM PDT 24 |
1501261500 ps |
| T1102 |
/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3745741179 |
|
|
Jul 16 05:32:19 PM PDT 24 |
Jul 16 05:32:33 PM PDT 24 |
26357600 ps |
| T1103 |
/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2790812405 |
|
|
Jul 16 05:33:43 PM PDT 24 |
Jul 16 05:48:00 PM PDT 24 |
60128226300 ps |
| T1104 |
/workspace/coverage/default/15.flash_ctrl_phy_arb.190816199 |
|
|
Jul 16 05:36:46 PM PDT 24 |
Jul 16 05:39:34 PM PDT 24 |
863995300 ps |
| T1105 |
/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1755443194 |
|
|
Jul 16 05:30:42 PM PDT 24 |
Jul 16 05:35:41 PM PDT 24 |
44185426800 ps |
| T1106 |
/workspace/coverage/default/2.flash_ctrl_config_regwen.2933043187 |
|
|
Jul 16 05:30:13 PM PDT 24 |
Jul 16 05:30:28 PM PDT 24 |
41040600 ps |
| T23 |
/workspace/coverage/default/2.flash_ctrl_access_after_disable.4281533411 |
|
|
Jul 16 05:30:13 PM PDT 24 |
Jul 16 05:30:28 PM PDT 24 |
23933000 ps |
| T1107 |
/workspace/coverage/default/10.flash_ctrl_prog_reset.185765198 |
|
|
Jul 16 05:36:56 PM PDT 24 |
Jul 16 05:40:24 PM PDT 24 |
4855601700 ps |
| T1108 |
/workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.751545498 |
|
|
Jul 16 05:35:52 PM PDT 24 |
Jul 16 06:10:06 PM PDT 24 |
344857620500 ps |
| T1109 |
/workspace/coverage/default/8.flash_ctrl_lcmgr_intg.4158473101 |
|
|
Jul 16 05:36:53 PM PDT 24 |
Jul 16 05:37:07 PM PDT 24 |
19795800 ps |
| T1110 |
/workspace/coverage/default/6.flash_ctrl_alert_test.1329445437 |
|
|
Jul 16 05:31:57 PM PDT 24 |
Jul 16 05:32:11 PM PDT 24 |
95323100 ps |
| T1111 |
/workspace/coverage/default/3.flash_ctrl_smoke_hw.3789073557 |
|
|
Jul 16 05:30:17 PM PDT 24 |
Jul 16 05:30:42 PM PDT 24 |
16203600 ps |
| T409 |
/workspace/coverage/default/18.flash_ctrl_sec_info_access.2333839336 |
|
|
Jul 16 05:34:08 PM PDT 24 |
Jul 16 05:35:17 PM PDT 24 |
5738525000 ps |
| T1112 |
/workspace/coverage/default/16.flash_ctrl_mp_regions.2364509702 |
|
|
Jul 16 05:33:27 PM PDT 24 |
Jul 16 05:37:25 PM PDT 24 |
7561914300 ps |
| T198 |
/workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.1733354517 |
|
|
Jul 16 05:30:30 PM PDT 24 |
Jul 16 06:12:03 PM PDT 24 |
230824494000 ps |
| T1113 |
/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.4202841044 |
|
|
Jul 16 05:34:24 PM PDT 24 |
Jul 16 05:36:05 PM PDT 24 |
184314100 ps |
| T1114 |
/workspace/coverage/default/9.flash_ctrl_smoke.2466923184 |
|
|
Jul 16 05:36:15 PM PDT 24 |
Jul 16 05:39:03 PM PDT 24 |
103331600 ps |
| T1115 |
/workspace/coverage/default/6.flash_ctrl_ro.3750708335 |
|
|
Jul 16 05:31:49 PM PDT 24 |
Jul 16 05:34:10 PM PDT 24 |
579635500 ps |
| T1116 |
/workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.601831311 |
|
|
Jul 16 05:35:54 PM PDT 24 |
Jul 16 05:40:06 PM PDT 24 |
12093369100 ps |
| T1117 |
/workspace/coverage/default/9.flash_ctrl_hw_rma_reset.356641958 |
|
|
Jul 16 05:36:54 PM PDT 24 |
Jul 16 05:52:04 PM PDT 24 |
160194708800 ps |
| T57 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1024630210 |
|
|
Jul 16 05:10:37 PM PDT 24 |
Jul 16 05:11:13 PM PDT 24 |
171335800 ps |
| T58 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3467896955 |
|
|
Jul 16 05:10:45 PM PDT 24 |
Jul 16 05:11:03 PM PDT 24 |
157520900 ps |
| T59 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3009720265 |
|
|
Jul 16 05:10:41 PM PDT 24 |
Jul 16 05:25:53 PM PDT 24 |
3226036300 ps |
| T258 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2252338072 |
|
|
Jul 16 05:11:05 PM PDT 24 |
Jul 16 05:11:19 PM PDT 24 |
22758900 ps |
| T100 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.547310776 |
|
|
Jul 16 05:10:21 PM PDT 24 |
Jul 16 05:11:24 PM PDT 24 |
2907194000 ps |
| T102 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3880825883 |
|
|
Jul 16 05:10:40 PM PDT 24 |
Jul 16 05:10:57 PM PDT 24 |
40416500 ps |
| T1118 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3945951898 |
|
|
Jul 16 05:10:55 PM PDT 24 |
Jul 16 05:11:13 PM PDT 24 |
32131300 ps |
| T251 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2423056786 |
|
|
Jul 16 05:10:41 PM PDT 24 |
Jul 16 05:10:59 PM PDT 24 |
166829100 ps |
| T210 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.439504422 |
|
|
Jul 16 05:10:51 PM PDT 24 |
Jul 16 05:11:08 PM PDT 24 |
257777000 ps |
| T252 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.193328460 |
|
|
Jul 16 05:10:21 PM PDT 24 |
Jul 16 05:11:43 PM PDT 24 |
8421333100 ps |
| T324 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.338116627 |
|
|
Jul 16 05:11:02 PM PDT 24 |
Jul 16 05:11:20 PM PDT 24 |
33986600 ps |
| T259 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1329712191 |
|
|
Jul 16 05:10:39 PM PDT 24 |
Jul 16 05:10:54 PM PDT 24 |
15324200 ps |
| T297 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2981927685 |
|
|
Jul 16 05:10:57 PM PDT 24 |
Jul 16 05:11:12 PM PDT 24 |
148746500 ps |
| T260 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1280421642 |
|
|
Jul 16 05:10:27 PM PDT 24 |
Jul 16 05:10:42 PM PDT 24 |
15874900 ps |
| T1119 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1844269995 |
|
|
Jul 16 05:10:50 PM PDT 24 |
Jul 16 05:11:06 PM PDT 24 |
13271500 ps |
| T325 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.439375589 |
|
|
Jul 16 05:10:38 PM PDT 24 |
Jul 16 05:10:52 PM PDT 24 |
80683700 ps |
| T326 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.281356225 |
|
|
Jul 16 05:10:52 PM PDT 24 |
Jul 16 05:11:06 PM PDT 24 |
27261100 ps |
| T263 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2270924537 |
|
|
Jul 16 05:10:38 PM PDT 24 |
Jul 16 05:11:18 PM PDT 24 |
250619600 ps |
| T101 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1689109258 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:25:22 PM PDT 24 |
2569880300 ps |
| T208 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.383830715 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:10:48 PM PDT 24 |
430475100 ps |
| T327 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.757122181 |
|
|
Jul 16 05:10:52 PM PDT 24 |
Jul 16 05:11:07 PM PDT 24 |
50030000 ps |
| T209 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2561434320 |
|
|
Jul 16 05:10:42 PM PDT 24 |
Jul 16 05:18:23 PM PDT 24 |
674306400 ps |
| T228 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3528428033 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:25:37 PM PDT 24 |
722262200 ps |
| T294 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.448596190 |
|
|
Jul 16 05:10:37 PM PDT 24 |
Jul 16 05:10:53 PM PDT 24 |
68394900 ps |
| T1120 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4276270255 |
|
|
Jul 16 05:10:24 PM PDT 24 |
Jul 16 05:10:40 PM PDT 24 |
46674200 ps |
| T220 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2407352784 |
|
|
Jul 16 05:10:51 PM PDT 24 |
Jul 16 05:11:08 PM PDT 24 |
31227400 ps |
| T328 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1659932789 |
|
|
Jul 16 05:10:52 PM PDT 24 |
Jul 16 05:11:07 PM PDT 24 |
57159400 ps |
| T1121 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3564233698 |
|
|
Jul 16 05:10:53 PM PDT 24 |
Jul 16 05:11:10 PM PDT 24 |
102417900 ps |
| T221 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2218428276 |
|
|
Jul 16 05:10:49 PM PDT 24 |
Jul 16 05:25:44 PM PDT 24 |
674972300 ps |
| T222 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1021797622 |
|
|
Jul 16 05:10:51 PM PDT 24 |
Jul 16 05:23:28 PM PDT 24 |
700710900 ps |
| T229 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2383136822 |
|
|
Jul 16 05:10:48 PM PDT 24 |
Jul 16 05:25:43 PM PDT 24 |
1799183700 ps |
| T339 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1573074887 |
|
|
Jul 16 05:10:40 PM PDT 24 |
Jul 16 05:10:54 PM PDT 24 |
44361000 ps |
| T223 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3886270966 |
|
|
Jul 16 05:10:51 PM PDT 24 |
Jul 16 05:11:10 PM PDT 24 |
78386200 ps |
| T230 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.4246205426 |
|
|
Jul 16 05:10:50 PM PDT 24 |
Jul 16 05:18:38 PM PDT 24 |
474636300 ps |
| T1122 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3961038412 |
|
|
Jul 16 05:11:02 PM PDT 24 |
Jul 16 05:11:21 PM PDT 24 |
159609200 ps |
| T1123 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3753968723 |
|
|
Jul 16 05:10:53 PM PDT 24 |
Jul 16 05:11:10 PM PDT 24 |
44440500 ps |
| T295 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.804822539 |
|
|
Jul 16 05:10:25 PM PDT 24 |
Jul 16 05:11:02 PM PDT 24 |
1807733300 ps |
| T1124 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3235031743 |
|
|
Jul 16 05:10:35 PM PDT 24 |
Jul 16 05:10:52 PM PDT 24 |
22693500 ps |
| T329 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2301192255 |
|
|
Jul 16 05:11:02 PM PDT 24 |
Jul 16 05:11:17 PM PDT 24 |
17710500 ps |
| T224 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.550578745 |
|
|
Jul 16 05:11:00 PM PDT 24 |
Jul 16 05:11:19 PM PDT 24 |
78672700 ps |
| T262 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1751660493 |
|
|
Jul 16 05:10:48 PM PDT 24 |
Jul 16 05:17:16 PM PDT 24 |
921826000 ps |
| T1125 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3769654813 |
|
|
Jul 16 05:10:53 PM PDT 24 |
Jul 16 05:11:08 PM PDT 24 |
15921900 ps |
| T1126 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3725210722 |
|
|
Jul 16 05:10:27 PM PDT 24 |
Jul 16 05:10:43 PM PDT 24 |
17321000 ps |
| T225 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1383876672 |
|
|
Jul 16 05:11:04 PM PDT 24 |
Jul 16 05:17:31 PM PDT 24 |
6565900800 ps |
| T1127 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.879874319 |
|
|
Jul 16 05:10:55 PM PDT 24 |
Jul 16 05:11:10 PM PDT 24 |
17184300 ps |
| T226 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4262121124 |
|
|
Jul 16 05:10:57 PM PDT 24 |
Jul 16 05:11:19 PM PDT 24 |
179322300 ps |
| T1128 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2550488569 |
|
|
Jul 16 05:10:55 PM PDT 24 |
Jul 16 05:11:16 PM PDT 24 |
16503100 ps |
| T1129 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.179621349 |
|
|
Jul 16 05:10:41 PM PDT 24 |
Jul 16 05:10:57 PM PDT 24 |
17304300 ps |
| T227 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2878559058 |
|
|
Jul 16 05:11:10 PM PDT 24 |
Jul 16 05:11:25 PM PDT 24 |
57165200 ps |
| T253 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3790289115 |
|
|
Jul 16 05:10:41 PM PDT 24 |
Jul 16 05:11:03 PM PDT 24 |
104620600 ps |
| T1130 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.123056451 |
|
|
Jul 16 05:10:23 PM PDT 24 |
Jul 16 05:11:04 PM PDT 24 |
1180319600 ps |
| T1131 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.701727287 |
|
|
Jul 16 05:11:07 PM PDT 24 |
Jul 16 05:11:21 PM PDT 24 |
57757700 ps |
| T298 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2765042815 |
|
|
Jul 16 05:11:01 PM PDT 24 |
Jul 16 05:11:20 PM PDT 24 |
211815700 ps |
| T255 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1453989622 |
|
|
Jul 16 05:10:46 PM PDT 24 |
Jul 16 05:11:05 PM PDT 24 |
313118700 ps |
| T296 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3292769123 |
|
|
Jul 16 05:11:05 PM PDT 24 |
Jul 16 05:11:24 PM PDT 24 |
205871200 ps |
| T1132 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3963474229 |
|
|
Jul 16 05:10:49 PM PDT 24 |
Jul 16 05:11:03 PM PDT 24 |
85185900 ps |
| T1133 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2109583123 |
|
|
Jul 16 05:10:42 PM PDT 24 |
Jul 16 05:10:57 PM PDT 24 |
49270000 ps |
| T1134 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.636551586 |
|
|
Jul 16 05:10:39 PM PDT 24 |
Jul 16 05:10:58 PM PDT 24 |
36608100 ps |
| T323 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3821206939 |
|
|
Jul 16 05:10:40 PM PDT 24 |
Jul 16 05:10:56 PM PDT 24 |
51269700 ps |
| T1135 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.417518565 |
|
|
Jul 16 05:11:03 PM PDT 24 |
Jul 16 05:11:17 PM PDT 24 |
58672900 ps |
| T299 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3202176881 |
|
|
Jul 16 05:10:38 PM PDT 24 |
Jul 16 05:10:56 PM PDT 24 |
62024300 ps |
| T300 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2742425533 |
|
|
Jul 16 05:10:40 PM PDT 24 |
Jul 16 05:10:57 PM PDT 24 |
62077300 ps |
| T372 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2048586728 |
|
|
Jul 16 05:10:38 PM PDT 24 |
Jul 16 05:23:13 PM PDT 24 |
2795972000 ps |
| T1136 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.793566281 |
|
|
Jul 16 05:10:43 PM PDT 24 |
Jul 16 05:10:59 PM PDT 24 |
107266400 ps |
| T1137 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1737813553 |
|
|
Jul 16 05:11:00 PM PDT 24 |
Jul 16 05:11:17 PM PDT 24 |
23436000 ps |
| T264 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.502625722 |
|
|
Jul 16 05:10:27 PM PDT 24 |
Jul 16 05:10:47 PM PDT 24 |
59528500 ps |
| T1138 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.4090270848 |
|
|
Jul 16 05:10:40 PM PDT 24 |
Jul 16 05:10:54 PM PDT 24 |
43280100 ps |
| T1139 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2658279125 |
|
|
Jul 16 05:10:56 PM PDT 24 |
Jul 16 05:11:12 PM PDT 24 |
15072000 ps |
| T1140 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.133322511 |
|
|
Jul 16 05:10:57 PM PDT 24 |
Jul 16 05:11:12 PM PDT 24 |
16509500 ps |
| T1141 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1444444162 |
|
|
Jul 16 05:10:55 PM PDT 24 |
Jul 16 05:11:33 PM PDT 24 |
653804800 ps |
| T1142 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.994528433 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:11:22 PM PDT 24 |
1718270400 ps |
| T1143 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3061939474 |
|
|
Jul 16 05:10:35 PM PDT 24 |
Jul 16 05:11:24 PM PDT 24 |
6071450900 ps |
| T254 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3152141117 |
|
|
Jul 16 05:10:37 PM PDT 24 |
Jul 16 05:10:54 PM PDT 24 |
118538200 ps |
| T1144 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1090910497 |
|
|
Jul 16 05:10:52 PM PDT 24 |
Jul 16 05:11:07 PM PDT 24 |
23996000 ps |
| T301 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3048914900 |
|
|
Jul 16 05:10:52 PM PDT 24 |
Jul 16 05:11:36 PM PDT 24 |
5442124000 ps |
| T1145 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3090955928 |
|
|
Jul 16 05:11:05 PM PDT 24 |
Jul 16 05:11:52 PM PDT 24 |
4770422400 ps |
| T1146 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2920688992 |
|
|
Jul 16 05:10:23 PM PDT 24 |
Jul 16 05:10:37 PM PDT 24 |
14585800 ps |
| T1147 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2055701095 |
|
|
Jul 16 05:11:07 PM PDT 24 |
Jul 16 05:11:24 PM PDT 24 |
11454000 ps |
| T1148 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1844379542 |
|
|
Jul 16 05:10:51 PM PDT 24 |
Jul 16 05:11:04 PM PDT 24 |
25101900 ps |
| T1149 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3108969864 |
|
|
Jul 16 05:10:55 PM PDT 24 |
Jul 16 05:11:10 PM PDT 24 |
37087700 ps |
| T1150 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1032673165 |
|
|
Jul 16 05:10:59 PM PDT 24 |
Jul 16 05:11:17 PM PDT 24 |
21137100 ps |
| T1151 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3385351124 |
|
|
Jul 16 05:11:05 PM PDT 24 |
Jul 16 05:11:19 PM PDT 24 |
18165100 ps |
| T1152 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1773652913 |
|
|
Jul 16 05:10:48 PM PDT 24 |
Jul 16 05:11:06 PM PDT 24 |
61485100 ps |
| T302 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.315502599 |
|
|
Jul 16 05:11:03 PM PDT 24 |
Jul 16 05:11:22 PM PDT 24 |
55774800 ps |
| T261 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.437722139 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:10:47 PM PDT 24 |
218652900 ps |
| T267 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.678930515 |
|
|
Jul 16 05:10:36 PM PDT 24 |
Jul 16 05:10:54 PM PDT 24 |
54095800 ps |
| T367 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3696286441 |
|
|
Jul 16 05:10:53 PM PDT 24 |
Jul 16 05:18:32 PM PDT 24 |
1496155400 ps |
| T1153 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.820317752 |
|
|
Jul 16 05:10:49 PM PDT 24 |
Jul 16 05:11:03 PM PDT 24 |
19478200 ps |
| T256 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3152260903 |
|
|
Jul 16 05:10:58 PM PDT 24 |
Jul 16 05:11:17 PM PDT 24 |
51100100 ps |
| T1154 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1504948409 |
|
|
Jul 16 05:11:03 PM PDT 24 |
Jul 16 05:11:17 PM PDT 24 |
62147800 ps |
| T1155 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2440076579 |
|
|
Jul 16 05:10:53 PM PDT 24 |
Jul 16 05:11:08 PM PDT 24 |
16535200 ps |
| T1156 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4061305568 |
|
|
Jul 16 05:11:07 PM PDT 24 |
Jul 16 05:11:26 PM PDT 24 |
105073400 ps |
| T368 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2516501037 |
|
|
Jul 16 05:10:36 PM PDT 24 |
Jul 16 05:25:49 PM PDT 24 |
1631242800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2623283296 |
|
|
Jul 16 05:10:24 PM PDT 24 |
Jul 16 05:10:43 PM PDT 24 |
50410800 ps |
| T1158 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1932220022 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:11:12 PM PDT 24 |
3415817400 ps |
| T1159 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.585110994 |
|
|
Jul 16 05:10:25 PM PDT 24 |
Jul 16 05:10:41 PM PDT 24 |
17672700 ps |
| T1160 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1952844031 |
|
|
Jul 16 05:10:38 PM PDT 24 |
Jul 16 05:10:54 PM PDT 24 |
21043900 ps |
| T233 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3676629115 |
|
|
Jul 16 05:10:34 PM PDT 24 |
Jul 16 05:10:49 PM PDT 24 |
19139800 ps |
| T1161 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2466082137 |
|
|
Jul 16 05:10:44 PM PDT 24 |
Jul 16 05:11:01 PM PDT 24 |
29967000 ps |
| T1162 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3040646142 |
|
|
Jul 16 05:11:04 PM PDT 24 |
Jul 16 05:11:19 PM PDT 24 |
17773300 ps |
| T1163 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1706274265 |
|
|
Jul 16 05:11:06 PM PDT 24 |
Jul 16 05:11:26 PM PDT 24 |
184648000 ps |
| T266 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.234845072 |
|
|
Jul 16 05:10:39 PM PDT 24 |
Jul 16 05:10:59 PM PDT 24 |
103325800 ps |
| T1164 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.868042950 |
|
|
Jul 16 05:10:21 PM PDT 24 |
Jul 16 05:10:35 PM PDT 24 |
43588600 ps |
| T1165 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1298194184 |
|
|
Jul 16 05:10:51 PM PDT 24 |
Jul 16 05:11:06 PM PDT 24 |
42144100 ps |
| T234 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1585827109 |
|
|
Jul 16 05:10:24 PM PDT 24 |
Jul 16 05:10:40 PM PDT 24 |
27577400 ps |
| T1166 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.4279938949 |
|
|
Jul 16 05:10:40 PM PDT 24 |
Jul 16 05:11:00 PM PDT 24 |
59181600 ps |
| T1167 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2491279539 |
|
|
Jul 16 05:10:58 PM PDT 24 |
Jul 16 05:11:17 PM PDT 24 |
146424600 ps |
| T1168 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1510628106 |
|
|
Jul 16 05:10:59 PM PDT 24 |
Jul 16 05:11:14 PM PDT 24 |
57996400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2579848481 |
|
|
Jul 16 05:11:01 PM PDT 24 |
Jul 16 05:11:16 PM PDT 24 |
14580400 ps |
| T1170 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2743755311 |
|
|
Jul 16 05:10:46 PM PDT 24 |
Jul 16 05:11:05 PM PDT 24 |
198798600 ps |
| T1171 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3154826527 |
|
|
Jul 16 05:10:54 PM PDT 24 |
Jul 16 05:11:10 PM PDT 24 |
24611000 ps |
| T1172 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.512556805 |
|
|
Jul 16 05:10:51 PM PDT 24 |
Jul 16 05:11:07 PM PDT 24 |
16573400 ps |
| T1173 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3131543513 |
|
|
Jul 16 05:11:03 PM PDT 24 |
Jul 16 05:11:20 PM PDT 24 |
45944200 ps |
| T366 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2875084928 |
|
|
Jul 16 05:11:10 PM PDT 24 |
Jul 16 05:17:37 PM PDT 24 |
490794200 ps |
| T1174 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.42768348 |
|
|
Jul 16 05:10:37 PM PDT 24 |
Jul 16 05:10:51 PM PDT 24 |
18145700 ps |
| T1175 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3549785382 |
|
|
Jul 16 05:10:41 PM PDT 24 |
Jul 16 05:11:00 PM PDT 24 |
134719300 ps |
| T363 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.475223307 |
|
|
Jul 16 05:10:59 PM PDT 24 |
Jul 16 05:26:09 PM PDT 24 |
1540487200 ps |
| T1176 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3228632342 |
|
|
Jul 16 05:10:52 PM PDT 24 |
Jul 16 05:11:07 PM PDT 24 |
15764400 ps |
| T369 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1820646714 |
|
|
Jul 16 05:10:41 PM PDT 24 |
Jul 16 05:18:23 PM PDT 24 |
355946300 ps |
| T1177 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.676838969 |
|
|
Jul 16 05:10:42 PM PDT 24 |
Jul 16 05:10:58 PM PDT 24 |
16416400 ps |
| T303 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1922578516 |
|
|
Jul 16 05:10:34 PM PDT 24 |
Jul 16 05:10:50 PM PDT 24 |
229847200 ps |
| T1178 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3812212845 |
|
|
Jul 16 05:10:57 PM PDT 24 |
Jul 16 05:11:12 PM PDT 24 |
27029800 ps |
| T1179 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4255838719 |
|
|
Jul 16 05:10:39 PM PDT 24 |
Jul 16 05:10:56 PM PDT 24 |
12201700 ps |
| T1180 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.306867386 |
|
|
Jul 16 05:11:07 PM PDT 24 |
Jul 16 05:11:22 PM PDT 24 |
36592300 ps |
| T1181 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.288157953 |
|
|
Jul 16 05:10:57 PM PDT 24 |
Jul 16 05:11:15 PM PDT 24 |
11508300 ps |
| T1182 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2003124090 |
|
|
Jul 16 05:10:59 PM PDT 24 |
Jul 16 05:11:16 PM PDT 24 |
20825800 ps |
| T364 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2883340277 |
|
|
Jul 16 05:10:36 PM PDT 24 |
Jul 16 05:25:46 PM PDT 24 |
2776705000 ps |
| T370 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1073695705 |
|
|
Jul 16 05:10:53 PM PDT 24 |
Jul 16 05:17:18 PM PDT 24 |
332541900 ps |
| T1183 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3093194291 |
|
|
Jul 16 05:10:35 PM PDT 24 |
Jul 16 05:11:06 PM PDT 24 |
1126963800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1176247592 |
|
|
Jul 16 05:10:55 PM PDT 24 |
Jul 16 05:11:12 PM PDT 24 |
18783700 ps |
| T1185 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3465959814 |
|
|
Jul 16 05:10:40 PM PDT 24 |
Jul 16 05:10:58 PM PDT 24 |
21350200 ps |
| T1186 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3190684573 |
|
|
Jul 16 05:10:55 PM PDT 24 |
Jul 16 05:11:10 PM PDT 24 |
15885500 ps |
| T1187 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1674624982 |
|
|
Jul 16 05:10:42 PM PDT 24 |
Jul 16 05:11:01 PM PDT 24 |
157664300 ps |
| T1188 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2107395322 |
|
|
Jul 16 05:10:43 PM PDT 24 |
Jul 16 05:11:00 PM PDT 24 |
13257400 ps |
| T304 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.500149986 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:11:07 PM PDT 24 |
204489400 ps |
| T1189 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1756622278 |
|
|
Jul 16 05:10:35 PM PDT 24 |
Jul 16 05:10:50 PM PDT 24 |
15287200 ps |
| T1190 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1538810571 |
|
|
Jul 16 05:10:56 PM PDT 24 |
Jul 16 05:11:14 PM PDT 24 |
13083600 ps |
| T1191 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2030941084 |
|
|
Jul 16 05:10:52 PM PDT 24 |
Jul 16 05:11:07 PM PDT 24 |
17042500 ps |
| T1192 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4226256068 |
|
|
Jul 16 05:11:02 PM PDT 24 |
Jul 16 05:11:23 PM PDT 24 |
669886800 ps |
| T1193 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3915988357 |
|
|
Jul 16 05:10:41 PM PDT 24 |
Jul 16 05:10:59 PM PDT 24 |
21987100 ps |
| T1194 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.781657709 |
|
|
Jul 16 05:10:51 PM PDT 24 |
Jul 16 05:11:11 PM PDT 24 |
308840600 ps |
| T1195 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2062038796 |
|
|
Jul 16 05:10:33 PM PDT 24 |
Jul 16 05:11:11 PM PDT 24 |
124737800 ps |
| T265 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.503826122 |
|
|
Jul 16 05:10:25 PM PDT 24 |
Jul 16 05:10:46 PM PDT 24 |
113053900 ps |
| T1196 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4196005956 |
|
|
Jul 16 05:10:40 PM PDT 24 |
Jul 16 05:11:01 PM PDT 24 |
663598600 ps |
| T1197 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3107471297 |
|
|
Jul 16 05:10:45 PM PDT 24 |
Jul 16 05:11:01 PM PDT 24 |
11922100 ps |
| T1198 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.685533923 |
|
|
Jul 16 05:10:59 PM PDT 24 |
Jul 16 05:11:15 PM PDT 24 |
206311400 ps |
| T1199 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2496205097 |
|
|
Jul 16 05:10:44 PM PDT 24 |
Jul 16 05:10:58 PM PDT 24 |
11179600 ps |
| T1200 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3888583539 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:10:42 PM PDT 24 |
136998100 ps |
| T1201 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4134900896 |
|
|
Jul 16 05:10:25 PM PDT 24 |
Jul 16 05:10:58 PM PDT 24 |
49710000 ps |
| T1202 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4099319592 |
|
|
Jul 16 05:10:25 PM PDT 24 |
Jul 16 05:10:41 PM PDT 24 |
25689800 ps |
| T1203 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4235589519 |
|
|
Jul 16 05:10:45 PM PDT 24 |
Jul 16 05:10:59 PM PDT 24 |
30466700 ps |
| T1204 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1998866137 |
|
|
Jul 16 05:10:54 PM PDT 24 |
Jul 16 05:11:08 PM PDT 24 |
16371000 ps |
| T1205 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.986311991 |
|
|
Jul 16 05:10:53 PM PDT 24 |
Jul 16 05:11:08 PM PDT 24 |
54535500 ps |
| T1206 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.984036460 |
|
|
Jul 16 05:10:56 PM PDT 24 |
Jul 16 05:11:12 PM PDT 24 |
22187000 ps |
| T1207 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4024709311 |
|
|
Jul 16 05:10:39 PM PDT 24 |
Jul 16 05:10:55 PM PDT 24 |
19540000 ps |
| T1208 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.320299358 |
|
|
Jul 16 05:11:03 PM PDT 24 |
Jul 16 05:11:18 PM PDT 24 |
15905300 ps |
| T1209 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1282838332 |
|
|
Jul 16 05:10:41 PM PDT 24 |
Jul 16 05:11:01 PM PDT 24 |
104401700 ps |
| T1210 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.228043731 |
|
|
Jul 16 05:10:40 PM PDT 24 |
Jul 16 05:10:57 PM PDT 24 |
22305600 ps |
| T235 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3348126290 |
|
|
Jul 16 05:10:27 PM PDT 24 |
Jul 16 05:10:42 PM PDT 24 |
30941600 ps |
| T1211 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1099704500 |
|
|
Jul 16 05:10:37 PM PDT 24 |
Jul 16 05:10:51 PM PDT 24 |
15994100 ps |
| T1212 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.4042476633 |
|
|
Jul 16 05:10:41 PM PDT 24 |
Jul 16 05:11:02 PM PDT 24 |
378247800 ps |
| T1213 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.127036972 |
|
|
Jul 16 05:11:00 PM PDT 24 |
Jul 16 05:11:14 PM PDT 24 |
41592400 ps |
| T1214 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2510962264 |
|
|
Jul 16 05:10:47 PM PDT 24 |
Jul 16 05:11:03 PM PDT 24 |
252307600 ps |
| T1215 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3229096066 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:10:41 PM PDT 24 |
12157600 ps |
| T1216 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2703304375 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:10:59 PM PDT 24 |
230327700 ps |
| T1217 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3245043156 |
|
|
Jul 16 05:11:00 PM PDT 24 |
Jul 16 05:11:21 PM PDT 24 |
92866600 ps |
| T1218 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2205785936 |
|
|
Jul 16 05:10:23 PM PDT 24 |
Jul 16 05:10:40 PM PDT 24 |
30847500 ps |
| T1219 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.224846052 |
|
|
Jul 16 05:10:27 PM PDT 24 |
Jul 16 05:10:44 PM PDT 24 |
21664800 ps |
| T1220 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4078369724 |
|
|
Jul 16 05:10:56 PM PDT 24 |
Jul 16 05:11:11 PM PDT 24 |
165099400 ps |
| T1221 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3134943852 |
|
|
Jul 16 05:10:28 PM PDT 24 |
Jul 16 05:11:16 PM PDT 24 |
44911700 ps |
| T1222 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2656454084 |
|
|
Jul 16 05:11:03 PM PDT 24 |
Jul 16 05:11:17 PM PDT 24 |
15262000 ps |
| T1223 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1550864321 |
|
|
Jul 16 05:10:35 PM PDT 24 |
Jul 16 05:10:52 PM PDT 24 |
120620300 ps |
| T1224 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1161496203 |
|
|
Jul 16 05:11:05 PM PDT 24 |
Jul 16 05:11:23 PM PDT 24 |
20767700 ps |
| T1225 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1860683706 |
|
|
Jul 16 05:10:58 PM PDT 24 |
Jul 16 05:11:13 PM PDT 24 |
41783600 ps |
| T1226 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1495085124 |
|
|
Jul 16 05:10:52 PM PDT 24 |
Jul 16 05:11:11 PM PDT 24 |
46183300 ps |
| T1227 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3192555457 |
|
|
Jul 16 05:10:45 PM PDT 24 |
Jul 16 05:11:02 PM PDT 24 |
14767500 ps |
| T1228 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3667855046 |
|
|
Jul 16 05:10:54 PM PDT 24 |
Jul 16 05:11:09 PM PDT 24 |
18557800 ps |
| T236 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1432047707 |
|
|
Jul 16 05:10:39 PM PDT 24 |
Jul 16 05:10:54 PM PDT 24 |
33495900 ps |
| T1229 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2393278951 |
|
|
Jul 16 05:10:47 PM PDT 24 |
Jul 16 05:11:05 PM PDT 24 |
158163400 ps |
| T1230 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2552120689 |
|
|
Jul 16 05:10:45 PM PDT 24 |
Jul 16 05:11:03 PM PDT 24 |
37596200 ps |
| T1231 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1957586447 |
|
|
Jul 16 05:10:56 PM PDT 24 |
Jul 16 05:11:11 PM PDT 24 |
57177200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2124240856 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:10:41 PM PDT 24 |
15776700 ps |
| T1233 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1477553815 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:10:43 PM PDT 24 |
12853800 ps |
| T1234 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2640036641 |
|
|
Jul 16 05:11:05 PM PDT 24 |
Jul 16 05:11:19 PM PDT 24 |
42239400 ps |
| T1235 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3081444217 |
|
|
Jul 16 05:10:24 PM PDT 24 |
Jul 16 05:10:40 PM PDT 24 |
86949400 ps |
| T365 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2207325388 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:25:16 PM PDT 24 |
627889800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3763056502 |
|
|
Jul 16 05:10:23 PM PDT 24 |
Jul 16 05:10:40 PM PDT 24 |
15758000 ps |
| T1237 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.4254175759 |
|
|
Jul 16 05:10:42 PM PDT 24 |
Jul 16 05:11:02 PM PDT 24 |
192331000 ps |
| T1238 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3697071070 |
|
|
Jul 16 05:10:29 PM PDT 24 |
Jul 16 05:10:45 PM PDT 24 |
38544000 ps |
| T1239 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2070415302 |
|
|
Jul 16 05:10:52 PM PDT 24 |
Jul 16 05:11:07 PM PDT 24 |
46951000 ps |
| T1240 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3467463449 |
|
|
Jul 16 05:10:39 PM PDT 24 |
Jul 16 05:10:56 PM PDT 24 |
117755400 ps |
| T1241 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1077461552 |
|
|
Jul 16 05:10:26 PM PDT 24 |
Jul 16 05:10:43 PM PDT 24 |
276911700 ps |
| T1242 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.948858472 |
|
|
Jul 16 05:10:55 PM PDT 24 |
Jul 16 05:11:11 PM PDT 24 |
18468100 ps |
| T1243 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3135644669 |
|
|
Jul 16 05:10:22 PM PDT 24 |
Jul 16 05:10:39 PM PDT 24 |
47313800 ps |
| T1244 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2346999932 |
|
|
Jul 16 05:10:41 PM PDT 24 |
Jul 16 05:10:59 PM PDT 24 |
11979900 ps |
| T1245 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.338898653 |
|
|
Jul 16 05:10:25 PM PDT 24 |
Jul 16 05:10:40 PM PDT 24 |
42996600 ps |
| T1246 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.541313757 |
|
|
Jul 16 05:10:41 PM PDT 24 |
Jul 16 05:10:57 PM PDT 24 |
15953800 ps |
| T257 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.271163404 |
|
|
Jul 16 05:11:07 PM PDT 24 |
Jul 16 05:11:28 PM PDT 24 |
56822000 ps |
| T1247 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1972514597 |
|
|
Jul 16 05:10:29 PM PDT 24 |
Jul 16 05:10:43 PM PDT 24 |
59575700 ps |
| T1248 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1005051140 |
|
|
Jul 16 05:10:25 PM PDT 24 |
Jul 16 05:10:53 PM PDT 24 |
52096700 ps |
| T1249 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4031303434 |
|
|
Jul 16 05:11:13 PM PDT 24 |
Jul 16 05:11:30 PM PDT 24 |
18187500 ps |
| T1250 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2517679917 |
|
|
Jul 16 05:10:44 PM PDT 24 |
Jul 16 05:11:02 PM PDT 24 |
105733400 ps |
| T1251 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2053258448 |
|
|
Jul 16 05:10:55 PM PDT 24 |
Jul 16 05:11:10 PM PDT 24 |
34390000 ps |