Unified Coverage Report :: Tests

Tests

dashboard | hierarchy | modlist | groups | tests | asserts

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.15	95.70	93.96	98.31	91.84	98.21	96.89	98.12

Total test records in report: 1262

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1252	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2403889473			Jul 16 05:10:55 PM PDT 24	Jul 16 05:11:14 PM PDT 24	116716500 ps
T1253	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.652966767			Jul 16 05:10:36 PM PDT 24	Jul 16 05:11:08 PM PDT 24	213650700 ps
T371	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2431761907			Jul 16 05:10:40 PM PDT 24	Jul 16 05:25:37 PM PDT 24	702080900 ps
T1254	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4039072692			Jul 16 05:10:53 PM PDT 24	Jul 16 05:11:11 PM PDT 24	43086200 ps
T1255	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.772935635			Jul 16 05:10:58 PM PDT 24	Jul 16 05:11:16 PM PDT 24	139680200 ps
T1256	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2936759864			Jul 16 05:10:55 PM PDT 24	Jul 16 05:11:10 PM PDT 24	32799600 ps
T1257	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.175346425			Jul 16 05:10:42 PM PDT 24	Jul 16 05:11:01 PM PDT 24	98443900 ps
T1258	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2992661878			Jul 16 05:10:22 PM PDT 24	Jul 16 05:10:39 PM PDT 24	98437500 ps
T1259	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1400939472			Jul 16 05:10:46 PM PDT 24	Jul 16 05:11:01 PM PDT 24	93752300 ps
T1260	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.4119743305			Jul 16 05:11:10 PM PDT 24	Jul 16 05:11:28 PM PDT 24	181592300 ps
T1261	/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3156689765			Jul 16 05:10:23 PM PDT 24	Jul 16 05:10:59 PM PDT 24	310114100 ps
T1262	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1640762855			Jul 16 05:10:54 PM PDT 24	Jul 16 05:11:13 PM PDT 24	184677400 ps

Test location	/workspace/coverage/default/0.flash_ctrl_rw_serr.3737294531
Short name	T4
Test name
Test status
Simulation time	4325174700 ps
CPU time	756.82 seconds
Started	Jul 16 05:31:21 PM PDT 24
Finished	Jul 16 05:43:58 PM PDT 24
Peak memory	312424 kb
Host	smart-ea7f30a7-cd87-4947-aa47-5dbb0fb86387
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737294531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s err.3737294531
Directory	/workspace/0.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma.815512873
Short name	T13
Test name
Test status
Simulation time	169760896700 ps
CPU time	1998.33 seconds
Started	Jul 16 05:36:34 PM PDT 24
Finished	Jul 16 06:09:55 PM PDT 24
Peak memory	264712 kb
Host	smart-489e3428-4583-46d0-9ba9-0e2fc16ae529
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815512873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_hw_rma.815512873
Directory	/workspace/2.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1689109258
Short name	T101
Test name
Test status
Simulation time	2569880300 ps
CPU time	894.24 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:25:22 PM PDT 24
Peak memory	263720 kb
Host	smart-d2c850a4-dc0b-4377-84ac-5992a6a50b4b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689109258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _tl_intg_err.1689109258
Directory	/workspace/3.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mid_op_rst.2288374107
Short name	T84
Test name
Test status
Simulation time	1799686100 ps
CPU time	68.34 seconds
Started	Jul 16 05:30:03 PM PDT 24
Finished	Jul 16 05:31:12 PM PDT 24
Peak memory	260504 kb
Host	smart-10e2f40b-3748-4b58-9bb6-ae93c9195534
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288374107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.2288374107
Directory	/workspace/2.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/19.flash_ctrl_mp_regions.1257578057
Short name	T116
Test name
Test status
Simulation time	11332800900 ps
CPU time	269.53 seconds
Started	Jul 16 05:34:16 PM PDT 24
Finished	Jul 16 05:38:46 PM PDT 24
Peak memory	275004 kb
Host	smart-c1705662-d990-4bd4-b555-7460f39a72b7
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257578057 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.1257578057
Directory	/workspace/19.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_cm.215397561
Short name	T14
Test name
Test status
Simulation time	7150154300 ps
CPU time	4795.25 seconds
Started	Jul 16 05:31:25 PM PDT 24
Finished	Jul 16 06:51:22 PM PDT 24
Peak memory	289988 kb
Host	smart-7bc314a0-6fc3-4447-903a-e78310a39933
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215397561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.215397561
Directory	/workspace/4.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/48.flash_ctrl_otp_reset.2117405797
Short name	T10
Test name
Test status
Simulation time	41031300 ps
CPU time	109.15 seconds
Started	Jul 16 05:37:09 PM PDT 24
Finished	Jul 16 05:38:59 PM PDT 24
Peak memory	261088 kb
Host	smart-74f5dcca-927a-4d3f-b940-9f743d40b070
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117405797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o tp_reset.2117405797
Directory	/workspace/48.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3467896955
Short name	T58
Test name
Test status
Simulation time	157520900 ps
CPU time	16.95 seconds
Started	Jul 16 05:10:45 PM PDT 24
Finished	Jul 16 05:11:03 PM PDT 24
Peak memory	270536 kb
Host	smart-14434248-865a-436b-a702-b2d71a9ef445
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467896955 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3467896955
Directory	/workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_erase_suspend.3997625235
Short name	T183
Test name
Test status
Simulation time	3886120600 ps
CPU time	304.27 seconds
Started	Jul 16 05:30:19 PM PDT 24
Finished	Jul 16 05:35:24 PM PDT 24
Peak memory	263388 kb
Host	smart-89122dd6-1e0e-47ab-b563-cb0b9c9b98a7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3997625235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.3997625235
Directory	/workspace/3.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.3252769181
Short name	T2
Test name
Test status
Simulation time	43533700 ps
CPU time	31.31 seconds
Started	Jul 16 05:35:02 PM PDT 24
Finished	Jul 16 05:35:34 PM PDT 24
Peak memory	274836 kb
Host	smart-3bf81d85-8961-402e-a155-cfc589504269
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252769181 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.3252769181
Directory	/workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/17.flash_ctrl_otp_reset.2083740063
Short name	T64
Test name
Test status
Simulation time	39273400 ps
CPU time	131.47 seconds
Started	Jul 16 05:33:47 PM PDT 24
Finished	Jul 16 05:35:59 PM PDT 24
Peak memory	259944 kb
Host	smart-ff6cce62-495e-4bda-9de2-0a451ea068a4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083740063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o tp_reset.2083740063
Directory	/workspace/17.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3070994083
Short name	T9
Test name
Test status
Simulation time	41485700 ps
CPU time	13.99 seconds
Started	Jul 16 05:30:58 PM PDT 24
Finished	Jul 16 05:31:12 PM PDT 24
Peak memory	262576 kb
Host	smart-0d90ed8c-278e-4bb5-a443-a692d22aadd8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070994083 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3070994083
Directory	/workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/58.flash_ctrl_otp_reset.2301033025
Short name	T62
Test name
Test status
Simulation time	141866400 ps
CPU time	131.63 seconds
Started	Jul 16 05:37:16 PM PDT 24
Finished	Jul 16 05:39:29 PM PDT 24
Peak memory	259992 kb
Host	smart-17e9eb07-7f39-45da-afb3-f04525b8c2bf
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301033025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o tp_reset.2301033025
Directory	/workspace/58.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_derr.761830168
Short name	T149
Test name
Test status
Simulation time	3263520700 ps
CPU time	627.3 seconds
Started	Jul 16 05:32:34 PM PDT 24
Finished	Jul 16 05:43:02 PM PDT 24
Peak memory	316924 kb
Host	smart-5f0cc7bb-7afd-4e2d-9cff-e1ce392d245f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761830168 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.flash_ctrl_rw_derr.761830168
Directory	/workspace/3.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/28.flash_ctrl_alert_test.23818654
Short name	T86
Test name
Test status
Simulation time	73936700 ps
CPU time	13.42 seconds
Started	Jul 16 05:35:24 PM PDT 24
Finished	Jul 16 05:35:38 PM PDT 24
Peak memory	265228 kb
Host	smart-9ce3a188-84cf-40f5-9269-b0ae86e7d5b4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23818654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.23818654
Directory	/workspace/28.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1280421642
Short name	T260
Test name
Test status
Simulation time	15874900 ps
CPU time	13.58 seconds
Started	Jul 16 05:10:27 PM PDT 24
Finished	Jul 16 05:10:42 PM PDT 24
Peak memory	261172 kb
Host	smart-209b4636-87d4-4038-a0cb-8877fb1c60b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280421642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.1 280421642
Directory	/workspace/0.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/32.flash_ctrl_otp_reset.998574253
Short name	T166
Test name
Test status
Simulation time	146130600 ps
CPU time	132.39 seconds
Started	Jul 16 05:35:41 PM PDT 24
Finished	Jul 16 05:37:54 PM PDT 24
Peak memory	265004 kb
Host	smart-46d920e9-4180-4b98-a6be-7e1b329f417f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998574253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot p_reset.998574253
Directory	/workspace/32.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1642201271
Short name	T182
Test name
Test status
Simulation time	5744288800 ps
CPU time	146.06 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:39:17 PM PDT 24
Peak memory	293928 kb
Host	smart-b5214d5b-3d23-44d4-945a-6ecaa23f6523
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642201271 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.1642201271
Directory	/workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1310600596
Short name	T449
Test name
Test status
Simulation time	10021413600 ps
CPU time	86.84 seconds
Started	Jul 16 05:33:23 PM PDT 24
Finished	Jul 16 05:34:50 PM PDT 24
Peak memory	323320 kb
Host	smart-a5224b47-1dc9-4c23-8b41-c21e2cf004d7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310600596 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.1310600596
Directory	/workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_sec_info_access.996540433
Short name	T193
Test name
Test status
Simulation time	2151527000 ps
CPU time	75.92 seconds
Started	Jul 16 05:38:45 PM PDT 24
Finished	Jul 16 05:40:02 PM PDT 24
Peak memory	265032 kb
Host	smart-05d415be-8db5-44ec-8838-8e8ce706fe1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996540433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.996540433
Directory	/workspace/9.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3790289115
Short name	T253
Test name
Test status
Simulation time	104620600 ps
CPU time	19.81 seconds
Started	Jul 16 05:10:41 PM PDT 24
Finished	Jul 16 05:11:03 PM PDT 24
Peak memory	263708 kb
Host	smart-87c97022-f41e-402c-98e3-66fadb47fdfa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790289115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors. 3790289115
Directory	/workspace/10.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/12.flash_ctrl_re_evict.591411526
Short name	T73
Test name
Test status
Simulation time	441063500 ps
CPU time	34.84 seconds
Started	Jul 16 05:33:08 PM PDT 24
Finished	Jul 16 05:33:43 PM PDT 24
Peak memory	268496 kb
Host	smart-a9792342-54d2-4c90-b665-3562e475fcac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591411526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_re_evict.591411526
Directory	/workspace/12.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/32.flash_ctrl_disable.2191338697
Short name	T94
Test name
Test status
Simulation time	18987300 ps
CPU time	20.98 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:37:18 PM PDT 24
Peak memory	273616 kb
Host	smart-2428f6f3-2acd-4cb0-bbc8-11fa3b32c0d4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191338697 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_disable.2191338697
Directory	/workspace/32.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.794938176
Short name	T190
Test name
Test status
Simulation time	28611500 ps
CPU time	13.6 seconds
Started	Jul 16 05:31:21 PM PDT 24
Finished	Jul 16 05:31:35 PM PDT 24
Peak memory	265324 kb
Host	smart-3cf0c522-d7d2-4a60-b795-3ac3a9262f13
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794938176 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.794938176
Directory	/workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rma_err.3462279730
Short name	T160
Test name
Test status
Simulation time	157491371100 ps
CPU time	990.54 seconds
Started	Jul 16 05:29:41 PM PDT 24
Finished	Jul 16 05:46:12 PM PDT 24
Peak memory	262608 kb
Host	smart-e0b30af3-fe9a-4ca8-a1a8-23a89dd9ffcd
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462279730 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.3462279730
Directory	/workspace/0.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_fetch_code.1997371680
Short name	T49
Test name
Test status
Simulation time	1326227000 ps
CPU time	31.54 seconds
Started	Jul 16 05:32:59 PM PDT 24
Finished	Jul 16 05:33:31 PM PDT 24
Peak memory	262520 kb
Host	smart-7eca1158-964f-4522-9d7c-9edff15a1702
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997371680 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.1997371680
Directory	/workspace/6.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/7.flash_ctrl_otp_reset.2123426115
Short name	T169
Test name
Test status
Simulation time	39253400 ps
CPU time	109.6 seconds
Started	Jul 16 05:36:14 PM PDT 24
Finished	Jul 16 05:38:04 PM PDT 24
Peak memory	260112 kb
Host	smart-b11fcb4b-db19-49d0-a13b-28a308470183
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123426115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot p_reset.2123426115
Directory	/workspace/7.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mid_op_rst.3241985415
Short name	T75
Test name
Test status
Simulation time	2658127200 ps
CPU time	71.99 seconds
Started	Jul 16 05:29:43 PM PDT 24
Finished	Jul 16 05:30:55 PM PDT 24
Peak memory	260884 kb
Host	smart-99bc72de-67b0-4e4c-8e0d-a41d5cc55631
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3241985415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.3241985415
Directory	/workspace/1.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rand_ops.3050426571
Short name	T53
Test name
Test status
Simulation time	1389519300 ps
CPU time	894.73 seconds
Started	Jul 16 05:36:37 PM PDT 24
Finished	Jul 16 05:51:33 PM PDT 24
Peak memory	284988 kb
Host	smart-fc576de8-db86-483e-b21f-1869c0081c69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050426571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.3050426571
Directory	/workspace/6.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1553085543
Short name	T95
Test name
Test status
Simulation time	4934545200 ps
CPU time	138.92 seconds
Started	Jul 16 05:35:59 PM PDT 24
Finished	Jul 16 05:38:19 PM PDT 24
Peak memory	260788 kb
Host	smart-d5e9fd85-447e-4def-bf66-96ddacba5388
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553085543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_ hw_sec_otp.1553085543
Directory	/workspace/36.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_type.2317591509
Short name	T78
Test name
Test status
Simulation time	9018292600 ps
CPU time	3183.35 seconds
Started	Jul 16 05:29:54 PM PDT 24
Finished	Jul 16 06:22:58 PM PDT 24
Peak memory	262060 kb
Host	smart-3009a9d3-ed07-426e-8491-8f993a0c8f1f
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317591509 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.2317591509
Directory	/workspace/2.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/5.flash_ctrl_mp_regions.388194092
Short name	T119
Test name
Test status
Simulation time	57302385500 ps
CPU time	448.6 seconds
Started	Jul 16 05:31:25 PM PDT 24
Finished	Jul 16 05:38:55 PM PDT 24
Peak memory	274412 kb
Host	smart-909c857a-b5af-403a-8464-390e1a30f211
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388194092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.388194092
Directory	/workspace/5.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/4.flash_ctrl_lcmgr_intg.2635739266
Short name	T152
Test name
Test status
Simulation time	25093400 ps
CPU time	13.66 seconds
Started	Jul 16 05:36:34 PM PDT 24
Finished	Jul 16 05:36:49 PM PDT 24
Peak memory	259912 kb
Host	smart-99c444ab-1ac5-47e5-bbae-dfe724e4b48f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635739266 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.2635739266
Directory	/workspace/4.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2383136822
Short name	T229
Test name
Test status
Simulation time	1799183700 ps
CPU time	894.85 seconds
Started	Jul 16 05:10:48 PM PDT 24
Finished	Jul 16 05:25:43 PM PDT 24
Peak memory	263752 kb
Host	smart-0e3c6d20-915f-43a0-ad77-25f05dd23d46
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383136822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl _tl_intg_err.2383136822
Directory	/workspace/8.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1585827109
Short name	T234
Test name
Test status
Simulation time	27577400 ps
CPU time	14.12 seconds
Started	Jul 16 05:10:24 PM PDT 24
Finished	Jul 16 05:10:40 PM PDT 24
Peak memory	262216 kb
Host	smart-f65479aa-83e9-401f-a65b-d1677907da5a
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585827109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_mem_partial_access.1585827109
Directory	/workspace/0.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.179621349
Short name	T1129
Test name
Test status
Simulation time	17304300 ps
CPU time	14.03 seconds
Started	Jul 16 05:10:41 PM PDT 24
Finished	Jul 16 05:10:57 PM PDT 24
Peak memory	260972 kb
Host	smart-d052e47d-cec7-4785-9311-970fcb4ccfcd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179621349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.179621349
Directory	/workspace/13.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd.1738121141
Short name	T200
Test name
Test status
Simulation time	1812080000 ps
CPU time	101 seconds
Started	Jul 16 05:34:40 PM PDT 24
Finished	Jul 16 05:36:21 PM PDT 24
Peak memory	294980 kb
Host	smart-b5914bfc-22cd-46cb-8e06-54bf0f9b6ee8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738121141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_intr_rd.1738121141
Directory	/workspace/16.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/17.flash_ctrl_invalid_op.1705506108
Short name	T414
Test name
Test status
Simulation time	10818737400 ps
CPU time	91.34 seconds
Started	Jul 16 05:33:39 PM PDT 24
Finished	Jul 16 05:35:11 PM PDT 24
Peak memory	260640 kb
Host	smart-19010f46-0e97-4c14-a527-50754bc87fd0
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705506108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.1 705506108
Directory	/workspace/17.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/13.flash_ctrl_re_evict.1743145379
Short name	T54
Test name
Test status
Simulation time	69271700 ps
CPU time	34.65 seconds
Started	Jul 16 05:33:18 PM PDT 24
Finished	Jul 16 05:33:53 PM PDT 24
Peak memory	268380 kb
Host	smart-f0d5f608-e936-43ae-b23a-a12be8ee0a6f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743145379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_re_evict.1743145379
Directory	/workspace/13.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd.3516167073
Short name	T31
Test name
Test status
Simulation time	784756000 ps
CPU time	136.88 seconds
Started	Jul 16 05:36:13 PM PDT 24
Finished	Jul 16 05:38:31 PM PDT 24
Peak memory	294208 kb
Host	smart-33bdadec-a6cd-419c-9440-425a7f82bd96
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516167073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla sh_ctrl_intr_rd.3516167073
Directory	/workspace/38.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.503826122
Short name	T265
Test name
Test status
Simulation time	113053900 ps
CPU time	19.05 seconds
Started	Jul 16 05:10:25 PM PDT 24
Finished	Jul 16 05:10:46 PM PDT 24
Peak memory	263588 kb
Host	smart-e229121d-ccab-43aa-9039-24eed1d19109
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503826122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.503826122
Directory	/workspace/2.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wr_intg.1100281014
Short name	T243
Test name
Test status
Simulation time	56961300 ps
CPU time	15.11 seconds
Started	Jul 16 05:29:30 PM PDT 24
Finished	Jul 16 05:29:46 PM PDT 24
Peak memory	260860 kb
Host	smart-196017bf-e57a-4b3c-bc7e-617719ea83dd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100281014 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.1100281014
Directory	/workspace/0.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.3698669556
Short name	T52
Test name
Test status
Simulation time	45672600 ps
CPU time	13.84 seconds
Started	Jul 16 05:37:01 PM PDT 24
Finished	Jul 16 05:37:16 PM PDT 24
Peak memory	277080 kb
Host	smart-47a86736-c918-44eb-9e1f-db5d84b8bf9c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3698669556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.3698669556
Directory	/workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_info_access.2877953134
Short name	T194
Test name
Test status
Simulation time	1779947700 ps
CPU time	61.36 seconds
Started	Jul 16 05:29:54 PM PDT 24
Finished	Jul 16 05:30:56 PM PDT 24
Peak memory	264180 kb
Host	smart-3a1ac64d-2bfd-465b-b9d9-db68d8c53567
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877953134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.2877953134
Directory	/workspace/0.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/11.flash_ctrl_invalid_op.3929609326
Short name	T139
Test name
Test status
Simulation time	2166278200 ps
CPU time	65.26 seconds
Started	Jul 16 05:36:51 PM PDT 24
Finished	Jul 16 05:37:57 PM PDT 24
Peak memory	263228 kb
Host	smart-6f02ba9a-a7ee-4e80-a7da-8b64baa3797e
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929609326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.3 929609326
Directory	/workspace/11.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1021797622
Short name	T222
Test name
Test status
Simulation time	700710900 ps
CPU time	756.26 seconds
Started	Jul 16 05:10:51 PM PDT 24
Finished	Jul 16 05:23:28 PM PDT 24
Peak memory	263744 kb
Host	smart-66abf4f3-002f-452c-8236-b96f6b23103c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021797622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr l_tl_intg_err.1021797622
Directory	/workspace/19.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd.2024176502
Short name	T32
Test name
Test status
Simulation time	2144116800 ps
CPU time	126.79 seconds
Started	Jul 16 05:34:26 PM PDT 24
Finished	Jul 16 05:36:34 PM PDT 24
Peak memory	291432 kb
Host	smart-b885a7ff-a5bf-43bc-855f-e76397401486
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024176502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_intr_rd.2024176502
Directory	/workspace/8.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb_redun.3868693511
Short name	T67
Test name
Test status
Simulation time	815762100 ps
CPU time	18.09 seconds
Started	Jul 16 05:29:27 PM PDT 24
Finished	Jul 16 05:29:45 PM PDT 24
Peak memory	264472 kb
Host	smart-4862541d-b529-4ebc-a66c-1b9fd179f6e7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868693511 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3868693511
Directory	/workspace/0.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3886270966
Short name	T223
Test name
Test status
Simulation time	78386200 ps
CPU time	18.1 seconds
Started	Jul 16 05:10:51 PM PDT 24
Finished	Jul 16 05:11:10 PM PDT 24
Peak memory	263704 kb
Host	smart-abfff235-0dae-4919-8d21-516ce98018f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886270966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors. 3886270966
Directory	/workspace/15.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.547310776
Short name	T100
Test name
Test status
Simulation time	2907194000 ps
CPU time	61.81 seconds
Started	Jul 16 05:10:21 PM PDT 24
Finished	Jul 16 05:11:24 PM PDT 24
Peak memory	261348 kb
Host	smart-13045e21-ef4a-4f6c-bf85-8436d33c7ffe
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547310776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.flash_ctrl_csr_aliasing.547310776
Directory	/workspace/0.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.1123987097
Short name	T684
Test name
Test status
Simulation time	46674000 ps
CPU time	13.38 seconds
Started	Jul 16 05:33:24 PM PDT 24
Finished	Jul 16 05:33:38 PM PDT 24
Peak memory	265056 kb
Host	smart-d6661b97-021d-44a4-8b90-b1bd88eeb4d5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123987097 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.1123987097
Directory	/workspace/13.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/41.flash_ctrl_otp_reset.2351103114
Short name	T151
Test name
Test status
Simulation time	158722200 ps
CPU time	130.35 seconds
Started	Jul 16 05:38:56 PM PDT 24
Finished	Jul 16 05:41:07 PM PDT 24
Peak memory	265372 kb
Host	smart-cb4822a5-cc67-45fd-a970-c0a383f84324
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351103114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o tp_reset.2351103114
Directory	/workspace/41.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.617982781
Short name	T341
Test name
Test status
Simulation time	15187900 ps
CPU time	13.56 seconds
Started	Jul 16 05:29:56 PM PDT 24
Finished	Jul 16 05:30:10 PM PDT 24
Peak memory	260236 kb
Host	smart-3ab1ecd5-8672-4645-bfd1-7b9db09956b2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617982781 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.617982781
Directory	/workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_re_evict.560744914
Short name	T353
Test name
Test status
Simulation time	199741800 ps
CPU time	32.96 seconds
Started	Jul 16 05:33:49 PM PDT 24
Finished	Jul 16 05:34:23 PM PDT 24
Peak memory	275620 kb
Host	smart-087c25fc-4e8e-4f03-b8b0-07dbee888875
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560744914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_re_evict.560744914
Directory	/workspace/17.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/25.flash_ctrl_connect.1174775767
Short name	T104
Test name
Test status
Simulation time	27039700 ps
CPU time	16 seconds
Started	Jul 16 05:34:59 PM PDT 24
Finished	Jul 16 05:35:16 PM PDT 24
Peak memory	274760 kb
Host	smart-85f8e218-707b-4ddf-8348-198e4f2898d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174775767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1174775767
Directory	/workspace/25.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw.317125342
Short name	T568
Test name
Test status
Simulation time	4645132100 ps
CPU time	506.4 seconds
Started	Jul 16 05:33:29 PM PDT 24
Finished	Jul 16 05:41:55 PM PDT 24
Peak memory	314424 kb
Host	smart-7bc951c3-b044-4266-8d6a-e71678641ef9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317125342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.317125342
Directory	/workspace/15.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_win.2523585330
Short name	T192
Test name
Test status
Simulation time	3144179400 ps
CPU time	821.48 seconds
Started	Jul 16 05:30:29 PM PDT 24
Finished	Jul 16 05:44:11 PM PDT 24
Peak memory	270444 kb
Host	smart-3860b353-9576-4794-b68c-96f8833a81ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523585330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.2523585330
Directory	/workspace/3.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict.88305512
Short name	T344
Test name
Test status
Simulation time	187961200 ps
CPU time	31.87 seconds
Started	Jul 16 05:35:07 PM PDT 24
Finished	Jul 16 05:35:39 PM PDT 24
Peak memory	275620 kb
Host	smart-a4eed7c7-a8ca-4f21-bee7-d168cc1b8677
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88305512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flas h_ctrl_rw_evict.88305512
Directory	/workspace/26.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_access_after_disable.4077486351
Short name	T22
Test name
Test status
Simulation time	19930500 ps
CPU time	13.92 seconds
Started	Jul 16 05:29:28 PM PDT 24
Finished	Jul 16 05:29:42 PM PDT 24
Peak memory	265260 kb
Host	smart-02c4bcec-4832-4588-b6da-c9d531dc2858
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077486351 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.4077486351
Directory	/workspace/0.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_cm.963082485
Short name	T39
Test name
Test status
Simulation time	4231319100 ps
CPU time	4761.25 seconds
Started	Jul 16 05:29:30 PM PDT 24
Finished	Jul 16 06:48:52 PM PDT 24
Peak memory	295240 kb
Host	smart-82e8442d-4700-4f89-9127-19d606860c2c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963082485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.963082485
Directory	/workspace/0.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2140387990
Short name	T188
Test name
Test status
Simulation time	10012298400 ps
CPU time	308.7 seconds
Started	Jul 16 05:30:00 PM PDT 24
Finished	Jul 16 05:35:09 PM PDT 24
Peak memory	317612 kb
Host	smart-391f5ab8-6d58-4f1d-b9fb-66683b9d4d01
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140387990 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2140387990
Directory	/workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2090351589
Short name	T1014
Test name
Test status
Simulation time	10110518500 ps
CPU time	34.15 seconds
Started	Jul 16 05:32:51 PM PDT 24
Finished	Jul 16 05:33:25 PM PDT 24
Peak memory	265432 kb
Host	smart-6d3a1953-998d-43f5-a618-f00c0e126e68
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090351589 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2090351589
Directory	/workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.2564587473
Short name	T1028
Test name
Test status
Simulation time	15330900 ps
CPU time	13.54 seconds
Started	Jul 16 05:32:49 PM PDT 24
Finished	Jul 16 05:33:02 PM PDT 24
Peak memory	265244 kb
Host	smart-fe2c59cf-9d31-415d-b6a9-3bde57c5a334
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564587473 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.2564587473
Directory	/workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1820646714
Short name	T369
Test name
Test status
Simulation time	355946300 ps
CPU time	460.56 seconds
Started	Jul 16 05:10:41 PM PDT 24
Finished	Jul 16 05:18:23 PM PDT 24
Peak memory	263616 kb
Host	smart-f216556d-8b16-44ee-ac1c-5e46ec4eb795
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820646714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl _tl_intg_err.1820646714
Directory	/workspace/0.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3528428033
Short name	T228
Test name
Test status
Simulation time	722262200 ps
CPU time	909.21 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:25:37 PM PDT 24
Peak memory	263740 kb
Host	smart-9b6139a6-c3b1-4d7c-8632-67109fc9edc0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528428033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl _tl_intg_err.3528428033
Directory	/workspace/1.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.475223307
Short name	T363
Test name
Test status
Simulation time	1540487200 ps
CPU time	909.29 seconds
Started	Jul 16 05:10:59 PM PDT 24
Finished	Jul 16 05:26:09 PM PDT 24
Peak memory	263556 kb
Host	smart-e1e2698c-6507-4828-888d-79628658b64b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475223307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl _tl_intg_err.475223307
Directory	/workspace/10.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_sec_info_access.1861454076
Short name	T407
Test name
Test status
Simulation time	6952379000 ps
CPU time	72.94 seconds
Started	Jul 16 05:33:09 PM PDT 24
Finished	Jul 16 05:34:23 PM PDT 24
Peak memory	263004 kb
Host	smart-83b64933-6341-4fe7-89bf-6a379c1c68c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1861454076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.1861454076
Directory	/workspace/12.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3344506235
Short name	T330
Test name
Test status
Simulation time	5848904100 ps
CPU time	149.33 seconds
Started	Jul 16 05:33:31 PM PDT 24
Finished	Jul 16 05:36:01 PM PDT 24
Peak memory	294112 kb
Host	smart-7d5957d6-6735-4854-8fba-c04d9cdd67fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344506235 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.3344506235
Directory	/workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/27.flash_ctrl_sec_info_access.1398426738
Short name	T400
Test name
Test status
Simulation time	3095903500 ps
CPU time	70.2 seconds
Started	Jul 16 05:35:13 PM PDT 24
Finished	Jul 16 05:36:24 PM PDT 24
Peak memory	263896 kb
Host	smart-1aa4d841-4042-4853-a2c7-c3373ef70f9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398426738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.1398426738
Directory	/workspace/27.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb_redun.2324634589
Short name	T70
Test name
Test status
Simulation time	756662900 ps
CPU time	20.11 seconds
Started	Jul 16 05:29:54 PM PDT 24
Finished	Jul 16 05:30:15 PM PDT 24
Peak memory	264212 kb
Host	smart-1fe7c277-2d2f-4dae-b1a6-e4bd65395fbc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324634589 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.2324634589
Directory	/workspace/1.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_dir_rd.2778109001
Short name	T275
Test name
Test status
Simulation time	508199800 ps
CPU time	102.65 seconds
Started	Jul 16 05:29:56 PM PDT 24
Finished	Jul 16 05:31:39 PM PDT 24
Peak memory	265216 kb
Host	smart-f573cfad-fd00-4af0-8323-46ff378d0b6a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2778109001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.2778109001
Directory	/workspace/2.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/11.flash_ctrl_disable.1089621819
Short name	T378
Test name
Test status
Simulation time	44814600 ps
CPU time	21.85 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:37:17 PM PDT 24
Peak memory	273396 kb
Host	smart-d2831d59-c3cb-4763-84cf-0f7a8743fdf5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089621819 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_disable.1089621819
Directory	/workspace/11.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb_redun.55971012
Short name	T68
Test name
Test status
Simulation time	725858900 ps
CPU time	18.6 seconds
Started	Jul 16 05:30:17 PM PDT 24
Finished	Jul 16 05:30:37 PM PDT 24
Peak memory	264992 kb
Host	smart-4896ef90-ec2e-4600-9e67-8b4e60c087a4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55971012 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.55971012
Directory	/workspace/2.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_derr.3734116019
Short name	T195
Test name
Test status
Simulation time	3817726100 ps
CPU time	644.37 seconds
Started	Jul 16 05:31:47 PM PDT 24
Finished	Jul 16 05:42:32 PM PDT 24
Peak memory	335152 kb
Host	smart-f3777283-9561-4009-bb44-996f82f25812
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734116019 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_rw_derr.3734116019
Directory	/workspace/6.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1573074887
Short name	T339
Test name
Test status
Simulation time	44361000 ps
CPU time	13.24 seconds
Started	Jul 16 05:10:40 PM PDT 24
Finished	Jul 16 05:10:54 PM PDT 24
Peak memory	261244 kb
Host	smart-50afef4a-ca03-41ab-a7a7-95e3af04e03a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573074887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test. 1573074887
Directory	/workspace/12.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2431761907
Short name	T371
Test name
Test status
Simulation time	702080900 ps
CPU time	895.73 seconds
Started	Jul 16 05:10:40 PM PDT 24
Finished	Jul 16 05:25:37 PM PDT 24
Peak memory	263668 kb
Host	smart-da3e30d0-884a-439a-aed9-3d015312190e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431761907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr l_tl_intg_err.2431761907
Directory	/workspace/12.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2218428276
Short name	T221
Test name
Test status
Simulation time	674972300 ps
CPU time	894.4 seconds
Started	Jul 16 05:10:49 PM PDT 24
Finished	Jul 16 05:25:44 PM PDT 24
Peak memory	263720 kb
Host	smart-8a5913c7-ee70-44a8-80bc-2f018ed13681
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218428276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr l_tl_intg_err.2218428276
Directory	/workspace/18.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_config_regwen.2266634097
Short name	T248
Test name
Test status
Simulation time	50758800 ps
CPU time	13.79 seconds
Started	Jul 16 05:29:30 PM PDT 24
Finished	Jul 16 05:29:44 PM PDT 24
Peak memory	264900 kb
Host	smart-c7f2bcc1-ce9a-46a9-bf24-a5f6fd677f68
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266634097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .flash_ctrl_config_regwen.2266634097
Directory	/workspace/0.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/1.flash_ctrl_disable.268206002
Short name	T393
Test name
Test status
Simulation time	26019600 ps
CPU time	22.04 seconds
Started	Jul 16 05:35:02 PM PDT 24
Finished	Jul 16 05:35:25 PM PDT 24
Peak memory	273540 kb
Host	smart-0534e1f1-7a51-42b2-92f8-0488d0b6dfc8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268206002 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_disable.268206002
Directory	/workspace/1.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke.2334804377
Short name	T18
Test name
Test status
Simulation time	23103900 ps
CPU time	147.17 seconds
Started	Jul 16 05:29:56 PM PDT 24
Finished	Jul 16 05:32:24 PM PDT 24
Peak memory	277908 kb
Host	smart-03af6c59-9590-4a61-a500-b3355501be9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334804377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.2334804377
Directory	/workspace/1.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.3714712485
Short name	T359
Test name
Test status
Simulation time	65196900 ps
CPU time	28.38 seconds
Started	Jul 16 05:33:10 PM PDT 24
Finished	Jul 16 05:33:38 PM PDT 24
Peak memory	275640 kb
Host	smart-d882e2d9-d3b0-4b07-bb0a-6deaeb5d601e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714712485 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.3714712485
Directory	/workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/12.flash_ctrl_disable.4089806807
Short name	T374
Test name
Test status
Simulation time	15433100 ps
CPU time	20.36 seconds
Started	Jul 16 05:36:48 PM PDT 24
Finished	Jul 16 05:37:09 PM PDT 24
Peak memory	273592 kb
Host	smart-d5ee0087-3134-4322-9472-40a1439be2c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089806807 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_disable.4089806807
Directory	/workspace/12.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/13.flash_ctrl_disable.2592235688
Short name	T175
Test name
Test status
Simulation time	27013800 ps
CPU time	22.14 seconds
Started	Jul 16 05:36:49 PM PDT 24
Finished	Jul 16 05:37:12 PM PDT 24
Peak memory	265544 kb
Host	smart-c67ca50d-0460-43f7-a013-f33986af8439
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592235688 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_disable.2592235688
Directory	/workspace/13.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict.3351638048
Short name	T355
Test name
Test status
Simulation time	202893000 ps
CPU time	27.48 seconds
Started	Jul 16 05:33:11 PM PDT 24
Finished	Jul 16 05:33:39 PM PDT 24
Peak memory	268436 kb
Host	smart-e51b6981-c303-47a6-af80-224154f15ac6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351638048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_rw_evict.3351638048
Directory	/workspace/13.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict.4117467642
Short name	T350
Test name
Test status
Simulation time	29170600 ps
CPU time	27.63 seconds
Started	Jul 16 05:33:21 PM PDT 24
Finished	Jul 16 05:33:49 PM PDT 24
Peak memory	275592 kb
Host	smart-b05334c8-dfd4-47f3-ba0f-f6ac49dcea7c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117467642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_rw_evict.4117467642
Directory	/workspace/15.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.3273053905
Short name	T495
Test name
Test status
Simulation time	32399800 ps
CPU time	31.31 seconds
Started	Jul 16 05:36:52 PM PDT 24
Finished	Jul 16 05:37:24 PM PDT 24
Peak memory	268432 kb
Host	smart-d3fd090e-2bf4-4036-9070-517ee0a2842d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273053905 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.3273053905
Directory	/workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/18.flash_ctrl_sec_info_access.2333839336
Short name	T409
Test name
Test status
Simulation time	5738525000 ps
CPU time	69.18 seconds
Started	Jul 16 05:34:08 PM PDT 24
Finished	Jul 16 05:35:17 PM PDT 24
Peak memory	264760 kb
Host	smart-16c2b4df-53d3-42cf-9189-c5ea0d79a8a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333839336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2333839336
Directory	/workspace/18.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.4110949697
Short name	T347
Test name
Test status
Simulation time	41401600 ps
CPU time	30.94 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:37:23 PM PDT 24
Peak memory	267496 kb
Host	smart-5ac1fc81-5164-4ca3-ac62-6b99ef7c8f6e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110949697 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.4110949697
Directory	/workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/24.flash_ctrl_disable.1753272492
Short name	T377
Test name
Test status
Simulation time	27430800 ps
CPU time	22.37 seconds
Started	Jul 16 05:34:46 PM PDT 24
Finished	Jul 16 05:35:09 PM PDT 24
Peak memory	273508 kb
Host	smart-c5b31c20-a01e-48b1-99d3-a4ca9d7b168d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753272492 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_disable.1753272492
Directory	/workspace/24.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/26.flash_ctrl_disable.527393935
Short name	T382
Test name
Test status
Simulation time	139095000 ps
CPU time	20.43 seconds
Started	Jul 16 05:36:52 PM PDT 24
Finished	Jul 16 05:37:14 PM PDT 24
Peak memory	273608 kb
Host	smart-0331ebd1-ee61-4116-9c45-fe90deb87b10
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527393935 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_disable.527393935
Directory	/workspace/26.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_info_access.2028477131
Short name	T401
Test name
Test status
Simulation time	731344700 ps
CPU time	57.65 seconds
Started	Jul 16 05:36:23 PM PDT 24
Finished	Jul 16 05:37:22 PM PDT 24
Peak memory	265052 kb
Host	smart-115531fe-8318-4388-b98b-d43a115d0c6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028477131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2028477131
Directory	/workspace/3.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_info_access.2932868612
Short name	T397
Test name
Test status
Simulation time	3025245800 ps
CPU time	73.51 seconds
Started	Jul 16 05:31:25 PM PDT 24
Finished	Jul 16 05:32:40 PM PDT 24
Peak memory	264120 kb
Host	smart-2f2e930f-5d94-4db8-9914-90bb19f78f32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932868612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2932868612
Directory	/workspace/4.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/41.flash_ctrl_sec_info_access.2346274359
Short name	T410
Test name
Test status
Simulation time	3077833900 ps
CPU time	60.32 seconds
Started	Jul 16 05:36:35 PM PDT 24
Finished	Jul 16 05:37:37 PM PDT 24
Peak memory	263692 kb
Host	smart-bd0f9320-2d55-4fe1-8178-55cd8219ff33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346274359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2346274359
Directory	/workspace/41.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1601039794
Short name	T26
Test name
Test status
Simulation time	21593576800 ps
CPU time	185.9 seconds
Started	Jul 16 05:29:30 PM PDT 24
Finished	Jul 16 05:32:37 PM PDT 24
Peak memory	260028 kb
Host	smart-c452a8dc-30a2-4689-962c-62c0e4166a80
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160 1039794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.1601039794
Directory	/workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.3663498454
Short name	T156
Test name
Test status
Simulation time	320258326300 ps
CPU time	1112.7 seconds
Started	Jul 16 05:29:50 PM PDT 24
Finished	Jul 16 05:48:23 PM PDT 24
Peak memory	264456 kb
Host	smart-17d284ae-7273-4fba-95d6-d19efe4df150
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663498454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.flash_ctrl_hw_rma_reset.3663498454
Directory	/workspace/1.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.2219121597
Short name	T7
Test name
Test status
Simulation time	17264300 ps
CPU time	14.1 seconds
Started	Jul 16 05:36:34 PM PDT 24
Finished	Jul 16 05:36:49 PM PDT 24
Peak memory	261300 kb
Host	smart-42be8cb3-f12d-4217-baf5-c0df143a0128
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2219121597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.2219121597
Directory	/workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.502625722
Short name	T264
Test name
Test status
Simulation time	59528500 ps
CPU time	18.94 seconds
Started	Jul 16 05:10:27 PM PDT 24
Finished	Jul 16 05:10:47 PM PDT 24
Peak memory	263716 kb
Host	smart-eddccd66-aa6a-420b-be79-0271810a27c7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502625722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.502625722
Directory	/workspace/1.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1751660493
Short name	T262
Test name
Test status
Simulation time	921826000 ps
CPU time	387.38 seconds
Started	Jul 16 05:10:48 PM PDT 24
Finished	Jul 16 05:17:16 PM PDT 24
Peak memory	263764 kb
Host	smart-c24c81b0-02a8-49b3-837e-aa61bd2fcc99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751660493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl _tl_intg_err.1751660493
Directory	/workspace/4.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_mp.2259579304
Short name	T216
Test name
Test status
Simulation time	18929087400 ps
CPU time	2210.4 seconds
Started	Jul 16 05:32:24 PM PDT 24
Finished	Jul 16 06:09:16 PM PDT 24
Peak memory	262720 kb
Host	smart-d48a3374-3afd-4d0d-a6e6-5223d81756ea
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2259579304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.2259579304
Directory	/workspace/0.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.709828697
Short name	T197
Test name
Test status
Simulation time	237493060900 ps
CPU time	2476.22 seconds
Started	Jul 16 05:34:24 PM PDT 24
Finished	Jul 16 06:15:42 PM PDT 24
Peak memory	263932 kb
Host	smart-1857aae5-4754-47cc-9cf2-2b39e62cab20
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709828697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.flash_ctrl_host_ctrl_arb.709828697
Directory	/workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_access_after_disable.2397247971
Short name	T43
Test name
Test status
Simulation time	29888600 ps
CPU time	13.52 seconds
Started	Jul 16 05:29:56 PM PDT 24
Finished	Jul 16 05:30:10 PM PDT 24
Peak memory	265420 kb
Host	smart-27ebf31d-a89b-49c3-a666-4e163b162bdc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397247971 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.2397247971
Directory	/workspace/1.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.1583040165
Short name	T71
Test name
Test status
Simulation time	697618861200 ps
CPU time	2180.38 seconds
Started	Jul 16 05:29:49 PM PDT 24
Finished	Jul 16 06:06:10 PM PDT 24
Peak memory	264076 kb
Host	smart-91a0ff5b-f83a-4c6d-b615-043ae876b8f3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583040165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.flash_ctrl_host_ctrl_arb.1583040165
Directory	/workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3485367077
Short name	T196
Test name
Test status
Simulation time	584990536500 ps
CPU time	2263.52 seconds
Started	Jul 16 05:29:56 PM PDT 24
Finished	Jul 16 06:07:40 PM PDT 24
Peak memory	264376 kb
Host	smart-b89dbf4f-427b-4387-9683-00242a8e05ce
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485367077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.flash_ctrl_host_ctrl_arb.3485367077
Directory	/workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.1733354517
Short name	T198
Test name
Test status
Simulation time	230824494000 ps
CPU time	2491.72 seconds
Started	Jul 16 05:30:30 PM PDT 24
Finished	Jul 16 06:12:03 PM PDT 24
Peak memory	265336 kb
Host	smart-e9865510-dbf0-4ae4-a31a-0eb6d3c47180
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733354517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.flash_ctrl_host_ctrl_arb.1733354517
Directory	/workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.123056451
Short name	T1130
Test name
Test status
Simulation time	1180319600 ps
CPU time	39.55 seconds
Started	Jul 16 05:10:23 PM PDT 24
Finished	Jul 16 05:11:04 PM PDT 24
Peak memory	261044 kb
Host	smart-d2fae848-7843-4a92-a809-5a9dd9eeec94
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123056451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.flash_ctrl_csr_bit_bash.123056451
Directory	/workspace/0.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1005051140
Short name	T1248
Test name
Test status
Simulation time	52096700 ps
CPU time	26.29 seconds
Started	Jul 16 05:10:25 PM PDT 24
Finished	Jul 16 05:10:53 PM PDT 24
Peak memory	261228 kb
Host	smart-3ac0f037-61e0-436b-a24a-8b9581c555b8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005051140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_hw_reset.1005051140
Directory	/workspace/0.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.383830715
Short name	T208
Test name
Test status
Simulation time	430475100 ps
CPU time	20.36 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:10:48 PM PDT 24
Peak memory	271896 kb
Host	smart-1707af8f-7961-4902-8a3a-27897c55409a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383830715 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.383830715
Directory	/workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3081444217
Short name	T1235
Test name
Test status
Simulation time	86949400 ps
CPU time	14.37 seconds
Started	Jul 16 05:10:24 PM PDT 24
Finished	Jul 16 05:10:40 PM PDT 24
Peak memory	263696 kb
Host	smart-ecf761c8-a6d6-48fa-8098-470af18fa96e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081444217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_csr_rw.3081444217
Directory	/workspace/0.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4099319592
Short name	T1202
Test name
Test status
Simulation time	25689800 ps
CPU time	14.38 seconds
Started	Jul 16 05:10:25 PM PDT 24
Finished	Jul 16 05:10:41 PM PDT 24
Peak memory	260848 kb
Host	smart-b3d17479-bdff-4cfc-b3bf-9a01d8874887
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099319592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me m_walk.4099319592
Directory	/workspace/0.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3156689765
Short name	T1261
Test name
Test status
Simulation time	310114100 ps
CPU time	34.94 seconds
Started	Jul 16 05:10:23 PM PDT 24
Finished	Jul 16 05:10:59 PM PDT 24
Peak memory	261160 kb
Host	smart-5c62a526-2305-49ff-a0c3-17781d2744b9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156689765 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.3156689765
Directory	/workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.868042950
Short name	T1164
Test name
Test status
Simulation time	43588600 ps
CPU time	13.53 seconds
Started	Jul 16 05:10:21 PM PDT 24
Finished	Jul 16 05:10:35 PM PDT 24
Peak memory	252944 kb
Host	smart-91b19831-16c3-41df-b7ff-efe73ee5690d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868042950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.868042950
Directory	/workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3763056502
Short name	T1236
Test name
Test status
Simulation time	15758000 ps
CPU time	16.37 seconds
Started	Jul 16 05:10:23 PM PDT 24
Finished	Jul 16 05:10:40 PM PDT 24
Peak memory	253124 kb
Host	smart-398e1b62-48f8-42f0-b739-49abe7bf2538
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763056502 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.3763056502
Directory	/workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2205785936
Short name	T1218
Test name
Test status
Simulation time	30847500 ps
CPU time	15.48 seconds
Started	Jul 16 05:10:23 PM PDT 24
Finished	Jul 16 05:10:40 PM PDT 24
Peak memory	263696 kb
Host	smart-c47d16f5-bffc-4148-938c-f1afa3638e89
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205785936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.2 205785936
Directory	/workspace/0.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2703304375
Short name	T1216
Test name
Test status
Simulation time	230327700 ps
CPU time	31.72 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:10:59 PM PDT 24
Peak memory	261208 kb
Host	smart-6e710932-6e5f-49cf-a76d-2a08ca8976a5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703304375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_aliasing.2703304375
Directory	/workspace/1.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1932220022
Short name	T1158
Test name
Test status
Simulation time	3415817400 ps
CPU time	44.29 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:11:12 PM PDT 24
Peak memory	261364 kb
Host	smart-fc684967-47cd-4b3a-84df-fbc35bfa8179
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932220022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_bit_bash.1932220022
Directory	/workspace/1.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4134900896
Short name	T1201
Test name
Test status
Simulation time	49710000 ps
CPU time	30.61 seconds
Started	Jul 16 05:10:25 PM PDT 24
Finished	Jul 16 05:10:58 PM PDT 24
Peak memory	263072 kb
Host	smart-0549bf47-1370-4d69-ba22-945b9d73a910
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134900896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_hw_reset.4134900896
Directory	/workspace/1.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2992661878
Short name	T1258
Test name
Test status
Simulation time	98437500 ps
CPU time	16.42 seconds
Started	Jul 16 05:10:22 PM PDT 24
Finished	Jul 16 05:10:39 PM PDT 24
Peak memory	270484 kb
Host	smart-0cd43aec-5194-4bcb-b9f6-c763ad42e96b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992661878 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.2992661878
Directory	/workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1077461552
Short name	T1241
Test name
Test status
Simulation time	276911700 ps
CPU time	15.45 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:10:43 PM PDT 24
Peak memory	261156 kb
Host	smart-78568be2-8b5e-437e-a1f0-d9dc2cfe6896
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077461552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_csr_rw.1077461552
Directory	/workspace/1.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2124240856
Short name	T1232
Test name
Test status
Simulation time	15776700 ps
CPU time	13.85 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:10:41 PM PDT 24
Peak memory	261048 kb
Host	smart-c9213aa9-a948-40bd-a49e-62a1100b7c9c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124240856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.2 124240856
Directory	/workspace/1.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3725210722
Short name	T1126
Test name
Test status
Simulation time	17321000 ps
CPU time	14.46 seconds
Started	Jul 16 05:10:27 PM PDT 24
Finished	Jul 16 05:10:43 PM PDT 24
Peak memory	261976 kb
Host	smart-0a021a7d-136d-4e24-9431-de6cf76e8974
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725210722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_mem_partial_access.3725210722
Directory	/workspace/1.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1972514597
Short name	T1247
Test name
Test status
Simulation time	59575700 ps
CPU time	13.51 seconds
Started	Jul 16 05:10:29 PM PDT 24
Finished	Jul 16 05:10:43 PM PDT 24
Peak memory	261084 kb
Host	smart-807e979b-b4e6-4545-ada7-56fbe2b07c28
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972514597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me m_walk.1972514597
Directory	/workspace/1.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.500149986
Short name	T304
Test name
Test status
Simulation time	204489400 ps
CPU time	35.38 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:11:07 PM PDT 24
Peak memory	261400 kb
Host	smart-40b65f7b-1211-4629-8122-71a6db11248b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500149986 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.500149986
Directory	/workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2920688992
Short name	T1146
Test name
Test status
Simulation time	14585800 ps
CPU time	13.62 seconds
Started	Jul 16 05:10:23 PM PDT 24
Finished	Jul 16 05:10:37 PM PDT 24
Peak memory	252932 kb
Host	smart-e557d659-8d64-49fe-9ff1-7243bfd8caa8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920688992 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.2920688992
Directory	/workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3135644669
Short name	T1243
Test name
Test status
Simulation time	47313800 ps
CPU time	15.89 seconds
Started	Jul 16 05:10:22 PM PDT 24
Finished	Jul 16 05:10:39 PM PDT 24
Peak memory	252828 kb
Host	smart-dc285a73-49ab-4af9-8861-442c7b81f473
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135644669 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.3135644669
Directory	/workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2742425533
Short name	T300
Test name
Test status
Simulation time	62077300 ps
CPU time	15.55 seconds
Started	Jul 16 05:10:40 PM PDT 24
Finished	Jul 16 05:10:57 PM PDT 24
Peak memory	270280 kb
Host	smart-f30849da-7ee3-40fc-ac25-21cd9ec7ba1c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742425533 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.2742425533
Directory	/workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1952844031
Short name	T1160
Test name
Test status
Simulation time	21043900 ps
CPU time	14.69 seconds
Started	Jul 16 05:10:38 PM PDT 24
Finished	Jul 16 05:10:54 PM PDT 24
Peak memory	263684 kb
Host	smart-815a946e-ffeb-4af2-bb98-52043141ffb6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952844031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_csr_rw.1952844031
Directory	/workspace/10.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2053258448
Short name	T1251
Test name
Test status
Simulation time	34390000 ps
CPU time	13.58 seconds
Started	Jul 16 05:10:55 PM PDT 24
Finished	Jul 16 05:11:10 PM PDT 24
Peak memory	261220 kb
Host	smart-52434366-8f8b-4de5-bfa9-24952a24de5a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053258448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test. 2053258448
Directory	/workspace/10.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.636551586
Short name	T1134
Test name
Test status
Simulation time	36608100 ps
CPU time	17.44 seconds
Started	Jul 16 05:10:39 PM PDT 24
Finished	Jul 16 05:10:58 PM PDT 24
Peak memory	262376 kb
Host	smart-2f376e70-f166-4243-9100-35f12bd3bfa0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636551586 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.636551586
Directory	/workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2936759864
Short name	T1256
Test name
Test status
Simulation time	32799600 ps
CPU time	13.23 seconds
Started	Jul 16 05:10:55 PM PDT 24
Finished	Jul 16 05:11:10 PM PDT 24
Peak memory	253140 kb
Host	smart-bc5e7778-7250-467e-84f1-0279f2599125
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936759864 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.2936759864
Directory	/workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3131543513
Short name	T1173
Test name
Test status
Simulation time	45944200 ps
CPU time	15.73 seconds
Started	Jul 16 05:11:03 PM PDT 24
Finished	Jul 16 05:11:20 PM PDT 24
Peak memory	253140 kb
Host	smart-6db1866f-0968-4ef7-b651-5a6da0a508c9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131543513 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.3131543513
Directory	/workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3821206939
Short name	T323
Test name
Test status
Simulation time	51269700 ps
CPU time	14.9 seconds
Started	Jul 16 05:10:40 PM PDT 24
Finished	Jul 16 05:10:56 PM PDT 24
Peak memory	263676 kb
Host	smart-e5f3503f-9cb4-4042-9630-bb8db014b085
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821206939 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.3821206939
Directory	/workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2491279539
Short name	T1167
Test name
Test status
Simulation time	146424600 ps
CPU time	17.79 seconds
Started	Jul 16 05:10:58 PM PDT 24
Finished	Jul 16 05:11:17 PM PDT 24
Peak memory	263680 kb
Host	smart-1d206352-d4b0-44e1-be53-c0a1d66e4a0f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491279539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_csr_rw.2491279539
Directory	/workspace/11.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4235589519
Short name	T1203
Test name
Test status
Simulation time	30466700 ps
CPU time	13.49 seconds
Started	Jul 16 05:10:45 PM PDT 24
Finished	Jul 16 05:10:59 PM PDT 24
Peak memory	261120 kb
Host	smart-31954824-40ac-41b4-83ad-9dc069636b51
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235589519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test. 4235589519
Directory	/workspace/11.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1674624982
Short name	T1187
Test name
Test status
Simulation time	157664300 ps
CPU time	17.41 seconds
Started	Jul 16 05:10:42 PM PDT 24
Finished	Jul 16 05:11:01 PM PDT 24
Peak memory	263000 kb
Host	smart-08755736-d2f8-4fe4-9d46-a745a6c9a318
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674624982 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.1674624982
Directory	/workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1737813553
Short name	T1137
Test name
Test status
Simulation time	23436000 ps
CPU time	15.98 seconds
Started	Jul 16 05:11:00 PM PDT 24
Finished	Jul 16 05:11:17 PM PDT 24
Peak memory	252744 kb
Host	smart-39058fec-3e8b-43f1-9e44-4ae24e263837
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737813553 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.1737813553
Directory	/workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2466082137
Short name	T1161
Test name
Test status
Simulation time	29967000 ps
CPU time	15.8 seconds
Started	Jul 16 05:10:44 PM PDT 24
Finished	Jul 16 05:11:01 PM PDT 24
Peak memory	253068 kb
Host	smart-141a339d-8f52-4cd6-8193-491d14736b9d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466082137 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2466082137
Directory	/workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3467463449
Short name	T1240
Test name
Test status
Simulation time	117755400 ps
CPU time	15.85 seconds
Started	Jul 16 05:10:39 PM PDT 24
Finished	Jul 16 05:10:56 PM PDT 24
Peak memory	263708 kb
Host	smart-2ec2c10d-26c1-489f-959c-6e95e37582cf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467463449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors. 3467463449
Directory	/workspace/11.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.4246205426
Short name	T230
Test name
Test status
Simulation time	474636300 ps
CPU time	468.09 seconds
Started	Jul 16 05:10:50 PM PDT 24
Finished	Jul 16 05:18:38 PM PDT 24
Peak memory	263556 kb
Host	smart-69111e34-0d28-40e6-a42d-22cad495144b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246205426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr l_tl_intg_err.4246205426
Directory	/workspace/11.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4262121124
Short name	T226
Test name
Test status
Simulation time	179322300 ps
CPU time	20.7 seconds
Started	Jul 16 05:10:57 PM PDT 24
Finished	Jul 16 05:11:19 PM PDT 24
Peak memory	279304 kb
Host	smart-23ec39d4-4d5a-46a5-b91a-73eea30f9f09
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262121124 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.4262121124
Directory	/workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2981927685
Short name	T297
Test name
Test status
Simulation time	148746500 ps
CPU time	13.89 seconds
Started	Jul 16 05:10:57 PM PDT 24
Finished	Jul 16 05:11:12 PM PDT 24
Peak memory	263512 kb
Host	smart-912154e9-8252-4940-a84b-d26682165b3a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981927685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_csr_rw.2981927685
Directory	/workspace/12.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1444444162
Short name	T1141
Test name
Test status
Simulation time	653804800 ps
CPU time	36.08 seconds
Started	Jul 16 05:10:55 PM PDT 24
Finished	Jul 16 05:11:33 PM PDT 24
Peak memory	262412 kb
Host	smart-0d86ad5a-3d9c-496c-bdba-f58706f0c875
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444444162 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.1444444162
Directory	/workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4255838719
Short name	T1179
Test name
Test status
Simulation time	12201700 ps
CPU time	15.54 seconds
Started	Jul 16 05:10:39 PM PDT 24
Finished	Jul 16 05:10:56 PM PDT 24
Peak memory	252956 kb
Host	smart-2dd3bd5e-7f13-4f96-aa67-004af70cb7e5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255838719 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.4255838719
Directory	/workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2346999932
Short name	T1244
Test name
Test status
Simulation time	11979900 ps
CPU time	15.97 seconds
Started	Jul 16 05:10:41 PM PDT 24
Finished	Jul 16 05:10:59 PM PDT 24
Peak memory	252484 kb
Host	smart-46cf0dcb-51f5-41c1-8f15-7635326e88bb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346999932 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.2346999932
Directory	/workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3880825883
Short name	T102
Test name
Test status
Simulation time	40416500 ps
CPU time	15.93 seconds
Started	Jul 16 05:10:40 PM PDT 24
Finished	Jul 16 05:10:57 PM PDT 24
Peak memory	263676 kb
Host	smart-3a4eafe3-6643-466b-9928-7105fd3f5958
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880825883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors. 3880825883
Directory	/workspace/12.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1282838332
Short name	T1209
Test name
Test status
Simulation time	104401700 ps
CPU time	17.57 seconds
Started	Jul 16 05:10:41 PM PDT 24
Finished	Jul 16 05:11:01 PM PDT 24
Peak memory	271944 kb
Host	smart-4613b2dd-6464-4c14-bc98-bcbaae9ae2d8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282838332 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1282838332
Directory	/workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3549785382
Short name	T1175
Test name
Test status
Simulation time	134719300 ps
CPU time	17.54 seconds
Started	Jul 16 05:10:41 PM PDT 24
Finished	Jul 16 05:11:00 PM PDT 24
Peak memory	263412 kb
Host	smart-b068eb31-9d58-489a-ae91-6f95e4d53317
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549785382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 13.flash_ctrl_csr_rw.3549785382
Directory	/workspace/13.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4226256068
Short name	T1192
Test name
Test status
Simulation time	669886800 ps
CPU time	20.29 seconds
Started	Jul 16 05:11:02 PM PDT 24
Finished	Jul 16 05:11:23 PM PDT 24
Peak memory	261532 kb
Host	smart-f3dc262e-8097-417a-b3d2-93b1a9e00644
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226256068 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.4226256068
Directory	/workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2440076579
Short name	T1155
Test name
Test status
Simulation time	16535200 ps
CPU time	13.5 seconds
Started	Jul 16 05:10:53 PM PDT 24
Finished	Jul 16 05:11:08 PM PDT 24
Peak memory	252952 kb
Host	smart-7e654001-83b8-49a5-99e8-dc668300cd9a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440076579 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.2440076579
Directory	/workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1510628106
Short name	T1168
Test name
Test status
Simulation time	57996400 ps
CPU time	13.3 seconds
Started	Jul 16 05:10:59 PM PDT 24
Finished	Jul 16 05:11:14 PM PDT 24
Peak memory	253032 kb
Host	smart-87561f92-d5cf-4174-b7ab-ba29ba9ab79e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510628106 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.1510628106
Directory	/workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3152260903
Short name	T256
Test name
Test status
Simulation time	51100100 ps
CPU time	18 seconds
Started	Jul 16 05:10:58 PM PDT 24
Finished	Jul 16 05:11:17 PM PDT 24
Peak memory	263668 kb
Host	smart-344ce4e2-7ceb-4d8e-a978-dfe8864880c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152260903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors. 3152260903
Directory	/workspace/13.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3009720265
Short name	T59
Test name
Test status
Simulation time	3226036300 ps
CPU time	909.89 seconds
Started	Jul 16 05:10:41 PM PDT 24
Finished	Jul 16 05:25:53 PM PDT 24
Peak memory	263744 kb
Host	smart-0b21c9ac-e0aa-4f6a-90b2-c9990d92fd2a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009720265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr l_tl_intg_err.3009720265
Directory	/workspace/13.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.4119743305
Short name	T1260
Test name
Test status
Simulation time	181592300 ps
CPU time	17.78 seconds
Started	Jul 16 05:11:10 PM PDT 24
Finished	Jul 16 05:11:28 PM PDT 24
Peak memory	272020 kb
Host	smart-7117f6d9-c262-432d-85ac-3ccc28804ffd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119743305 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.4119743305
Directory	/workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4031303434
Short name	T1249
Test name
Test status
Simulation time	18187500 ps
CPU time	16.25 seconds
Started	Jul 16 05:11:13 PM PDT 24
Finished	Jul 16 05:11:30 PM PDT 24
Peak memory	261272 kb
Host	smart-84d8c556-4f69-4fe3-a0ce-d1fcc7cd9ffb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031303434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_csr_rw.4031303434
Directory	/workspace/14.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1860683706
Short name	T1225
Test name
Test status
Simulation time	41783600 ps
CPU time	13.61 seconds
Started	Jul 16 05:10:58 PM PDT 24
Finished	Jul 16 05:11:13 PM PDT 24
Peak memory	261132 kb
Host	smart-395af707-b431-4d49-b614-696de6890bd7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860683706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test. 1860683706
Directory	/workspace/14.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3961038412
Short name	T1122
Test name
Test status
Simulation time	159609200 ps
CPU time	17.83 seconds
Started	Jul 16 05:11:02 PM PDT 24
Finished	Jul 16 05:11:21 PM PDT 24
Peak memory	263760 kb
Host	smart-89b77b19-d97b-48c3-8c3b-669022dbb443
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961038412 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.3961038412
Directory	/workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.127036972
Short name	T1213
Test name
Test status
Simulation time	41592400 ps
CPU time	13.14 seconds
Started	Jul 16 05:11:00 PM PDT 24
Finished	Jul 16 05:11:14 PM PDT 24
Peak memory	252844 kb
Host	smart-ca44dec4-14d6-4dcc-883e-2cf9bacbb51f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127036972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.127036972
Directory	/workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2003124090
Short name	T1182
Test name
Test status
Simulation time	20825800 ps
CPU time	15.96 seconds
Started	Jul 16 05:10:59 PM PDT 24
Finished	Jul 16 05:11:16 PM PDT 24
Peak memory	253036 kb
Host	smart-07f6d174-7452-4d36-87f7-d4ab4ec64e41
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003124090 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.2003124090
Directory	/workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.772935635
Short name	T1255
Test name
Test status
Simulation time	139680200 ps
CPU time	16.58 seconds
Started	Jul 16 05:10:58 PM PDT 24
Finished	Jul 16 05:11:16 PM PDT 24
Peak memory	263676 kb
Host	smart-51ca1afa-65c2-429f-b7ce-dec13b3a158d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772935635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.772935635
Directory	/workspace/14.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2048586728
Short name	T372
Test name
Test status
Simulation time	2795972000 ps
CPU time	754.19 seconds
Started	Jul 16 05:10:38 PM PDT 24
Finished	Jul 16 05:23:13 PM PDT 24
Peak memory	263676 kb
Host	smart-c6d86045-80b2-4f40-b966-4ce02f6e2f6b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048586728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr l_tl_intg_err.2048586728
Directory	/workspace/14.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2517679917
Short name	T1250
Test name
Test status
Simulation time	105733400 ps
CPU time	17.27 seconds
Started	Jul 16 05:10:44 PM PDT 24
Finished	Jul 16 05:11:02 PM PDT 24
Peak memory	261200 kb
Host	smart-27a791d7-3a82-4d89-8687-7465847174d2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517679917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_csr_rw.2517679917
Directory	/workspace/15.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1099704500
Short name	T1211
Test name
Test status
Simulation time	15994100 ps
CPU time	13.52 seconds
Started	Jul 16 05:10:37 PM PDT 24
Finished	Jul 16 05:10:51 PM PDT 24
Peak memory	261228 kb
Host	smart-dd0407bf-d6c4-43bc-8958-005295567516
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099704500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test. 1099704500
Directory	/workspace/15.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.4042476633
Short name	T1212
Test name
Test status
Simulation time	378247800 ps
CPU time	19.74 seconds
Started	Jul 16 05:10:41 PM PDT 24
Finished	Jul 16 05:11:02 PM PDT 24
Peak memory	261144 kb
Host	smart-ed06e298-153f-4ff0-887f-5b4f704133b1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042476633 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.4042476633
Directory	/workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.4090270848
Short name	T1138
Test name
Test status
Simulation time	43280100 ps
CPU time	13.3 seconds
Started	Jul 16 05:10:40 PM PDT 24
Finished	Jul 16 05:10:54 PM PDT 24
Peak memory	252884 kb
Host	smart-459c7484-aee8-429b-ab1e-9c51041334cf
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090270848 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.4090270848
Directory	/workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1161496203
Short name	T1224
Test name
Test status
Simulation time	20767700 ps
CPU time	15.84 seconds
Started	Jul 16 05:11:05 PM PDT 24
Finished	Jul 16 05:11:23 PM PDT 24
Peak memory	252956 kb
Host	smart-c72aba63-bcd5-4fb5-8865-6eee99f5f07c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161496203 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.1161496203
Directory	/workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1073695705
Short name	T370
Test name
Test status
Simulation time	332541900 ps
CPU time	383.6 seconds
Started	Jul 16 05:10:53 PM PDT 24
Finished	Jul 16 05:17:18 PM PDT 24
Peak memory	263608 kb
Host	smart-70a2121a-79aa-4baa-a0eb-fef29a3a2267
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073695705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr l_tl_intg_err.1073695705
Directory	/workspace/15.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1706274265
Short name	T1163
Test name
Test status
Simulation time	184648000 ps
CPU time	19.04 seconds
Started	Jul 16 05:11:06 PM PDT 24
Finished	Jul 16 05:11:26 PM PDT 24
Peak memory	271544 kb
Host	smart-2e49dd00-da8f-410c-a13b-06b1056b57db
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706274265 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.1706274265
Directory	/workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.338116627
Short name	T324
Test name
Test status
Simulation time	33986600 ps
CPU time	16.88 seconds
Started	Jul 16 05:11:02 PM PDT 24
Finished	Jul 16 05:11:20 PM PDT 24
Peak memory	261176 kb
Host	smart-a01fbcce-779c-40b4-9925-3a035af2181f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338116627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.flash_ctrl_csr_rw.338116627
Directory	/workspace/16.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2550488569
Short name	T1128
Test name
Test status
Simulation time	16503100 ps
CPU time	13.62 seconds
Started	Jul 16 05:10:55 PM PDT 24
Finished	Jul 16 05:11:16 PM PDT 24
Peak memory	261220 kb
Host	smart-9b44c760-82cd-4521-9e7f-4321a0a46c00
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550488569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test. 2550488569
Directory	/workspace/16.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3564233698
Short name	T1121
Test name
Test status
Simulation time	102417900 ps
CPU time	15.29 seconds
Started	Jul 16 05:10:53 PM PDT 24
Finished	Jul 16 05:11:10 PM PDT 24
Peak memory	263688 kb
Host	smart-ebaa5878-af79-4eeb-8c65-e0f8b019afb7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564233698 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.3564233698
Directory	/workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3192555457
Short name	T1227
Test name
Test status
Simulation time	14767500 ps
CPU time	15.88 seconds
Started	Jul 16 05:10:45 PM PDT 24
Finished	Jul 16 05:11:02 PM PDT 24
Peak memory	252960 kb
Host	smart-4e4a0eb6-46ab-4284-8941-d12e1b583411
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192555457 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.3192555457
Directory	/workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1176247592
Short name	T1184
Test name
Test status
Simulation time	18783700 ps
CPU time	15.95 seconds
Started	Jul 16 05:10:55 PM PDT 24
Finished	Jul 16 05:11:12 PM PDT 24
Peak memory	253076 kb
Host	smart-99888ffa-0999-4e73-a043-45fc92c7107a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176247592 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.1176247592
Directory	/workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3152141117
Short name	T254
Test name
Test status
Simulation time	118538200 ps
CPU time	16.1 seconds
Started	Jul 16 05:10:37 PM PDT 24
Finished	Jul 16 05:10:54 PM PDT 24
Peak memory	263712 kb
Host	smart-1b3d6694-d98e-4989-8f96-b43c9b4b512f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152141117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors. 3152141117
Directory	/workspace/16.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3696286441
Short name	T367
Test name
Test status
Simulation time	1496155400 ps
CPU time	457.91 seconds
Started	Jul 16 05:10:53 PM PDT 24
Finished	Jul 16 05:18:32 PM PDT 24
Peak memory	263604 kb
Host	smart-76dad986-2443-4745-a172-39d1770f5bf7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696286441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr l_tl_intg_err.3696286441
Directory	/workspace/16.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2403889473
Short name	T1252
Test name
Test status
Simulation time	116716500 ps
CPU time	17.63 seconds
Started	Jul 16 05:10:55 PM PDT 24
Finished	Jul 16 05:11:14 PM PDT 24
Peak memory	277488 kb
Host	smart-0a942f66-f186-470d-8f27-120ef0c1093a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403889473 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.2403889473
Directory	/workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2765042815
Short name	T298
Test name
Test status
Simulation time	211815700 ps
CPU time	17.2 seconds
Started	Jul 16 05:11:01 PM PDT 24
Finished	Jul 16 05:11:20 PM PDT 24
Peak memory	263740 kb
Host	smart-9e2f3330-b147-42b3-b5f1-3b783991da5c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765042815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_csr_rw.2765042815
Directory	/workspace/17.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3667855046
Short name	T1228
Test name
Test status
Simulation time	18557800 ps
CPU time	13.53 seconds
Started	Jul 16 05:10:54 PM PDT 24
Finished	Jul 16 05:11:09 PM PDT 24
Peak memory	261152 kb
Host	smart-9a2909c4-5ce0-49c2-b0a1-59b3bad30ad3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667855046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test. 3667855046
Directory	/workspace/17.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3245043156
Short name	T1217
Test name
Test status
Simulation time	92866600 ps
CPU time	19.23 seconds
Started	Jul 16 05:11:00 PM PDT 24
Finished	Jul 16 05:11:21 PM PDT 24
Peak memory	261160 kb
Host	smart-f5db82af-a8a1-4f61-9420-08256f85486a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245043156 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.3245043156
Directory	/workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4039072692
Short name	T1254
Test name
Test status
Simulation time	43086200 ps
CPU time	15.86 seconds
Started	Jul 16 05:10:53 PM PDT 24
Finished	Jul 16 05:11:11 PM PDT 24
Peak memory	252880 kb
Host	smart-f203490c-117c-4f14-82ce-39bbd96c42e4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039072692 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.4039072692
Directory	/workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3753968723
Short name	T1123
Test name
Test status
Simulation time	44440500 ps
CPU time	15.83 seconds
Started	Jul 16 05:10:53 PM PDT 24
Finished	Jul 16 05:11:10 PM PDT 24
Peak memory	252952 kb
Host	smart-5a72b704-ef0b-487e-a33a-2353d1399c3c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753968723 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.3753968723
Directory	/workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.271163404
Short name	T257
Test name
Test status
Simulation time	56822000 ps
CPU time	20.64 seconds
Started	Jul 16 05:11:07 PM PDT 24
Finished	Jul 16 05:11:28 PM PDT 24
Peak memory	263716 kb
Host	smart-d90bd2b1-e2b0-4d43-a220-5c9329ef63d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271163404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.271163404
Directory	/workspace/17.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1383876672
Short name	T225
Test name
Test status
Simulation time	6565900800 ps
CPU time	385.96 seconds
Started	Jul 16 05:11:04 PM PDT 24
Finished	Jul 16 05:17:31 PM PDT 24
Peak memory	263732 kb
Host	smart-e9f22304-0396-44a3-a73f-d8b822e7ceeb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383876672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr l_tl_intg_err.1383876672
Directory	/workspace/17.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2878559058
Short name	T227
Test name
Test status
Simulation time	57165200 ps
CPU time	14.5 seconds
Started	Jul 16 05:11:10 PM PDT 24
Finished	Jul 16 05:11:25 PM PDT 24
Peak memory	262048 kb
Host	smart-ab4f9151-e4d6-4623-b191-b85b4d6cdba7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878559058 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.2878559058
Directory	/workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.439504422
Short name	T210
Test name
Test status
Simulation time	257777000 ps
CPU time	15.42 seconds
Started	Jul 16 05:10:51 PM PDT 24
Finished	Jul 16 05:11:08 PM PDT 24
Peak memory	261160 kb
Host	smart-b22cb68e-9f86-4996-a581-c601274d0570
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439504422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.flash_ctrl_csr_rw.439504422
Directory	/workspace/18.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.948858472
Short name	T1242
Test name
Test status
Simulation time	18468100 ps
CPU time	14.58 seconds
Started	Jul 16 05:10:55 PM PDT 24
Finished	Jul 16 05:11:11 PM PDT 24
Peak memory	261104 kb
Host	smart-0e8383fe-6bea-4b91-b7ed-991436105483
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948858472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.948858472
Directory	/workspace/18.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3292769123
Short name	T296
Test name
Test status
Simulation time	205871200 ps
CPU time	18.33 seconds
Started	Jul 16 05:11:05 PM PDT 24
Finished	Jul 16 05:11:24 PM PDT 24
Peak memory	261356 kb
Host	smart-974942d9-1529-4217-9d0f-8704d7ccc86a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292769123 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.3292769123
Directory	/workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.288157953
Short name	T1181
Test name
Test status
Simulation time	11508300 ps
CPU time	16.05 seconds
Started	Jul 16 05:10:57 PM PDT 24
Finished	Jul 16 05:11:15 PM PDT 24
Peak memory	253040 kb
Host	smart-b6eab338-b1ba-404a-98b1-4e572e84f325
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288157953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.288157953
Directory	/workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.820317752
Short name	T1153
Test name
Test status
Simulation time	19478200 ps
CPU time	13.34 seconds
Started	Jul 16 05:10:49 PM PDT 24
Finished	Jul 16 05:11:03 PM PDT 24
Peak memory	252936 kb
Host	smart-22349899-c254-4ea6-b579-85c34376ba48
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820317752 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.820317752
Directory	/workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.550578745
Short name	T224
Test name
Test status
Simulation time	78672700 ps
CPU time	16.53 seconds
Started	Jul 16 05:11:00 PM PDT 24
Finished	Jul 16 05:11:19 PM PDT 24
Peak memory	263612 kb
Host	smart-39015f3c-5bc8-44d0-88bc-b765edd66c70
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550578745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.550578745
Directory	/workspace/18.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3154826527
Short name	T1171
Test name
Test status
Simulation time	24611000 ps
CPU time	14.64 seconds
Started	Jul 16 05:10:54 PM PDT 24
Finished	Jul 16 05:11:10 PM PDT 24
Peak memory	270360 kb
Host	smart-53d16bee-af7b-4e14-acfe-e66b7b4965ae
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154826527 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.3154826527
Directory	/workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2393278951
Short name	T1229
Test name
Test status
Simulation time	158163400 ps
CPU time	16.71 seconds
Started	Jul 16 05:10:47 PM PDT 24
Finished	Jul 16 05:11:05 PM PDT 24
Peak memory	263512 kb
Host	smart-6b770af1-3c51-482c-8957-d153f0e9669a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393278951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.flash_ctrl_csr_rw.2393278951
Directory	/workspace/19.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.757122181
Short name	T327
Test name
Test status
Simulation time	50030000 ps
CPU time	13.92 seconds
Started	Jul 16 05:10:52 PM PDT 24
Finished	Jul 16 05:11:07 PM PDT 24
Peak memory	261104 kb
Host	smart-0ec5287c-91e6-45ac-adcd-8145f7572f99
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757122181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.757122181
Directory	/workspace/19.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4061305568
Short name	T1156
Test name
Test status
Simulation time	105073400 ps
CPU time	17.34 seconds
Started	Jul 16 05:11:07 PM PDT 24
Finished	Jul 16 05:11:26 PM PDT 24
Peak memory	262516 kb
Host	smart-465b586c-fa5b-4ede-a465-1eb3ed35b18a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061305568 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.4061305568
Directory	/workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1844269995
Short name	T1119
Test name
Test status
Simulation time	13271500 ps
CPU time	16.1 seconds
Started	Jul 16 05:10:50 PM PDT 24
Finished	Jul 16 05:11:06 PM PDT 24
Peak memory	252832 kb
Host	smart-22b7a927-2f74-4d0e-9334-53bfd2024325
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844269995 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.1844269995
Directory	/workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2055701095
Short name	T1147
Test name
Test status
Simulation time	11454000 ps
CPU time	16.16 seconds
Started	Jul 16 05:11:07 PM PDT 24
Finished	Jul 16 05:11:24 PM PDT 24
Peak memory	252968 kb
Host	smart-18a158c4-97ba-4460-9bbb-94b977607791
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055701095 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2055701095
Directory	/workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2407352784
Short name	T220
Test name
Test status
Simulation time	31227400 ps
CPU time	16.09 seconds
Started	Jul 16 05:10:51 PM PDT 24
Finished	Jul 16 05:11:08 PM PDT 24
Peak memory	263696 kb
Host	smart-6a25c2d1-cd1c-4f82-ad4d-76c215454a29
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407352784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors. 2407352784
Directory	/workspace/19.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.994528433
Short name	T1142
Test name
Test status
Simulation time	1718270400 ps
CPU time	54.18 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:11:22 PM PDT 24
Peak memory	261292 kb
Host	smart-9238d122-a780-4adc-a352-82761be46562
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994528433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.flash_ctrl_csr_aliasing.994528433
Directory	/workspace/2.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.193328460
Short name	T252
Test name
Test status
Simulation time	8421333100 ps
CPU time	81.47 seconds
Started	Jul 16 05:10:21 PM PDT 24
Finished	Jul 16 05:11:43 PM PDT 24
Peak memory	261392 kb
Host	smart-6244ba67-ed19-435b-9293-44a96be2cc2b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193328460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.flash_ctrl_csr_bit_bash.193328460
Directory	/workspace/2.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3134943852
Short name	T1221
Test name
Test status
Simulation time	44911700 ps
CPU time	46.89 seconds
Started	Jul 16 05:10:28 PM PDT 24
Finished	Jul 16 05:11:16 PM PDT 24
Peak memory	261188 kb
Host	smart-c4e51b03-2cf5-42f6-9ff2-1d9bf709c130
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134943852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_hw_reset.3134943852
Directory	/workspace/2.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2623283296
Short name	T1157
Test name
Test status
Simulation time	50410800 ps
CPU time	17.75 seconds
Started	Jul 16 05:10:24 PM PDT 24
Finished	Jul 16 05:10:43 PM PDT 24
Peak memory	270316 kb
Host	smart-ea548da7-400f-4e41-a13a-b9a44f2073cc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623283296 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2623283296
Directory	/workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3888583539
Short name	T1200
Test name
Test status
Simulation time	136998100 ps
CPU time	14.13 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:10:42 PM PDT 24
Peak memory	263712 kb
Host	smart-e3f6bcd9-1e40-4af2-8fa5-92c737b0d4c1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888583539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_csr_rw.3888583539
Directory	/workspace/2.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.585110994
Short name	T1159
Test name
Test status
Simulation time	17672700 ps
CPU time	14.18 seconds
Started	Jul 16 05:10:25 PM PDT 24
Finished	Jul 16 05:10:41 PM PDT 24
Peak memory	261048 kb
Host	smart-99f29a5d-45c8-4c83-83be-836c7aa2599b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585110994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.585110994
Directory	/workspace/2.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3348126290
Short name	T235
Test name
Test status
Simulation time	30941600 ps
CPU time	14.04 seconds
Started	Jul 16 05:10:27 PM PDT 24
Finished	Jul 16 05:10:42 PM PDT 24
Peak memory	262740 kb
Host	smart-9179fbb4-fef7-4b9d-9687-d4cae6d603e9
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348126290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_mem_partial_access.3348126290
Directory	/workspace/2.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4276270255
Short name	T1120
Test name
Test status
Simulation time	46674200 ps
CPU time	13.9 seconds
Started	Jul 16 05:10:24 PM PDT 24
Finished	Jul 16 05:10:40 PM PDT 24
Peak memory	261016 kb
Host	smart-982f7475-1e6a-43bc-9ef4-47286eff57a4
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276270255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me m_walk.4276270255
Directory	/workspace/2.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.804822539
Short name	T295
Test name
Test status
Simulation time	1807733300 ps
CPU time	35.12 seconds
Started	Jul 16 05:10:25 PM PDT 24
Finished	Jul 16 05:11:02 PM PDT 24
Peak memory	263272 kb
Host	smart-ecd31a0e-72e6-41cf-9816-f793907bde9b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804822539 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.804822539
Directory	/workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.224846052
Short name	T1219
Test name
Test status
Simulation time	21664800 ps
CPU time	16.02 seconds
Started	Jul 16 05:10:27 PM PDT 24
Finished	Jul 16 05:10:44 PM PDT 24
Peak memory	252956 kb
Host	smart-0a6dfebd-046b-449c-8ced-c306fe722ad8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224846052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.224846052
Directory	/workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3697071070
Short name	T1238
Test name
Test status
Simulation time	38544000 ps
CPU time	15.64 seconds
Started	Jul 16 05:10:29 PM PDT 24
Finished	Jul 16 05:10:45 PM PDT 24
Peak memory	252936 kb
Host	smart-88f97643-5b2b-4a10-bd6f-c0bb645eebe5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697071070 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.3697071070
Directory	/workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2207325388
Short name	T365
Test name
Test status
Simulation time	627889800 ps
CPU time	888.34 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:25:16 PM PDT 24
Peak memory	263744 kb
Host	smart-99d414d3-10ac-468e-a74b-7657dc5e88cb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207325388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl _tl_intg_err.2207325388
Directory	/workspace/2.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.133322511
Short name	T1140
Test name
Test status
Simulation time	16509500 ps
CPU time	13.54 seconds
Started	Jul 16 05:10:57 PM PDT 24
Finished	Jul 16 05:11:12 PM PDT 24
Peak memory	261200 kb
Host	smart-7a26edb1-9cd0-4714-8459-00e34adf314f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133322511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.133322511
Directory	/workspace/20.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.281356225
Short name	T326
Test name
Test status
Simulation time	27261100 ps
CPU time	13.57 seconds
Started	Jul 16 05:10:52 PM PDT 24
Finished	Jul 16 05:11:06 PM PDT 24
Peak memory	261012 kb
Host	smart-45665caa-2ec2-4ed2-9010-ff9e8cda03bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281356225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.281356225
Directory	/workspace/21.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1957586447
Short name	T1231
Test name
Test status
Simulation time	57177200 ps
CPU time	13.92 seconds
Started	Jul 16 05:10:56 PM PDT 24
Finished	Jul 16 05:11:11 PM PDT 24
Peak memory	261236 kb
Host	smart-42797359-9c69-4079-bcc9-c047e1a699f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957586447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test. 1957586447
Directory	/workspace/22.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.320299358
Short name	T1208
Test name
Test status
Simulation time	15905300 ps
CPU time	13.95 seconds
Started	Jul 16 05:11:03 PM PDT 24
Finished	Jul 16 05:11:18 PM PDT 24
Peak memory	260924 kb
Host	smart-f1c8e316-a04d-46a2-9d53-3c3ee17418d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320299358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.320299358
Directory	/workspace/23.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.512556805
Short name	T1172
Test name
Test status
Simulation time	16573400 ps
CPU time	14.01 seconds
Started	Jul 16 05:10:51 PM PDT 24
Finished	Jul 16 05:11:07 PM PDT 24
Peak memory	261020 kb
Host	smart-04a3ba41-f417-4b33-ad27-09e23b8ca2fe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512556805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.512556805
Directory	/workspace/24.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1504948409
Short name	T1154
Test name
Test status
Simulation time	62147800 ps
CPU time	13.42 seconds
Started	Jul 16 05:11:03 PM PDT 24
Finished	Jul 16 05:11:17 PM PDT 24
Peak memory	261108 kb
Host	smart-37574e11-23ee-4c91-b062-14353abf1391
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504948409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test. 1504948409
Directory	/workspace/25.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3040646142
Short name	T1162
Test name
Test status
Simulation time	17773300 ps
CPU time	14.49 seconds
Started	Jul 16 05:11:04 PM PDT 24
Finished	Jul 16 05:11:19 PM PDT 24
Peak memory	261080 kb
Host	smart-bea6447c-6058-4020-a47a-79ea767e0cda
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040646142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test. 3040646142
Directory	/workspace/26.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1844379542
Short name	T1148
Test name
Test status
Simulation time	25101900 ps
CPU time	13.24 seconds
Started	Jul 16 05:10:51 PM PDT 24
Finished	Jul 16 05:11:04 PM PDT 24
Peak memory	261244 kb
Host	smart-891f46ab-d4b0-44d2-9a02-28bfa35337b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844379542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test. 1844379542
Directory	/workspace/27.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2640036641
Short name	T1234
Test name
Test status
Simulation time	42239400 ps
CPU time	13.42 seconds
Started	Jul 16 05:11:05 PM PDT 24
Finished	Jul 16 05:11:19 PM PDT 24
Peak memory	261080 kb
Host	smart-2536965d-a794-4af5-a2b8-da19efef9702
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640036641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test. 2640036641
Directory	/workspace/28.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2658279125
Short name	T1139
Test name
Test status
Simulation time	15072000 ps
CPU time	14.44 seconds
Started	Jul 16 05:10:56 PM PDT 24
Finished	Jul 16 05:11:12 PM PDT 24
Peak memory	261184 kb
Host	smart-536d7970-7082-4d7b-97ec-85b6195215d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658279125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test. 2658279125
Directory	/workspace/29.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3048914900
Short name	T301
Test name
Test status
Simulation time	5442124000 ps
CPU time	42.24 seconds
Started	Jul 16 05:10:52 PM PDT 24
Finished	Jul 16 05:11:36 PM PDT 24
Peak memory	261300 kb
Host	smart-5e2cf494-e8ed-4929-b2c1-b4478b29c15d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048914900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_aliasing.3048914900
Directory	/workspace/3.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3090955928
Short name	T1145
Test name
Test status
Simulation time	4770422400 ps
CPU time	47.22 seconds
Started	Jul 16 05:11:05 PM PDT 24
Finished	Jul 16 05:11:52 PM PDT 24
Peak memory	261036 kb
Host	smart-b7a8d0cf-a485-4ef3-aca6-3128c00bed35
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090955928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_bit_bash.3090955928
Directory	/workspace/3.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2270924537
Short name	T263
Test name
Test status
Simulation time	250619600 ps
CPU time	39.13 seconds
Started	Jul 16 05:10:38 PM PDT 24
Finished	Jul 16 05:11:18 PM PDT 24
Peak memory	261216 kb
Host	smart-fe7528c5-e05b-4b84-97e1-fec9754740d8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270924537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_hw_reset.2270924537
Directory	/workspace/3.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.793566281
Short name	T1136
Test name
Test status
Simulation time	107266400 ps
CPU time	15.05 seconds
Started	Jul 16 05:10:43 PM PDT 24
Finished	Jul 16 05:10:59 PM PDT 24
Peak memory	270432 kb
Host	smart-6f8c4269-6d13-4656-98ac-68a14b7b02df
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793566281 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.793566281
Directory	/workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3235031743
Short name	T1124
Test name
Test status
Simulation time	22693500 ps
CPU time	16.54 seconds
Started	Jul 16 05:10:35 PM PDT 24
Finished	Jul 16 05:10:52 PM PDT 24
Peak memory	263724 kb
Host	smart-b9bf4eef-67a9-4418-91ae-310628480aa0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235031743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_csr_rw.3235031743
Directory	/workspace/3.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.338898653
Short name	T1245
Test name
Test status
Simulation time	42996600 ps
CPU time	13.8 seconds
Started	Jul 16 05:10:25 PM PDT 24
Finished	Jul 16 05:10:40 PM PDT 24
Peak memory	261224 kb
Host	smart-903c7859-cd08-4e46-a7c1-7782d28db9eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338898653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.338898653
Directory	/workspace/3.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3676629115
Short name	T233
Test name
Test status
Simulation time	19139800 ps
CPU time	14.25 seconds
Started	Jul 16 05:10:34 PM PDT 24
Finished	Jul 16 05:10:49 PM PDT 24
Peak memory	262672 kb
Host	smart-0d412aeb-8e66-453b-8417-fb4ccee0d8e0
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676629115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_mem_partial_access.3676629115
Directory	/workspace/3.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3963474229
Short name	T1132
Test name
Test status
Simulation time	85185900 ps
CPU time	13.44 seconds
Started	Jul 16 05:10:49 PM PDT 24
Finished	Jul 16 05:11:03 PM PDT 24
Peak memory	260992 kb
Host	smart-21ccc49d-a027-470f-ac65-b14047deef3a
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963474229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me m_walk.3963474229
Directory	/workspace/3.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1773652913
Short name	T1152
Test name
Test status
Simulation time	61485100 ps
CPU time	17.48 seconds
Started	Jul 16 05:10:48 PM PDT 24
Finished	Jul 16 05:11:06 PM PDT 24
Peak memory	261200 kb
Host	smart-bfa27771-1b42-4db6-b371-b3d4c3acc6c4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773652913 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.1773652913
Directory	/workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1477553815
Short name	T1233
Test name
Test status
Simulation time	12853800 ps
CPU time	16 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:10:43 PM PDT 24
Peak memory	253076 kb
Host	smart-9cb59090-64b5-4f84-93ce-01db4718df24
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477553815 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.1477553815
Directory	/workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3229096066
Short name	T1215
Test name
Test status
Simulation time	12157600 ps
CPU time	13.4 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:10:41 PM PDT 24
Peak memory	252872 kb
Host	smart-584f8840-f22a-481a-b243-097f1ed7f823
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229096066 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.3229096066
Directory	/workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.437722139
Short name	T261
Test name
Test status
Simulation time	218652900 ps
CPU time	19.95 seconds
Started	Jul 16 05:10:26 PM PDT 24
Finished	Jul 16 05:10:47 PM PDT 24
Peak memory	263720 kb
Host	smart-e9d0e852-b80a-4128-a0ff-d3fc79571a69
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437722139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.437722139
Directory	/workspace/3.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.701727287
Short name	T1131
Test name
Test status
Simulation time	57757700 ps
CPU time	13.67 seconds
Started	Jul 16 05:11:07 PM PDT 24
Finished	Jul 16 05:11:21 PM PDT 24
Peak memory	261208 kb
Host	smart-4d2035ab-b6ac-416f-a35f-546ca3dacdee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701727287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.701727287
Directory	/workspace/30.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1659932789
Short name	T328
Test name
Test status
Simulation time	57159400 ps
CPU time	13.57 seconds
Started	Jul 16 05:10:52 PM PDT 24
Finished	Jul 16 05:11:07 PM PDT 24
Peak memory	261076 kb
Host	smart-700fbc8c-389c-4eb4-9191-c199162bf668
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659932789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test. 1659932789
Directory	/workspace/31.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2252338072
Short name	T258
Test name
Test status
Simulation time	22758900 ps
CPU time	13.3 seconds
Started	Jul 16 05:11:05 PM PDT 24
Finished	Jul 16 05:11:19 PM PDT 24
Peak memory	261108 kb
Host	smart-12c8f813-7d8a-4703-8adf-fa86167d53a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252338072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test. 2252338072
Directory	/workspace/32.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3385351124
Short name	T1151
Test name
Test status
Simulation time	18165100 ps
CPU time	14.16 seconds
Started	Jul 16 05:11:05 PM PDT 24
Finished	Jul 16 05:11:19 PM PDT 24
Peak memory	260956 kb
Host	smart-e87c278b-0170-481a-a0a7-152f207f1d9d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385351124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test. 3385351124
Directory	/workspace/33.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2070415302
Short name	T1239
Test name
Test status
Simulation time	46951000 ps
CPU time	13.65 seconds
Started	Jul 16 05:10:52 PM PDT 24
Finished	Jul 16 05:11:07 PM PDT 24
Peak memory	261244 kb
Host	smart-cf57de2b-a18e-4265-b97e-82d1ef3decde
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070415302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test. 2070415302
Directory	/workspace/34.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3228632342
Short name	T1176
Test name
Test status
Simulation time	15764400 ps
CPU time	14.11 seconds
Started	Jul 16 05:10:52 PM PDT 24
Finished	Jul 16 05:11:07 PM PDT 24
Peak memory	260968 kb
Host	smart-495f9562-37df-43a3-b18e-50ecd7d2c7e5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228632342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test. 3228632342
Directory	/workspace/35.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.986311991
Short name	T1205
Test name
Test status
Simulation time	54535500 ps
CPU time	13.57 seconds
Started	Jul 16 05:10:53 PM PDT 24
Finished	Jul 16 05:11:08 PM PDT 24
Peak memory	261240 kb
Host	smart-6b32ccd7-8201-4949-9160-8ef036f92fb8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986311991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.986311991
Directory	/workspace/36.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2030941084
Short name	T1191
Test name
Test status
Simulation time	17042500 ps
CPU time	14.15 seconds
Started	Jul 16 05:10:52 PM PDT 24
Finished	Jul 16 05:11:07 PM PDT 24
Peak memory	261060 kb
Host	smart-ae8e3d00-d256-470f-97b1-ccdb7dad9daa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030941084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test. 2030941084
Directory	/workspace/37.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.984036460
Short name	T1206
Test name
Test status
Simulation time	22187000 ps
CPU time	13.97 seconds
Started	Jul 16 05:10:56 PM PDT 24
Finished	Jul 16 05:11:12 PM PDT 24
Peak memory	261248 kb
Host	smart-ee874141-77cd-44e7-b77b-cb2399989b37
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984036460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.984036460
Directory	/workspace/38.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.879874319
Short name	T1127
Test name
Test status
Simulation time	17184300 ps
CPU time	13.6 seconds
Started	Jul 16 05:10:55 PM PDT 24
Finished	Jul 16 05:11:10 PM PDT 24
Peak memory	261148 kb
Host	smart-e8897626-de54-46d4-a131-3b2de42fe915
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879874319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.879874319
Directory	/workspace/39.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.652966767
Short name	T1253
Test name
Test status
Simulation time	213650700 ps
CPU time	32.36 seconds
Started	Jul 16 05:10:36 PM PDT 24
Finished	Jul 16 05:11:08 PM PDT 24
Peak memory	261392 kb
Host	smart-66462139-cfed-4f56-8db0-ea8c5077e5c9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652966767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.flash_ctrl_csr_aliasing.652966767
Directory	/workspace/4.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3061939474
Short name	T1143
Test name
Test status
Simulation time	6071450900 ps
CPU time	48.05 seconds
Started	Jul 16 05:10:35 PM PDT 24
Finished	Jul 16 05:11:24 PM PDT 24
Peak memory	261520 kb
Host	smart-682b6d92-c4f8-4661-859b-7aba220ef49f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061939474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_bit_bash.3061939474
Directory	/workspace/4.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2062038796
Short name	T1195
Test name
Test status
Simulation time	124737800 ps
CPU time	38.23 seconds
Started	Jul 16 05:10:33 PM PDT 24
Finished	Jul 16 05:11:11 PM PDT 24
Peak memory	261112 kb
Host	smart-eb2a963a-3754-4306-9b9e-9ed307b13837
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062038796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_hw_reset.2062038796
Directory	/workspace/4.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1640762855
Short name	T1262
Test name
Test status
Simulation time	184677400 ps
CPU time	17.4 seconds
Started	Jul 16 05:10:54 PM PDT 24
Finished	Jul 16 05:11:13 PM PDT 24
Peak memory	263816 kb
Host	smart-4fa3b443-d81f-4274-ba5b-7235dbab75d6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640762855 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1640762855
Directory	/workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.685533923
Short name	T1198
Test name
Test status
Simulation time	206311400 ps
CPU time	14.7 seconds
Started	Jul 16 05:10:59 PM PDT 24
Finished	Jul 16 05:11:15 PM PDT 24
Peak memory	261756 kb
Host	smart-46c34b24-4467-4644-b778-18959110e5c2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685533923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_csr_rw.685533923
Directory	/workspace/4.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.676838969
Short name	T1177
Test name
Test status
Simulation time	16416400 ps
CPU time	14.14 seconds
Started	Jul 16 05:10:42 PM PDT 24
Finished	Jul 16 05:10:58 PM PDT 24
Peak memory	261036 kb
Host	smart-852e6663-59dd-4f54-8730-7a4e2917c6e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676838969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.676838969
Directory	/workspace/4.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1432047707
Short name	T236
Test name
Test status
Simulation time	33495900 ps
CPU time	13.47 seconds
Started	Jul 16 05:10:39 PM PDT 24
Finished	Jul 16 05:10:54 PM PDT 24
Peak memory	261164 kb
Host	smart-72271c18-e57f-4671-b079-7ec516bbd353
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432047707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_mem_partial_access.1432047707
Directory	/workspace/4.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.541313757
Short name	T1246
Test name
Test status
Simulation time	15953800 ps
CPU time	13.99 seconds
Started	Jul 16 05:10:41 PM PDT 24
Finished	Jul 16 05:10:57 PM PDT 24
Peak memory	260876 kb
Host	smart-c8f50a14-e599-46b8-96ab-81737fb9eb0c
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541313757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem _walk.541313757
Directory	/workspace/4.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1922578516
Short name	T303
Test name
Test status
Simulation time	229847200 ps
CPU time	15.99 seconds
Started	Jul 16 05:10:34 PM PDT 24
Finished	Jul 16 05:10:50 PM PDT 24
Peak memory	263600 kb
Host	smart-d1f0c690-e1b2-45be-ba49-7f72b96b711d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922578516 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.1922578516
Directory	/workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3769654813
Short name	T1125
Test name
Test status
Simulation time	15921900 ps
CPU time	13.36 seconds
Started	Jul 16 05:10:53 PM PDT 24
Finished	Jul 16 05:11:08 PM PDT 24
Peak memory	253012 kb
Host	smart-756fc983-1545-4782-8d9c-0b63712f9f41
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769654813 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.3769654813
Directory	/workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3915988357
Short name	T1193
Test name
Test status
Simulation time	21987100 ps
CPU time	15.98 seconds
Started	Jul 16 05:10:41 PM PDT 24
Finished	Jul 16 05:10:59 PM PDT 24
Peak memory	252960 kb
Host	smart-7c7cc582-0612-44b6-bf4c-37cdcf9fced5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915988357 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.3915988357
Directory	/workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.678930515
Short name	T267
Test name
Test status
Simulation time	54095800 ps
CPU time	16.99 seconds
Started	Jul 16 05:10:36 PM PDT 24
Finished	Jul 16 05:10:54 PM PDT 24
Peak memory	262860 kb
Host	smart-5751bd75-5b37-4949-ba4b-080c99a52043
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678930515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.678930515
Directory	/workspace/4.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3812212845
Short name	T1178
Test name
Test status
Simulation time	27029800 ps
CPU time	13.66 seconds
Started	Jul 16 05:10:57 PM PDT 24
Finished	Jul 16 05:11:12 PM PDT 24
Peak memory	261080 kb
Host	smart-37e73d0d-f33a-4580-a358-4784fae563fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812212845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test. 3812212845
Directory	/workspace/40.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3108969864
Short name	T1149
Test name
Test status
Simulation time	37087700 ps
CPU time	13.6 seconds
Started	Jul 16 05:10:55 PM PDT 24
Finished	Jul 16 05:11:10 PM PDT 24
Peak memory	261116 kb
Host	smart-b62e516b-64ea-4ff5-b097-5eb6449c5361
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108969864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test. 3108969864
Directory	/workspace/41.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3190684573
Short name	T1186
Test name
Test status
Simulation time	15885500 ps
CPU time	13.71 seconds
Started	Jul 16 05:10:55 PM PDT 24
Finished	Jul 16 05:11:10 PM PDT 24
Peak memory	261168 kb
Host	smart-3d9c2057-9390-4987-b8c4-be0d05db596b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190684573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test. 3190684573
Directory	/workspace/42.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2579848481
Short name	T1169
Test name
Test status
Simulation time	14580400 ps
CPU time	13.22 seconds
Started	Jul 16 05:11:01 PM PDT 24
Finished	Jul 16 05:11:16 PM PDT 24
Peak memory	261248 kb
Host	smart-3aa1c725-414f-41ab-bf04-31731d031541
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579848481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test. 2579848481
Directory	/workspace/43.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.306867386
Short name	T1180
Test name
Test status
Simulation time	36592300 ps
CPU time	13.7 seconds
Started	Jul 16 05:11:07 PM PDT 24
Finished	Jul 16 05:11:22 PM PDT 24
Peak memory	261168 kb
Host	smart-d40d4ad0-232d-48db-bac0-b6d36b7cb935
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306867386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.306867386
Directory	/workspace/44.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2301192255
Short name	T329
Test name
Test status
Simulation time	17710500 ps
CPU time	13.89 seconds
Started	Jul 16 05:11:02 PM PDT 24
Finished	Jul 16 05:11:17 PM PDT 24
Peak memory	261272 kb
Host	smart-d4fddcf9-51a5-4c65-8d76-2391a6b14b1c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301192255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test. 2301192255
Directory	/workspace/45.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.417518565
Short name	T1135
Test name
Test status
Simulation time	58672900 ps
CPU time	13.47 seconds
Started	Jul 16 05:11:03 PM PDT 24
Finished	Jul 16 05:11:17 PM PDT 24
Peak memory	260984 kb
Host	smart-cba09dd2-ce61-4e3e-b7ae-62d722a2e79c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417518565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.417518565
Directory	/workspace/46.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1298194184
Short name	T1165
Test name
Test status
Simulation time	42144100 ps
CPU time	14.16 seconds
Started	Jul 16 05:10:51 PM PDT 24
Finished	Jul 16 05:11:06 PM PDT 24
Peak memory	261064 kb
Host	smart-8e245921-b0ac-4a2b-ace1-5ec5a2b0caf7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298194184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test. 1298194184
Directory	/workspace/47.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1090910497
Short name	T1144
Test name
Test status
Simulation time	23996000 ps
CPU time	13.91 seconds
Started	Jul 16 05:10:52 PM PDT 24
Finished	Jul 16 05:11:07 PM PDT 24
Peak memory	261112 kb
Host	smart-4391899a-6ef9-4f9d-8dc8-b4fc7dcfa1a1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090910497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test. 1090910497
Directory	/workspace/48.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1998866137
Short name	T1204
Test name
Test status
Simulation time	16371000 ps
CPU time	13.37 seconds
Started	Jul 16 05:10:54 PM PDT 24
Finished	Jul 16 05:11:08 PM PDT 24
Peak memory	261164 kb
Host	smart-bd843599-908d-4c0e-a548-2a25475c8775
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998866137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test. 1998866137
Directory	/workspace/49.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2743755311
Short name	T1170
Test name
Test status
Simulation time	198798600 ps
CPU time	18.16 seconds
Started	Jul 16 05:10:46 PM PDT 24
Finished	Jul 16 05:11:05 PM PDT 24
Peak memory	271904 kb
Host	smart-8d2ed2d5-0cfa-4d95-b51b-16bc64ef91a5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743755311 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.2743755311
Directory	/workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2510962264
Short name	T1214
Test name
Test status
Simulation time	252307600 ps
CPU time	15.04 seconds
Started	Jul 16 05:10:47 PM PDT 24
Finished	Jul 16 05:11:03 PM PDT 24
Peak memory	263724 kb
Host	smart-e640ad16-1fd0-4193-a0c6-d3b6e4f9a228
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510962264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.flash_ctrl_csr_rw.2510962264
Directory	/workspace/5.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4078369724
Short name	T1220
Test name
Test status
Simulation time	165099400 ps
CPU time	14.07 seconds
Started	Jul 16 05:10:56 PM PDT 24
Finished	Jul 16 05:11:11 PM PDT 24
Peak memory	261100 kb
Host	smart-d4d75aa6-eca5-47ea-bd75-8e077c75c685
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078369724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.4 078369724
Directory	/workspace/5.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2423056786
Short name	T251
Test name
Test status
Simulation time	166829100 ps
CPU time	15.76 seconds
Started	Jul 16 05:10:41 PM PDT 24
Finished	Jul 16 05:10:59 PM PDT 24
Peak memory	261280 kb
Host	smart-4db2e5b5-3f03-42c4-b69c-1d93cb29ebd8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423056786 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.2423056786
Directory	/workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3945951898
Short name	T1118
Test name
Test status
Simulation time	32131300 ps
CPU time	16.44 seconds
Started	Jul 16 05:10:55 PM PDT 24
Finished	Jul 16 05:11:13 PM PDT 24
Peak memory	252840 kb
Host	smart-18337c4b-0986-4f3d-90b3-789b34d36ca7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945951898 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.3945951898
Directory	/workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.228043731
Short name	T1210
Test name
Test status
Simulation time	22305600 ps
CPU time	15.56 seconds
Started	Jul 16 05:10:40 PM PDT 24
Finished	Jul 16 05:10:57 PM PDT 24
Peak memory	252944 kb
Host	smart-4247380e-12b4-4c47-ac74-93a15c61f8a5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228043731 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.228043731
Directory	/workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1495085124
Short name	T1226
Test name
Test status
Simulation time	46183300 ps
CPU time	17.29 seconds
Started	Jul 16 05:10:52 PM PDT 24
Finished	Jul 16 05:11:11 PM PDT 24
Peak memory	263600 kb
Host	smart-c98d1c49-0357-4433-b4a9-5f147ff935a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495085124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1 495085124
Directory	/workspace/5.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2561434320
Short name	T209
Test name
Test status
Simulation time	674306400 ps
CPU time	459.74 seconds
Started	Jul 16 05:10:42 PM PDT 24
Finished	Jul 16 05:18:23 PM PDT 24
Peak memory	263724 kb
Host	smart-41c9f72e-c196-4bc5-92f0-9bd563c4564d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561434320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl _tl_intg_err.2561434320
Directory	/workspace/5.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3202176881
Short name	T299
Test name
Test status
Simulation time	62024300 ps
CPU time	17.74 seconds
Started	Jul 16 05:10:38 PM PDT 24
Finished	Jul 16 05:10:56 PM PDT 24
Peak memory	271904 kb
Host	smart-fb52b03c-a7b0-4c2a-986b-b2a73f05a8cf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202176881 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.3202176881
Directory	/workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1032673165
Short name	T1150
Test name
Test status
Simulation time	21137100 ps
CPU time	16.66 seconds
Started	Jul 16 05:10:59 PM PDT 24
Finished	Jul 16 05:11:17 PM PDT 24
Peak memory	263700 kb
Host	smart-ef1aa62b-1b78-43e2-9dc7-cb6b7799847b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032673165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 6.flash_ctrl_csr_rw.1032673165
Directory	/workspace/6.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1756622278
Short name	T1189
Test name
Test status
Simulation time	15287200 ps
CPU time	13.93 seconds
Started	Jul 16 05:10:35 PM PDT 24
Finished	Jul 16 05:10:50 PM PDT 24
Peak memory	261096 kb
Host	smart-7dbb2589-82f4-4951-843c-d00a5b8b5623
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756622278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1 756622278
Directory	/workspace/6.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1024630210
Short name	T57
Test name
Test status
Simulation time	171335800 ps
CPU time	35.29 seconds
Started	Jul 16 05:10:37 PM PDT 24
Finished	Jul 16 05:11:13 PM PDT 24
Peak memory	262436 kb
Host	smart-0893be68-3acd-4ec9-a664-f69912cd3318
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024630210 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1024630210
Directory	/workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1538810571
Short name	T1190
Test name
Test status
Simulation time	13083600 ps
CPU time	16.33 seconds
Started	Jul 16 05:10:56 PM PDT 24
Finished	Jul 16 05:11:14 PM PDT 24
Peak memory	252992 kb
Host	smart-fff5b312-bfb0-4618-9a9c-8eb275c28720
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538810571 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.1538810571
Directory	/workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.42768348
Short name	T1174
Test name
Test status
Simulation time	18145700 ps
CPU time	13.57 seconds
Started	Jul 16 05:10:37 PM PDT 24
Finished	Jul 16 05:10:51 PM PDT 24
Peak memory	252776 kb
Host	smart-942d9ded-1147-4a8c-b446-919505e96257
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42768348 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.42768348
Directory	/workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2552120689
Short name	T1230
Test name
Test status
Simulation time	37596200 ps
CPU time	16.97 seconds
Started	Jul 16 05:10:45 PM PDT 24
Finished	Jul 16 05:11:03 PM PDT 24
Peak memory	263724 kb
Host	smart-93e013fb-0c3b-4eb0-932a-df4983097c28
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552120689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2 552120689
Directory	/workspace/6.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2516501037
Short name	T368
Test name
Test status
Simulation time	1631242800 ps
CPU time	911.38 seconds
Started	Jul 16 05:10:36 PM PDT 24
Finished	Jul 16 05:25:49 PM PDT 24
Peak memory	263720 kb
Host	smart-f3922dba-3fea-463f-878e-c20193b1c40e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516501037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl _tl_intg_err.2516501037
Directory	/workspace/6.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.4279938949
Short name	T1166
Test name
Test status
Simulation time	59181600 ps
CPU time	18.38 seconds
Started	Jul 16 05:10:40 PM PDT 24
Finished	Jul 16 05:11:00 PM PDT 24
Peak memory	263716 kb
Host	smart-5ef756cf-32e8-42bc-9cf9-c23999453d4b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279938949 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.4279938949
Directory	/workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4024709311
Short name	T1207
Test name
Test status
Simulation time	19540000 ps
CPU time	14.78 seconds
Started	Jul 16 05:10:39 PM PDT 24
Finished	Jul 16 05:10:55 PM PDT 24
Peak memory	263752 kb
Host	smart-462af112-4e41-4fb9-a578-3288243cbacb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024709311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_csr_rw.4024709311
Directory	/workspace/7.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.439375589
Short name	T325
Test name
Test status
Simulation time	80683700 ps
CPU time	13.35 seconds
Started	Jul 16 05:10:38 PM PDT 24
Finished	Jul 16 05:10:52 PM PDT 24
Peak memory	261248 kb
Host	smart-91d31d93-703e-4257-a034-6427ae293d6c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439375589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.439375589
Directory	/workspace/7.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3093194291
Short name	T1183
Test name
Test status
Simulation time	1126963800 ps
CPU time	30.48 seconds
Started	Jul 16 05:10:35 PM PDT 24
Finished	Jul 16 05:11:06 PM PDT 24
Peak memory	261204 kb
Host	smart-83235e70-4e51-44fb-ad76-3588a6079f6e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093194291 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.3093194291
Directory	/workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2109583123
Short name	T1133
Test name
Test status
Simulation time	49270000 ps
CPU time	13.19 seconds
Started	Jul 16 05:10:42 PM PDT 24
Finished	Jul 16 05:10:57 PM PDT 24
Peak memory	253048 kb
Host	smart-75ce4669-da53-4d3b-a375-fb62c388e617
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109583123 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2109583123
Directory	/workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1550864321
Short name	T1223
Test name
Test status
Simulation time	120620300 ps
CPU time	16.18 seconds
Started	Jul 16 05:10:35 PM PDT 24
Finished	Jul 16 05:10:52 PM PDT 24
Peak memory	252824 kb
Host	smart-32f3cd2a-aa03-47ee-a7c2-b0ed793ddb26
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550864321 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.1550864321
Directory	/workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.234845072
Short name	T266
Test name
Test status
Simulation time	103325800 ps
CPU time	18.81 seconds
Started	Jul 16 05:10:39 PM PDT 24
Finished	Jul 16 05:10:59 PM PDT 24
Peak memory	263708 kb
Host	smart-ee019387-59f8-4d3a-8847-89a9401dfbe8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234845072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.234845072
Directory	/workspace/7.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2883340277
Short name	T364
Test name
Test status
Simulation time	2776705000 ps
CPU time	908.47 seconds
Started	Jul 16 05:10:36 PM PDT 24
Finished	Jul 16 05:25:46 PM PDT 24
Peak memory	263628 kb
Host	smart-39a74f74-8b47-4808-bcdb-0a267fe5cb09
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883340277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl _tl_intg_err.2883340277
Directory	/workspace/7.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.175346425
Short name	T1257
Test name
Test status
Simulation time	98443900 ps
CPU time	17.72 seconds
Started	Jul 16 05:10:42 PM PDT 24
Finished	Jul 16 05:11:01 PM PDT 24
Peak memory	276044 kb
Host	smart-699a44cf-dd65-4104-a72d-c38a523df05e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175346425 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.175346425
Directory	/workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.448596190
Short name	T294
Test name
Test status
Simulation time	68394900 ps
CPU time	14.9 seconds
Started	Jul 16 05:10:37 PM PDT 24
Finished	Jul 16 05:10:53 PM PDT 24
Peak memory	263740 kb
Host	smart-238531c2-3d4e-4285-ad26-63ff1daeacab
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448596190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.flash_ctrl_csr_rw.448596190
Directory	/workspace/8.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1329712191
Short name	T259
Test name
Test status
Simulation time	15324200 ps
CPU time	13.94 seconds
Started	Jul 16 05:10:39 PM PDT 24
Finished	Jul 16 05:10:54 PM PDT 24
Peak memory	261116 kb
Host	smart-8e534f88-9f15-42e3-80ba-9212d44a9f97
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329712191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1 329712191
Directory	/workspace/8.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.4254175759
Short name	T1237
Test name
Test status
Simulation time	192331000 ps
CPU time	18.28 seconds
Started	Jul 16 05:10:42 PM PDT 24
Finished	Jul 16 05:11:02 PM PDT 24
Peak memory	261220 kb
Host	smart-b1d45e48-d88d-46a5-ae50-21497468d51c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254175759 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.4254175759
Directory	/workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2107395322
Short name	T1188
Test name
Test status
Simulation time	13257400 ps
CPU time	15.98 seconds
Started	Jul 16 05:10:43 PM PDT 24
Finished	Jul 16 05:11:00 PM PDT 24
Peak memory	253044 kb
Host	smart-fb255135-5dea-4634-8780-af58c56e3f77
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107395322 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.2107395322
Directory	/workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3465959814
Short name	T1185
Test name
Test status
Simulation time	21350200 ps
CPU time	16.28 seconds
Started	Jul 16 05:10:40 PM PDT 24
Finished	Jul 16 05:10:58 PM PDT 24
Peak memory	252944 kb
Host	smart-11fad49f-8945-4efe-9c69-c5ba46e99947
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465959814 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.3465959814
Directory	/workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1453989622
Short name	T255
Test name
Test status
Simulation time	313118700 ps
CPU time	18.94 seconds
Started	Jul 16 05:10:46 PM PDT 24
Finished	Jul 16 05:11:05 PM PDT 24
Peak memory	263656 kb
Host	smart-f4f558c4-ae77-4fd5-b4b9-130b3973fea8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453989622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1 453989622
Directory	/workspace/8.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.315502599
Short name	T302
Test name
Test status
Simulation time	55774800 ps
CPU time	17.67 seconds
Started	Jul 16 05:11:03 PM PDT 24
Finished	Jul 16 05:11:22 PM PDT 24
Peak memory	275832 kb
Host	smart-e61febe7-0f60-4112-a175-fff1e9a3ff3c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315502599 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.315502599
Directory	/workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1400939472
Short name	T1259
Test name
Test status
Simulation time	93752300 ps
CPU time	14.66 seconds
Started	Jul 16 05:10:46 PM PDT 24
Finished	Jul 16 05:11:01 PM PDT 24
Peak memory	263592 kb
Host	smart-1a629268-eb97-4106-9ab4-60027abe50d3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400939472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.flash_ctrl_csr_rw.1400939472
Directory	/workspace/9.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2656454084
Short name	T1222
Test name
Test status
Simulation time	15262000 ps
CPU time	13.68 seconds
Started	Jul 16 05:11:03 PM PDT 24
Finished	Jul 16 05:11:17 PM PDT 24
Peak memory	260996 kb
Host	smart-cdb3a925-a5c0-40ed-bc10-f9af87e1973f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656454084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.2 656454084
Directory	/workspace/9.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.781657709
Short name	T1194
Test name
Test status
Simulation time	308840600 ps
CPU time	19.47 seconds
Started	Jul 16 05:10:51 PM PDT 24
Finished	Jul 16 05:11:11 PM PDT 24
Peak memory	262452 kb
Host	smart-1edc4af2-bf6f-4f32-8e3b-64666ea61e2a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781657709 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.781657709
Directory	/workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3107471297
Short name	T1197
Test name
Test status
Simulation time	11922100 ps
CPU time	15.95 seconds
Started	Jul 16 05:10:45 PM PDT 24
Finished	Jul 16 05:11:01 PM PDT 24
Peak memory	252952 kb
Host	smart-bcafbe54-6bc0-44e5-a570-b562bf7a97d7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107471297 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.3107471297
Directory	/workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2496205097
Short name	T1199
Test name
Test status
Simulation time	11179600 ps
CPU time	13.5 seconds
Started	Jul 16 05:10:44 PM PDT 24
Finished	Jul 16 05:10:58 PM PDT 24
Peak memory	252840 kb
Host	smart-e6e171ce-a9d8-443a-b23c-d376b9eb6e07
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496205097 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2496205097
Directory	/workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4196005956
Short name	T1196
Test name
Test status
Simulation time	663598600 ps
CPU time	19.16 seconds
Started	Jul 16 05:10:40 PM PDT 24
Finished	Jul 16 05:11:01 PM PDT 24
Peak memory	263724 kb
Host	smart-5a4d3e0a-d157-4ccf-b37c-8cf4ce8588fd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196005956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.4 196005956
Directory	/workspace/9.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2875084928
Short name	T366
Test name
Test status
Simulation time	490794200 ps
CPU time	386.18 seconds
Started	Jul 16 05:11:10 PM PDT 24
Finished	Jul 16 05:17:37 PM PDT 24
Peak memory	263764 kb
Host	smart-cda49c35-6b87-404c-8d22-49804f13abdc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875084928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl _tl_intg_err.2875084928
Directory	/workspace/9.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_alert_test.1120213603
Short name	T87
Test name
Test status
Simulation time	38136100 ps
CPU time	13.62 seconds
Started	Jul 16 05:29:48 PM PDT 24
Finished	Jul 16 05:30:02 PM PDT 24
Peak memory	258308 kb
Host	smart-5b10133b-b416-4384-a301-ab384369fbc5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120213603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.1 120213603
Directory	/workspace/0.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_connect.3594105206
Short name	T558
Test name
Test status
Simulation time	199989100 ps
CPU time	16.11 seconds
Started	Jul 16 05:36:44 PM PDT 24
Finished	Jul 16 05:37:01 PM PDT 24
Peak memory	274944 kb
Host	smart-7501cb40-36bf-4047-9751-b4d5eac1779f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594105206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.3594105206
Directory	/workspace/0.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/0.flash_ctrl_disable.2524302352
Short name	T952
Test name
Test status
Simulation time	62972700 ps
CPU time	22.26 seconds
Started	Jul 16 05:29:44 PM PDT 24
Finished	Jul 16 05:30:07 PM PDT 24
Peak memory	265600 kb
Host	smart-c4dcc8de-1fbf-4f99-8b08-d6ec8134c78f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524302352 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_disable.2524302352
Directory	/workspace/0.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_erase_suspend.447783494
Short name	T806
Test name
Test status
Simulation time	5615580100 ps
CPU time	453.83 seconds
Started	Jul 16 05:29:21 PM PDT 24
Finished	Jul 16 05:36:55 PM PDT 24
Peak memory	263600 kb
Host	smart-df7582e1-60b6-44d8-ba4e-fbe6b19c4322
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=447783494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.447783494
Directory	/workspace/0.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_type.3571779290
Short name	T1043
Test name
Test status
Simulation time	1424750400 ps
CPU time	2261.85 seconds
Started	Jul 16 05:34:24 PM PDT 24
Finished	Jul 16 06:12:08 PM PDT 24
Peak memory	261988 kb
Host	smart-40ec741b-671c-4b0e-89a2-a16f8306d356
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571779290 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.3571779290
Directory	/workspace/0.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_win.2173252594
Short name	T921
Test name
Test status
Simulation time	792731600 ps
CPU time	961.38 seconds
Started	Jul 16 05:29:28 PM PDT 24
Finished	Jul 16 05:45:30 PM PDT 24
Peak memory	273424 kb
Host	smart-bd397b0e-d3e1-4938-8cc7-53cf3229e43a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173252594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.2173252594
Directory	/workspace/0.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fetch_code.881238805
Short name	T950
Test name
Test status
Simulation time	143196500 ps
CPU time	25.72 seconds
Started	Jul 16 05:29:25 PM PDT 24
Finished	Jul 16 05:29:52 PM PDT 24
Peak memory	263520 kb
Host	smart-8d3b75cd-8eb2-4c20-b4b3-83dc9c823968
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881238805 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.881238805
Directory	/workspace/0.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fs_sup.1551733280
Short name	T830
Test name
Test status
Simulation time	815266200 ps
CPU time	39.7 seconds
Started	Jul 16 05:29:29 PM PDT 24
Finished	Jul 16 05:30:09 PM PDT 24
Peak memory	262956 kb
Host	smart-0ba5bcf8-2b3e-4542-80cd-f000c477d2b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551733280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.flash_ctrl_fs_sup.1551733280
Directory	/workspace/0.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/0.flash_ctrl_full_mem_access.457883966
Short name	T134
Test name
Test status
Simulation time	325734326300 ps
CPU time	4144.72 seconds
Started	Jul 16 05:29:20 PM PDT 24
Finished	Jul 16 06:38:26 PM PDT 24
Peak memory	264168 kb
Host	smart-e11fa8b0-46db-4e68-b6aa-235d30df5d82
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457883966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct rl_full_mem_access.457883966
Directory	/workspace/0.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_addr_infection.2059120758
Short name	T770
Test name
Test status
Simulation time	94803100 ps
CPU time	28.18 seconds
Started	Jul 16 05:29:42 PM PDT 24
Finished	Jul 16 05:30:10 PM PDT 24
Peak memory	275624 kb
Host	smart-70b18aa1-b74d-49a7-a385-d013af2b2c38
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059120758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_host_addr_infection.2059120758
Directory	/workspace/0.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_dir_rd.1907936306
Short name	T698
Test name
Test status
Simulation time	99234300 ps
CPU time	90.54 seconds
Started	Jul 16 05:29:22 PM PDT 24
Finished	Jul 16 05:30:54 PM PDT 24
Peak memory	265428 kb
Host	smart-30238c90-9f86-4cf9-9742-e15867cb6707
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1907936306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.1907936306
Directory	/workspace/0.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3752316792
Short name	T799
Test name
Test status
Simulation time	10042875900 ps
CPU time	49.17 seconds
Started	Jul 16 05:34:27 PM PDT 24
Finished	Jul 16 05:35:18 PM PDT 24
Peak memory	277976 kb
Host	smart-66bbdcd6-4c97-4ce4-be76-bed4296ff1ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752316792 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.3752316792
Directory	/workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.2355781792
Short name	T1040
Test name
Test status
Simulation time	48568400 ps
CPU time	13.46 seconds
Started	Jul 16 05:29:50 PM PDT 24
Finished	Jul 16 05:30:03 PM PDT 24
Peak memory	258344 kb
Host	smart-8e9fa91f-7291-4856-abcf-551d1a1a5a68
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355781792 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.2355781792
Directory	/workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma.2431430566
Short name	T996
Test name
Test status
Simulation time	142820458600 ps
CPU time	2063.42 seconds
Started	Jul 16 05:29:20 PM PDT 24
Finished	Jul 16 06:03:44 PM PDT 24
Peak memory	260208 kb
Host	smart-8eccb004-9238-4fed-913b-8ef41c0f04b3
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431430566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.flash_ctrl_hw_rma.2431430566
Directory	/workspace/0.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1301875336
Short name	T659
Test name
Test status
Simulation time	60133580600 ps
CPU time	855.08 seconds
Started	Jul 16 05:29:22 PM PDT 24
Finished	Jul 16 05:43:38 PM PDT 24
Peak memory	264244 kb
Host	smart-508d2a5a-8e9a-4b28-b17a-daecd1dbbef7
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301875336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.flash_ctrl_hw_rma_reset.1301875336
Directory	/workspace/0.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_sec_otp.1779998129
Short name	T984
Test name
Test status
Simulation time	3510235000 ps
CPU time	202.36 seconds
Started	Jul 16 05:36:24 PM PDT 24
Finished	Jul 16 05:39:47 PM PDT 24
Peak memory	260928 kb
Host	smart-cec50400-7794-42dc-8641-5da0f12a3da4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779998129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h w_sec_otp.1779998129
Directory	/workspace/0.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_integrity.1231172516
Short name	T740
Test name
Test status
Simulation time	37669150500 ps
CPU time	686.82 seconds
Started	Jul 16 05:29:44 PM PDT 24
Finished	Jul 16 05:41:11 PM PDT 24
Peak memory	335608 kb
Host	smart-1afd30cb-9b97-42ac-aaf6-9044565099b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231172516 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_integrity.1231172516
Directory	/workspace/0.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd.2702485702
Short name	T362
Test name
Test status
Simulation time	3346891900 ps
CPU time	157 seconds
Started	Jul 16 05:31:21 PM PDT 24
Finished	Jul 16 05:33:59 PM PDT 24
Peak memory	294012 kb
Host	smart-de1893c8-ef6e-4b62-9630-2f557bb39098
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702485702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_intr_rd.2702485702
Directory	/workspace/0.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2862755915
Short name	T334
Test name
Test status
Simulation time	48204056900 ps
CPU time	309.66 seconds
Started	Jul 16 05:29:44 PM PDT 24
Finished	Jul 16 05:34:54 PM PDT 24
Peak memory	292020 kb
Host	smart-99e7b30c-2bdf-47d9-8222-f2d837573023
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862755915 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.2862755915
Directory	/workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr.1413100307
Short name	T785
Test name
Test status
Simulation time	19499613700 ps
CPU time	60.79 seconds
Started	Jul 16 05:29:29 PM PDT 24
Finished	Jul 16 05:30:31 PM PDT 24
Peak memory	260084 kb
Host	smart-ffaee8ad-d9a8-4166-8fcb-0b1297092a5f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413100307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_intr_wr.1413100307
Directory	/workspace/0.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_invalid_op.484527359
Short name	T623
Test name
Test status
Simulation time	1699734200 ps
CPU time	66.76 seconds
Started	Jul 16 05:34:27 PM PDT 24
Finished	Jul 16 05:35:35 PM PDT 24
Peak memory	262976 kb
Host	smart-62d7a2cf-30fd-4049-8823-d253a651a218
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484527359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.484527359
Directory	/workspace/0.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1185114410
Short name	T290
Test name
Test status
Simulation time	64286000 ps
CPU time	13.16 seconds
Started	Jul 16 05:29:41 PM PDT 24
Finished	Jul 16 05:29:55 PM PDT 24
Peak memory	264868 kb
Host	smart-6a43c901-087a-482c-b81d-c89a87e52ef6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185114410 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1185114410
Directory	/workspace/0.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mid_op_rst.782207959
Short name	T187
Test name
Test status
Simulation time	3748739400 ps
CPU time	71.13 seconds
Started	Jul 16 05:29:29 PM PDT 24
Finished	Jul 16 05:30:40 PM PDT 24
Peak memory	260572 kb
Host	smart-2583a982-d604-42ed-bfed-64f3ef3d40fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782207959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.782207959
Directory	/workspace/0.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mp_regions.3614807241
Short name	T1015
Test name
Test status
Simulation time	191638719000 ps
CPU time	1162.29 seconds
Started	Jul 16 05:34:17 PM PDT 24
Finished	Jul 16 05:53:40 PM PDT 24
Peak memory	274576 kb
Host	smart-ec5a9a05-5af6-4883-bd9d-d932bb6e282a
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614807241 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.3614807241
Directory	/workspace/0.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/0.flash_ctrl_otp_reset.1522776194
Short name	T491
Test name
Test status
Simulation time	81876300 ps
CPU time	109.69 seconds
Started	Jul 16 05:29:22 PM PDT 24
Finished	Jul 16 05:31:13 PM PDT 24
Peak memory	260152 kb
Host	smart-4cda25ec-93d2-4de0-a1ef-a3e12cd8e4fd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522776194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot p_reset.1522776194
Directory	/workspace/0.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb.1585421616
Short name	T1094
Test name
Test status
Simulation time	918337300 ps
CPU time	419.1 seconds
Started	Jul 16 05:29:22 PM PDT 24
Finished	Jul 16 05:36:22 PM PDT 24
Peak memory	263148 kb
Host	smart-ece9830f-9cb2-4487-8ef9-d325a777e048
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1585421616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.1585421616
Directory	/workspace/0.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.2230634615
Short name	T213
Test name
Test status
Simulation time	91103100 ps
CPU time	14.18 seconds
Started	Jul 16 05:29:44 PM PDT 24
Finished	Jul 16 05:29:59 PM PDT 24
Peak memory	262816 kb
Host	smart-6b695c38-83af-4d57-b34f-cf9df07a5346
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230634615 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2230634615
Directory	/workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_prog_reset.177395618
Short name	T422
Test name
Test status
Simulation time	18450200 ps
CPU time	13.75 seconds
Started	Jul 16 05:29:30 PM PDT 24
Finished	Jul 16 05:29:45 PM PDT 24
Peak memory	265336 kb
Host	smart-21ef27e0-3ad2-4925-8f87-861786773888
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177395618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.flash_ctrl_prog_reset.177395618
Directory	/workspace/0.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rand_ops.240704350
Short name	T783
Test name
Test status
Simulation time	421099600 ps
CPU time	207.54 seconds
Started	Jul 16 05:29:23 PM PDT 24
Finished	Jul 16 05:32:51 PM PDT 24
Peak memory	279684 kb
Host	smart-a6ada6c4-1b8b-4d5b-a392-ce0c9d406150
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240704350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.240704350
Directory	/workspace/0.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.4202841044
Short name	T1113
Test name
Test status
Simulation time	184314100 ps
CPU time	99.67 seconds
Started	Jul 16 05:34:24 PM PDT 24
Finished	Jul 16 05:36:05 PM PDT 24
Peak memory	262668 kb
Host	smart-14194cd4-6ce8-491d-86c0-5f9c938de31e
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4202841044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.4202841044
Directory	/workspace/0.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_intg.1980384764
Short name	T340
Test name
Test status
Simulation time	823091200 ps
CPU time	32.27 seconds
Started	Jul 16 05:29:35 PM PDT 24
Finished	Jul 16 05:30:07 PM PDT 24
Peak memory	275680 kb
Host	smart-eb63fd3c-d915-4852-b12e-b0be1f03d2ec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980384764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.flash_ctrl_rd_intg.1980384764
Directory	/workspace/0.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_ooo.4117640180
Short name	T527
Test name
Test status
Simulation time	106057900 ps
CPU time	43.75 seconds
Started	Jul 16 05:29:43 PM PDT 24
Finished	Jul 16 05:30:27 PM PDT 24
Peak memory	275852 kb
Host	smart-8247907d-b8db-4bb4-8200-e5d63aac6a1b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117640180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_rd_ooo.4117640180
Directory	/workspace/0.flash_ctrl_rd_ooo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_re_evict.3827733810
Short name	T543
Test name
Test status
Simulation time	105649900 ps
CPU time	31.16 seconds
Started	Jul 16 05:29:44 PM PDT 24
Finished	Jul 16 05:30:16 PM PDT 24
Peak memory	268512 kb
Host	smart-ddd8c6cc-7287-45b7-86d4-b86c4eb51f61
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827733810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_re_evict.3827733810
Directory	/workspace/0.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep.564336231
Short name	T472
Test name
Test status
Simulation time	25025700 ps
CPU time	13.92 seconds
Started	Jul 16 05:34:24 PM PDT 24
Finished	Jul 16 05:34:39 PM PDT 24
Peak memory	258740 kb
Host	smart-e033f9bb-c25d-46a0-af5c-4b2218ca8a4b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=564336231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep. 564336231
Directory	/workspace/0.flash_ctrl_read_word_sweep/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.208746331
Short name	T456
Test name
Test status
Simulation time	34271700 ps
CPU time	22.49 seconds
Started	Jul 16 05:29:30 PM PDT 24
Finished	Jul 16 05:29:53 PM PDT 24
Peak memory	265472 kb
Host	smart-b6feb1e6-b2d6-48dc-a068-d7371f65ba2c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208746331 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.208746331
Directory	/workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.480611922
Short name	T1029
Test name
Test status
Simulation time	46765600 ps
CPU time	22.97 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:37:26 PM PDT 24
Peak memory	265412 kb
Host	smart-0340ba7f-5ba5-44a1-a0a9-03b3599d693e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480611922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_read_word_sweep_serr.480611922
Directory	/workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro.3949232336
Short name	T201
Test name
Test status
Simulation time	2042291300 ps
CPU time	105.9 seconds
Started	Jul 16 05:29:44 PM PDT 24
Finished	Jul 16 05:31:30 PM PDT 24
Peak memory	291464 kb
Host	smart-c8e37cd4-bd21-4825-b699-2c4741341228
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949232336 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_ro.3949232336
Directory	/workspace/0.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_derr.2995803688
Short name	T948
Test name
Test status
Simulation time	9044586300 ps
CPU time	177.86 seconds
Started	Jul 16 05:31:21 PM PDT 24
Finished	Jul 16 05:34:20 PM PDT 24
Peak memory	282764 kb
Host	smart-827a819f-294c-41ae-b209-dc293eeb1c74
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2995803688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.2995803688
Directory	/workspace/0.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_serr.3698852131
Short name	T903
Test name
Test status
Simulation time	618846600 ps
CPU time	119.5 seconds
Started	Jul 16 05:29:27 PM PDT 24
Finished	Jul 16 05:31:27 PM PDT 24
Peak memory	281792 kb
Host	smart-8f0a88da-5af2-4242-b516-273207d7c591
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698852131 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.3698852131
Directory	/workspace/0.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw.2108479100
Short name	T1053
Test name
Test status
Simulation time	6441174200 ps
CPU time	574.72 seconds
Started	Jul 16 05:29:32 PM PDT 24
Finished	Jul 16 05:39:07 PM PDT 24
Peak memory	314692 kb
Host	smart-cb3ed192-0d81-4c49-8e0a-ba6f4695c0f2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108479100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.flash_ctrl_rw.2108479100
Directory	/workspace/0.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.468812195
Short name	T352
Test name
Test status
Simulation time	68264400 ps
CPU time	27.91 seconds
Started	Jul 16 05:29:26 PM PDT 24
Finished	Jul 16 05:29:54 PM PDT 24
Peak memory	268616 kb
Host	smart-f8c5b74d-a9ab-4658-a09d-b3e85f417913
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468812195 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.468812195
Directory	/workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_address.3822372866
Short name	T1064
Test name
Test status
Simulation time	1119680900 ps
CPU time	107.92 seconds
Started	Jul 16 05:29:29 PM PDT 24
Finished	Jul 16 05:31:17 PM PDT 24
Peak memory	265388 kb
Host	smart-a49bd373-f051-4090-846b-d62c2d95541e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822372866 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_serr_address.3822372866
Directory	/workspace/0.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_counter.2379647915
Short name	T733
Test name
Test status
Simulation time	1044860300 ps
CPU time	46.13 seconds
Started	Jul 16 05:36:51 PM PDT 24
Finished	Jul 16 05:37:38 PM PDT 24
Peak memory	273900 kb
Host	smart-f00d32db-67fb-4ff2-a9d5-860137453a05
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379647915 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_serr_counter.2379647915
Directory	/workspace/0.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke.2548629696
Short name	T448
Test name
Test status
Simulation time	20168400 ps
CPU time	49.49 seconds
Started	Jul 16 05:34:27 PM PDT 24
Finished	Jul 16 05:35:18 PM PDT 24
Peak memory	271244 kb
Host	smart-d49968c3-4a05-475c-9c43-8cac34ec1f5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2548629696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2548629696
Directory	/workspace/0.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke_hw.1008626263
Short name	T619
Test name
Test status
Simulation time	13081500 ps
CPU time	23.6 seconds
Started	Jul 16 05:34:24 PM PDT 24
Finished	Jul 16 05:34:49 PM PDT 24
Peak memory	259548 kb
Host	smart-230dfde9-d645-4f9d-83d6-e219ce1e167d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008626263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1008626263
Directory	/workspace/0.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_stress_all.2669504738
Short name	T485
Test name
Test status
Simulation time	532146100 ps
CPU time	1142.74 seconds
Started	Jul 16 05:29:28 PM PDT 24
Finished	Jul 16 05:48:31 PM PDT 24
Peak memory	286796 kb
Host	smart-775d515c-320d-4e5f-9255-2c159a24ad80
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669504738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres s_all.2669504738
Directory	/workspace/0.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sw_op.1186031030
Short name	T902
Test name
Test status
Simulation time	22959600 ps
CPU time	24.51 seconds
Started	Jul 16 05:29:20 PM PDT 24
Finished	Jul 16 05:29:45 PM PDT 24
Peak memory	259660 kb
Host	smart-079e87ca-09dd-44d3-8f65-9b7e627ecbbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186031030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1186031030
Directory	/workspace/0.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wo.3051013333
Short name	T440
Test name
Test status
Simulation time	7941088700 ps
CPU time	192.25 seconds
Started	Jul 16 05:34:28 PM PDT 24
Finished	Jul 16 05:37:41 PM PDT 24
Peak memory	259948 kb
Host	smart-8210ef4b-0dcb-424c-9a61-2ce9d2d6ed2e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051013333 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.flash_ctrl_wo.3051013333
Directory	/workspace/0.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_write_word_sweep.2839673321
Short name	T736
Test name
Test status
Simulation time	143709700 ps
CPU time	15.32 seconds
Started	Jul 16 05:29:30 PM PDT 24
Finished	Jul 16 05:29:46 PM PDT 24
Peak memory	258960 kb
Host	smart-567b84c2-50ef-476e-88d8-cf83ef407fdd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2839673321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe ep.2839673321
Directory	/workspace/0.flash_ctrl_write_word_sweep/latest

Test location	/workspace/coverage/default/1.flash_ctrl_alert_test.1436479746
Short name	T633
Test name
Test status
Simulation time	47516800 ps
CPU time	13.78 seconds
Started	Jul 16 05:29:55 PM PDT 24
Finished	Jul 16 05:30:10 PM PDT 24
Peak memory	265204 kb
Host	smart-5295b6a5-573d-4c87-9395-95ca71be3365
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436479746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.1 436479746
Directory	/workspace/1.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.flash_ctrl_config_regwen.1761663935
Short name	T373
Test name
Test status
Simulation time	19556700 ps
CPU time	14.03 seconds
Started	Jul 16 05:29:55 PM PDT 24
Finished	Jul 16 05:30:10 PM PDT 24
Peak memory	264900 kb
Host	smart-8b9bc15d-41db-4ca2-a644-4759d10a1793
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761663935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .flash_ctrl_config_regwen.1761663935
Directory	/workspace/1.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/1.flash_ctrl_connect.3201769685
Short name	T510
Test name
Test status
Simulation time	16537700 ps
CPU time	15.71 seconds
Started	Jul 16 05:30:03 PM PDT 24
Finished	Jul 16 05:30:19 PM PDT 24
Peak memory	284360 kb
Host	smart-da383a93-5582-4195-9cdd-299c51787127
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3201769685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3201769685
Directory	/workspace/1.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/1.flash_ctrl_erase_suspend.1924833367
Short name	T1026
Test name
Test status
Simulation time	2051510700 ps
CPU time	387.72 seconds
Started	Jul 16 05:29:50 PM PDT 24
Finished	Jul 16 05:36:18 PM PDT 24
Peak memory	263352 kb
Host	smart-cebbce7b-d808-4432-a22d-a1187506def3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1924833367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.1924833367
Directory	/workspace/1.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_mp.285671809
Short name	T217
Test name
Test status
Simulation time	5300987100 ps
CPU time	2247.66 seconds
Started	Jul 16 05:29:39 PM PDT 24
Finished	Jul 16 06:07:08 PM PDT 24
Peak memory	264960 kb
Host	smart-becb59db-51b9-43e2-bae6-8d33a316fefa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=285671809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.285671809
Directory	/workspace/1.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_type.3296244686
Short name	T794
Test name
Test status
Simulation time	2254964600 ps
CPU time	1853.06 seconds
Started	Jul 16 05:29:50 PM PDT 24
Finished	Jul 16 06:00:43 PM PDT 24
Peak memory	265116 kb
Host	smart-a9edf465-10a9-4338-a9c7-0910e865d023
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296244686 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.3296244686
Directory	/workspace/1.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_win.592123544
Short name	T1038
Test name
Test status
Simulation time	1329905000 ps
CPU time	839.77 seconds
Started	Jul 16 05:29:47 PM PDT 24
Finished	Jul 16 05:43:47 PM PDT 24
Peak memory	273428 kb
Host	smart-a3194040-18e7-4bc9-ae0b-f2eb8257c451
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592123544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.592123544
Directory	/workspace/1.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fetch_code.2068992032
Short name	T46
Test name
Test status
Simulation time	651556700 ps
CPU time	23.19 seconds
Started	Jul 16 05:29:40 PM PDT 24
Finished	Jul 16 05:30:03 PM PDT 24
Peak memory	262488 kb
Host	smart-adfbe0ef-e6be-467d-a11d-4af95e284e09
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068992032 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.2068992032
Directory	/workspace/1.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fs_sup.465883023
Short name	T993
Test name
Test status
Simulation time	1435460100 ps
CPU time	39.58 seconds
Started	Jul 16 05:33:22 PM PDT 24
Finished	Jul 16 05:34:02 PM PDT 24
Peak memory	265360 kb
Host	smart-bb751680-077d-42a0-a30d-dc038d6a10c6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465883023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_fs_sup.465883023
Directory	/workspace/1.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/1.flash_ctrl_full_mem_access.416110899
Short name	T56
Test name
Test status
Simulation time	189927780400 ps
CPU time	2951 seconds
Started	Jul 16 05:29:47 PM PDT 24
Finished	Jul 16 06:18:58 PM PDT 24
Peak memory	265024 kb
Host	smart-e73e304c-4401-40d3-9cd4-c0617aff6688
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416110899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct rl_full_mem_access.416110899
Directory	/workspace/1.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_addr_infection.463548495
Short name	T565
Test name
Test status
Simulation time	38988400 ps
CPU time	29.82 seconds
Started	Jul 16 05:29:56 PM PDT 24
Finished	Jul 16 05:30:26 PM PDT 24
Peak memory	275580 kb
Host	smart-45b66991-b851-4ad5-bbfd-70d5858e9ae3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463548495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_host_addr_infection.463548495
Directory	/workspace/1.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_dir_rd.352424625
Short name	T1072
Test name
Test status
Simulation time	160045200 ps
CPU time	70.08 seconds
Started	Jul 16 05:29:39 PM PDT 24
Finished	Jul 16 05:30:50 PM PDT 24
Peak memory	262668 kb
Host	smart-26c5decf-4804-4139-a8fd-0b678c8f375b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=352424625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.352424625
Directory	/workspace/1.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma.1499834888
Short name	T11
Test name
Test status
Simulation time	334253028700 ps
CPU time	2173.39 seconds
Started	Jul 16 05:29:41 PM PDT 24
Finished	Jul 16 06:05:55 PM PDT 24
Peak memory	265060 kb
Host	smart-2413ad30-c6ec-458e-a5ae-d69e5b903cf5
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499834888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.flash_ctrl_hw_rma.1499834888
Directory	/workspace/1.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_sec_otp.827327180
Short name	T1099
Test name
Test status
Simulation time	9069101500 ps
CPU time	128.03 seconds
Started	Jul 16 05:29:49 PM PDT 24
Finished	Jul 16 05:31:57 PM PDT 24
Peak memory	259876 kb
Host	smart-9a43ccb5-eec3-4b37-9deb-7efe58e1c956
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827327180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw _sec_otp.827327180
Directory	/workspace/1.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_integrity.710729904
Short name	T237
Test name
Test status
Simulation time	4022516700 ps
CPU time	598.2 seconds
Started	Jul 16 05:29:47 PM PDT 24
Finished	Jul 16 05:39:46 PM PDT 24
Peak memory	328276 kb
Host	smart-b16abb76-da8a-4984-8d24-3143a7c63970
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710729904 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.flash_ctrl_integrity.710729904
Directory	/workspace/1.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd.2501436518
Short name	T333
Test name
Test status
Simulation time	3023501400 ps
CPU time	141.1 seconds
Started	Jul 16 05:34:21 PM PDT 24
Finished	Jul 16 05:36:43 PM PDT 24
Peak memory	291364 kb
Host	smart-5084a2be-f1c7-4016-a21f-859df837b9b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501436518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_intr_rd.2501436518
Directory	/workspace/1.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.381352958
Short name	T82
Test name
Test status
Simulation time	70222807600 ps
CPU time	426.79 seconds
Started	Jul 16 05:30:03 PM PDT 24
Finished	Jul 16 05:37:11 PM PDT 24
Peak memory	293004 kb
Host	smart-033f8189-4827-40e3-bd6f-95aeeb6a4b0e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381352958 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.381352958
Directory	/workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr.751143290
Short name	T1069
Test name
Test status
Simulation time	2317485600 ps
CPU time	65.59 seconds
Started	Jul 16 05:29:55 PM PDT 24
Finished	Jul 16 05:31:02 PM PDT 24
Peak memory	265172 kb
Host	smart-c4b8c7a4-974f-4e45-b713-1abd12169e36
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751143290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.flash_ctrl_intr_wr.751143290
Directory	/workspace/1.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1142663505
Short name	T642
Test name
Test status
Simulation time	215102266300 ps
CPU time	221.13 seconds
Started	Jul 16 05:29:55 PM PDT 24
Finished	Jul 16 05:33:36 PM PDT 24
Peak memory	265428 kb
Host	smart-07a3506a-d9fa-4bf3-a832-6d498f8f5164
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114 2663505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.1142663505
Directory	/workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_invalid_op.2599502646
Short name	T888
Test name
Test status
Simulation time	6479382900 ps
CPU time	68.29 seconds
Started	Jul 16 05:29:41 PM PDT 24
Finished	Jul 16 05:30:49 PM PDT 24
Peak memory	262748 kb
Host	smart-d27c239e-cc9c-4051-b99c-b3b7d1d3dd2c
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599502646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.2599502646
Directory	/workspace/1.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_lcmgr_intg.1649079830
Short name	T904
Test name
Test status
Simulation time	40930500 ps
CPU time	13.55 seconds
Started	Jul 16 05:30:03 PM PDT 24
Finished	Jul 16 05:30:17 PM PDT 24
Peak memory	260816 kb
Host	smart-35fa616a-b993-42b7-b8af-586eda8f8f27
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649079830 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.1649079830
Directory	/workspace/1.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mp_regions.553867319
Short name	T945
Test name
Test status
Simulation time	13694517200 ps
CPU time	393.67 seconds
Started	Jul 16 05:29:48 PM PDT 24
Finished	Jul 16 05:36:22 PM PDT 24
Peak memory	275088 kb
Host	smart-eb78ab0f-3221-4ab3-8ac8-25f808856d97
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553867319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.553867319
Directory	/workspace/1.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/1.flash_ctrl_otp_reset.811216837
Short name	T501
Test name
Test status
Simulation time	156928100 ps
CPU time	111.34 seconds
Started	Jul 16 05:29:42 PM PDT 24
Finished	Jul 16 05:31:34 PM PDT 24
Peak memory	260188 kb
Host	smart-387ad28c-1300-4c1b-9057-f4f0e562f024
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811216837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp _reset.811216837
Directory	/workspace/1.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_oversize_error.473275839
Short name	T578
Test name
Test status
Simulation time	5646323200 ps
CPU time	188.31 seconds
Started	Jul 16 05:29:41 PM PDT 24
Finished	Jul 16 05:32:51 PM PDT 24
Peak memory	289940 kb
Host	smart-b7fd17ed-6e78-4d05-afc4-13ffd97e0519
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473275839 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.473275839
Directory	/workspace/1.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb.4077125378
Short name	T1023
Test name
Test status
Simulation time	1406516300 ps
CPU time	287.53 seconds
Started	Jul 16 05:29:42 PM PDT 24
Finished	Jul 16 05:34:30 PM PDT 24
Peak memory	263144 kb
Host	smart-aeb52938-4cce-412d-b0bf-394888301aee
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4077125378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.4077125378
Directory	/workspace/1.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.939067868
Short name	T819
Test name
Test status
Simulation time	14891500 ps
CPU time	13.87 seconds
Started	Jul 16 05:32:25 PM PDT 24
Finished	Jul 16 05:32:40 PM PDT 24
Peak memory	262348 kb
Host	smart-7b376351-b9ce-49ca-958d-0e8afb00cebd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939067868 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.939067868
Directory	/workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_prog_reset.2069112588
Short name	T1016
Test name
Test status
Simulation time	42115500 ps
CPU time	13.75 seconds
Started	Jul 16 05:30:03 PM PDT 24
Finished	Jul 16 05:30:17 PM PDT 24
Peak memory	265260 kb
Host	smart-a07458b6-63ea-4cb0-a92d-3e328a7e3471
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069112588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.flash_ctrl_prog_reset.2069112588
Directory	/workspace/1.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rand_ops.445647576
Short name	T650
Test name
Test status
Simulation time	286566200 ps
CPU time	419.75 seconds
Started	Jul 16 05:29:39 PM PDT 24
Finished	Jul 16 05:36:39 PM PDT 24
Peak memory	281636 kb
Host	smart-dcf889b2-fb79-4b5a-bf81-ff5e5e32c87c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445647576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.445647576
Directory	/workspace/1.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.1700789501
Short name	T55
Test name
Test status
Simulation time	3018162900 ps
CPU time	118.86 seconds
Started	Jul 16 05:29:47 PM PDT 24
Finished	Jul 16 05:31:46 PM PDT 24
Peak memory	262884 kb
Host	smart-018ca71b-56e2-4996-8bbd-807866eca056
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1700789501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.1700789501
Directory	/workspace/1.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_intg.2607966084
Short name	T108
Test name
Test status
Simulation time	124633700 ps
CPU time	28.58 seconds
Started	Jul 16 05:29:58 PM PDT 24
Finished	Jul 16 05:30:27 PM PDT 24
Peak memory	272264 kb
Host	smart-5d68d00e-0240-4ead-aac5-aebd8db0d81d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607966084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_rd_intg.2607966084
Directory	/workspace/1.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_re_evict.3497303252
Short name	T811
Test name
Test status
Simulation time	227119500 ps
CPU time	34.12 seconds
Started	Jul 16 05:29:56 PM PDT 24
Finished	Jul 16 05:30:31 PM PDT 24
Peak memory	275668 kb
Host	smart-327b67e1-a707-446a-8430-3fe5e8fe3ddd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497303252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_re_evict.3497303252
Directory	/workspace/1.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.1114060167
Short name	T848
Test name
Test status
Simulation time	19438700 ps
CPU time	22.49 seconds
Started	Jul 16 05:29:47 PM PDT 24
Finished	Jul 16 05:30:10 PM PDT 24
Peak memory	265012 kb
Host	smart-b736d919-e3e2-4e32-b398-d7218c21375b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114060167 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.1114060167
Directory	/workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1969387330
Short name	T957
Test name
Test status
Simulation time	86338000 ps
CPU time	22.77 seconds
Started	Jul 16 05:29:39 PM PDT 24
Finished	Jul 16 05:30:03 PM PDT 24
Peak memory	264900 kb
Host	smart-25dd34ab-4354-4429-b987-b0f3b19ce66e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969387330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_read_word_sweep_serr.1969387330
Directory	/workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rma_err.2156841360
Short name	T172
Test name
Test status
Simulation time	163787681300 ps
CPU time	973.88 seconds
Started	Jul 16 05:29:53 PM PDT 24
Finished	Jul 16 05:46:08 PM PDT 24
Peak memory	261416 kb
Host	smart-aed558f9-d54c-4858-829c-1703e8d3123b
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156841360 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2156841360
Directory	/workspace/1.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro.9399192
Short name	T81
Test name
Test status
Simulation time	2101733400 ps
CPU time	109.03 seconds
Started	Jul 16 05:29:48 PM PDT 24
Finished	Jul 16 05:31:37 PM PDT 24
Peak memory	291156 kb
Host	smart-55168a00-f2f0-4b85-9e21-54a7b1d41e92
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9399192 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_ro.9399192
Directory	/workspace/1.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_derr.1436838628
Short name	T1030
Test name
Test status
Simulation time	1352535800 ps
CPU time	132.41 seconds
Started	Jul 16 05:29:40 PM PDT 24
Finished	Jul 16 05:31:52 PM PDT 24
Peak memory	281788 kb
Host	smart-d238b8f7-1262-4cfb-81ad-17afe10d280e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1436838628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1436838628
Directory	/workspace/1.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_serr.240648294
Short name	T433
Test name
Test status
Simulation time	693662100 ps
CPU time	119.83 seconds
Started	Jul 16 05:32:27 PM PDT 24
Finished	Jul 16 05:34:27 PM PDT 24
Peak memory	281704 kb
Host	smart-e734ae36-04e4-4036-bf37-a4e7ed209b99
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240648294 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.240648294
Directory	/workspace/1.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw.878276966
Short name	T780
Test name
Test status
Simulation time	2942405600 ps
CPU time	512.52 seconds
Started	Jul 16 05:29:42 PM PDT 24
Finished	Jul 16 05:38:15 PM PDT 24
Peak memory	309744 kb
Host	smart-9af77709-906f-47b2-9c87-d6466c1b0eb5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878276966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.878276966
Directory	/workspace/1.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_derr.3631730858
Short name	T1034
Test name
Test status
Simulation time	25509307700 ps
CPU time	437.26 seconds
Started	Jul 16 05:34:17 PM PDT 24
Finished	Jul 16 05:41:35 PM PDT 24
Peak memory	325344 kb
Host	smart-f31beeea-f7cb-4e0d-8ad9-398614f52d02
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631730858 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_rw_derr.3631730858
Directory	/workspace/1.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict.1242996939
Short name	T682
Test name
Test status
Simulation time	70278400 ps
CPU time	30.54 seconds
Started	Jul 16 05:34:20 PM PDT 24
Finished	Jul 16 05:34:51 PM PDT 24
Peak memory	275676 kb
Host	smart-d752b0df-f838-420b-b306-b7cd62e49a3c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242996939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_rw_evict.1242996939
Directory	/workspace/1.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.3387126948
Short name	T447
Test name
Test status
Simulation time	34597100 ps
CPU time	30.66 seconds
Started	Jul 16 05:29:55 PM PDT 24
Finished	Jul 16 05:30:26 PM PDT 24
Peak memory	275708 kb
Host	smart-ac3e12c6-0fc5-478d-b1ae-096da0a1f957
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387126948 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.3387126948
Directory	/workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_cm.356600433
Short name	T106
Test name
Test status
Simulation time	2585284200 ps
CPU time	4789.81 seconds
Started	Jul 16 05:29:56 PM PDT 24
Finished	Jul 16 06:49:47 PM PDT 24
Peak memory	289100 kb
Host	smart-6e7f93f3-98a5-4356-9cde-69b5ca681ae1
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356600433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.356600433
Directory	/workspace/1.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_info_access.2814544186
Short name	T1039
Test name
Test status
Simulation time	10262273100 ps
CPU time	84.03 seconds
Started	Jul 16 05:29:55 PM PDT 24
Finished	Jul 16 05:31:20 PM PDT 24
Peak memory	263792 kb
Host	smart-a8b40039-abe6-45b5-858b-972887056ada
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814544186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.2814544186
Directory	/workspace/1.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_address.1629708112
Short name	T486
Test name
Test status
Simulation time	1035146900 ps
CPU time	57.18 seconds
Started	Jul 16 05:29:50 PM PDT 24
Finished	Jul 16 05:30:48 PM PDT 24
Peak memory	273548 kb
Host	smart-7d6484a9-a474-4dc2-9eb2-7f8c5673aad5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629708112 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_serr_address.1629708112
Directory	/workspace/1.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke_hw.24384910
Short name	T721
Test name
Test status
Simulation time	17710500 ps
CPU time	26.41 seconds
Started	Jul 16 05:29:47 PM PDT 24
Finished	Jul 16 05:30:14 PM PDT 24
Peak memory	259716 kb
Host	smart-3af559e4-8943-4ea7-af46-e1a1a1aa3092
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24384910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.24384910
Directory	/workspace/1.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_stress_all.4185088729
Short name	T956
Test name
Test status
Simulation time	278004400 ps
CPU time	985.94 seconds
Started	Jul 16 05:34:17 PM PDT 24
Finished	Jul 16 05:50:44 PM PDT 24
Peak memory	283652 kb
Host	smart-9bfb72cf-8ae6-4800-89fa-020b8e508aa6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185088729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres s_all.4185088729
Directory	/workspace/1.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sw_op.2412065146
Short name	T496
Test name
Test status
Simulation time	74513700 ps
CPU time	24.59 seconds
Started	Jul 16 05:29:39 PM PDT 24
Finished	Jul 16 05:30:04 PM PDT 24
Peak memory	262476 kb
Host	smart-ef79ce32-d506-43e6-8390-2e24b4cc27ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2412065146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2412065146
Directory	/workspace/1.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wo.360660906
Short name	T588
Test name
Test status
Simulation time	3934250600 ps
CPU time	178.21 seconds
Started	Jul 16 05:34:28 PM PDT 24
Finished	Jul 16 05:37:27 PM PDT 24
Peak memory	259944 kb
Host	smart-ea0da7d6-b846-43b1-8509-08992861a432
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360660906 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.flash_ctrl_wo.360660906
Directory	/workspace/1.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wr_intg.3518620808
Short name	T8
Test name
Test status
Simulation time	167575100 ps
CPU time	15.1 seconds
Started	Jul 16 05:36:29 PM PDT 24
Finished	Jul 16 05:36:44 PM PDT 24
Peak memory	260720 kb
Host	smart-26950eda-226f-41cf-8ec1-8415ed621b28
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518620808 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.3518620808
Directory	/workspace/1.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/10.flash_ctrl_alert_test.498008603
Short name	T426
Test name
Test status
Simulation time	151830100 ps
CPU time	13.5 seconds
Started	Jul 16 05:32:51 PM PDT 24
Finished	Jul 16 05:33:05 PM PDT 24
Peak memory	265168 kb
Host	smart-34922cb9-8e59-43f5-8885-e9ff7a79bde7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498008603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.498008603
Directory	/workspace/10.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.flash_ctrl_connect.2125596190
Short name	T983
Test name
Test status
Simulation time	52545400 ps
CPU time	13.32 seconds
Started	Jul 16 05:32:51 PM PDT 24
Finished	Jul 16 05:33:05 PM PDT 24
Peak memory	284092 kb
Host	smart-7ce1db7e-04eb-4d71-b800-d96d633eaff3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125596190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.2125596190
Directory	/workspace/10.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/10.flash_ctrl_disable.3079704527
Short name	T273
Test name
Test status
Simulation time	16324000 ps
CPU time	22 seconds
Started	Jul 16 05:36:33 PM PDT 24
Finished	Jul 16 05:36:55 PM PDT 24
Peak memory	273592 kb
Host	smart-d714e5fc-863c-4ca1-a54e-9d33f29593c9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079704527 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_disable.3079704527
Directory	/workspace/10.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_rma_reset.2897009972
Short name	T180
Test name
Test status
Simulation time	80148695300 ps
CPU time	882.73 seconds
Started	Jul 16 05:37:11 PM PDT 24
Finished	Jul 16 05:51:55 PM PDT 24
Peak memory	263624 kb
Host	smart-4d69831d-2ea7-4f4d-8db5-9ac5c5f9eabe
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897009972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.flash_ctrl_hw_rma_reset.2897009972
Directory	/workspace/10.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.3298607336
Short name	T591
Test name
Test status
Simulation time	2914615200 ps
CPU time	200.69 seconds
Started	Jul 16 05:36:53 PM PDT 24
Finished	Jul 16 05:40:15 PM PDT 24
Peak memory	263168 kb
Host	smart-b8b41924-ca45-43a9-8d8a-38656c7df5ab
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298607336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ hw_sec_otp.3298607336
Directory	/workspace/10.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd.2582896648
Short name	T272
Test name
Test status
Simulation time	1619181500 ps
CPU time	206.54 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:40:21 PM PDT 24
Peak memory	284924 kb
Host	smart-8e1418b7-c024-4842-bd6a-f48d42d5ca92
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582896648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_intr_rd.2582896648
Directory	/workspace/10.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/10.flash_ctrl_invalid_op.3493184637
Short name	T1084
Test name
Test status
Simulation time	3353940600 ps
CPU time	65.46 seconds
Started	Jul 16 05:32:34 PM PDT 24
Finished	Jul 16 05:33:39 PM PDT 24
Peak memory	262600 kb
Host	smart-61a548f0-5214-49d0-8503-f995dae94fee
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493184637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.3 493184637
Directory	/workspace/10.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/10.flash_ctrl_lcmgr_intg.1374145441
Short name	T991
Test name
Test status
Simulation time	45135100 ps
CPU time	13.47 seconds
Started	Jul 16 05:32:50 PM PDT 24
Finished	Jul 16 05:33:04 PM PDT 24
Peak memory	260036 kb
Host	smart-caeb873e-e7c7-452a-bfca-0c427e091c12
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374145441 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.1374145441
Directory	/workspace/10.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/10.flash_ctrl_mp_regions.2931179769
Short name	T117
Test name
Test status
Simulation time	12413260700 ps
CPU time	249.02 seconds
Started	Jul 16 05:32:38 PM PDT 24
Finished	Jul 16 05:36:48 PM PDT 24
Peak memory	274340 kb
Host	smart-0e672e84-096a-4836-9348-131c783e9ad4
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931179769 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.2931179769
Directory	/workspace/10.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/10.flash_ctrl_otp_reset.1769985529
Short name	T654
Test name
Test status
Simulation time	70480500 ps
CPU time	133.6 seconds
Started	Jul 16 05:36:51 PM PDT 24
Finished	Jul 16 05:39:06 PM PDT 24
Peak memory	265164 kb
Host	smart-84f8449b-3320-4745-8397-858afe9660d0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769985529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o tp_reset.1769985529
Directory	/workspace/10.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_phy_arb.3605573202
Short name	T820
Test name
Test status
Simulation time	1422241000 ps
CPU time	169.69 seconds
Started	Jul 16 05:32:36 PM PDT 24
Finished	Jul 16 05:35:26 PM PDT 24
Peak memory	262968 kb
Host	smart-f428090b-8c79-4a9c-a7e0-9153f6fd1a03
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3605573202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3605573202
Directory	/workspace/10.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/10.flash_ctrl_prog_reset.185765198
Short name	T1107
Test name
Test status
Simulation time	4855601700 ps
CPU time	206.03 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:40:24 PM PDT 24
Peak memory	260628 kb
Host	smart-07db2ebe-7391-45fe-b9e2-062a095b1638
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185765198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.flash_ctrl_prog_reset.185765198
Directory	/workspace/10.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rand_ops.3720291525
Short name	T630
Test name
Test status
Simulation time	128852800 ps
CPU time	945.51 seconds
Started	Jul 16 05:37:10 PM PDT 24
Finished	Jul 16 05:52:56 PM PDT 24
Peak memory	285600 kb
Host	smart-7e9cb4d9-3d30-42a9-aac5-e1f2e33271f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720291525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.3720291525
Directory	/workspace/10.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/10.flash_ctrl_re_evict.3959984142
Short name	T145
Test name
Test status
Simulation time	258613000 ps
CPU time	32.8 seconds
Started	Jul 16 05:32:52 PM PDT 24
Finished	Jul 16 05:33:25 PM PDT 24
Peak memory	277848 kb
Host	smart-6c902d41-f028-49ac-b8cb-465747ed1d3d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959984142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_re_evict.3959984142
Directory	/workspace/10.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_ro.3486185212
Short name	T875
Test name
Test status
Simulation time	1713718900 ps
CPU time	128.56 seconds
Started	Jul 16 05:32:39 PM PDT 24
Finished	Jul 16 05:34:48 PM PDT 24
Peak memory	281756 kb
Host	smart-52f83dff-64e6-4815-9317-616c7c50bba2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486185212 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 10.flash_ctrl_ro.3486185212
Directory	/workspace/10.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw.1253338933
Short name	T1035
Test name
Test status
Simulation time	3748033300 ps
CPU time	559.72 seconds
Started	Jul 16 05:32:36 PM PDT 24
Finished	Jul 16 05:41:57 PM PDT 24
Peak memory	314060 kb
Host	smart-2fd6b409-7eb5-4460-b656-67864d609b9d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253338933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.flash_ctrl_rw.1253338933
Directory	/workspace/10.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict.526517776
Short name	T555
Test name
Test status
Simulation time	42565500 ps
CPU time	31.78 seconds
Started	Jul 16 05:32:51 PM PDT 24
Finished	Jul 16 05:33:23 PM PDT 24
Peak memory	274760 kb
Host	smart-2a59c163-cb26-459e-ae26-b87ec5d8316f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526517776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_rw_evict.526517776
Directory	/workspace/10.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.3401657245
Short name	T891
Test name
Test status
Simulation time	71527300 ps
CPU time	31.01 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:37:29 PM PDT 24
Peak memory	275420 kb
Host	smart-e203518b-e827-418b-b812-f1a6eb464546
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401657245 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.3401657245
Directory	/workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/10.flash_ctrl_sec_info_access.1851962657
Short name	T443
Test name
Test status
Simulation time	525095300 ps
CPU time	64.35 seconds
Started	Jul 16 05:36:46 PM PDT 24
Finished	Jul 16 05:37:52 PM PDT 24
Peak memory	264040 kb
Host	smart-64b3359d-a361-4fd0-9b41-34a8b898986c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851962657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.1851962657
Directory	/workspace/10.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/10.flash_ctrl_smoke.400595849
Short name	T709
Test name
Test status
Simulation time	40931600 ps
CPU time	123.54 seconds
Started	Jul 16 05:32:36 PM PDT 24
Finished	Jul 16 05:34:40 PM PDT 24
Peak memory	277656 kb
Host	smart-e3a07a1f-d93c-4d8c-a27f-1e0c1d1fe67d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=400595849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.400595849
Directory	/workspace/10.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.flash_ctrl_wo.3719281270
Short name	T961
Test name
Test status
Simulation time	5837716900 ps
CPU time	213.12 seconds
Started	Jul 16 05:32:36 PM PDT 24
Finished	Jul 16 05:36:10 PM PDT 24
Peak memory	260004 kb
Host	smart-1e5793e7-cf11-4dca-a638-0382906f39ed
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719281270 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.flash_ctrl_wo.3719281270
Directory	/workspace/10.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/11.flash_ctrl_alert_test.3206077677
Short name	T421
Test name
Test status
Simulation time	155477100 ps
CPU time	13.93 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:37:05 PM PDT 24
Peak memory	257988 kb
Host	smart-f8cdc57b-eace-4eb9-934f-92563d8101c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206077677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test. 3206077677
Directory	/workspace/11.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.flash_ctrl_connect.179566119
Short name	T1025
Test name
Test status
Simulation time	14016400 ps
CPU time	15.53 seconds
Started	Jul 16 05:36:53 PM PDT 24
Finished	Jul 16 05:37:10 PM PDT 24
Peak memory	274888 kb
Host	smart-b208b3e0-3da9-4909-839c-d9981281b747
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=179566119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.179566119
Directory	/workspace/11.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2684230421
Short name	T286
Test name
Test status
Simulation time	10012014400 ps
CPU time	329.57 seconds
Started	Jul 16 05:33:00 PM PDT 24
Finished	Jul 16 05:38:30 PM PDT 24
Peak memory	332244 kb
Host	smart-727e55e4-ad27-4ea4-8a75-0610febbb989
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684230421 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.2684230421
Directory	/workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.2776456061
Short name	T814
Test name
Test status
Simulation time	25730900 ps
CPU time	13.39 seconds
Started	Jul 16 05:37:18 PM PDT 24
Finished	Jul 16 05:37:32 PM PDT 24
Peak memory	258664 kb
Host	smart-eb07c9c9-8e1f-4ebd-bcf8-212778f73f8f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776456061 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.2776456061
Directory	/workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_rma_reset.1110525420
Short name	T909
Test name
Test status
Simulation time	80152409400 ps
CPU time	836.88 seconds
Started	Jul 16 05:32:58 PM PDT 24
Finished	Jul 16 05:46:56 PM PDT 24
Peak memory	260844 kb
Host	smart-da6fe674-17e1-42ff-bba9-9fb0feeebc63
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110525420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.flash_ctrl_hw_rma_reset.1110525420
Directory	/workspace/11.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_sec_otp.2870445195
Short name	T541
Test name
Test status
Simulation time	3276170100 ps
CPU time	100.77 seconds
Started	Jul 16 05:36:51 PM PDT 24
Finished	Jul 16 05:38:32 PM PDT 24
Peak memory	263164 kb
Host	smart-c85bd67d-138f-4b16-a776-84647c263a7d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870445195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ hw_sec_otp.2870445195
Directory	/workspace/11.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd.3890210238
Short name	T277
Test name
Test status
Simulation time	3440687300 ps
CPU time	215.39 seconds
Started	Jul 16 05:33:06 PM PDT 24
Finished	Jul 16 05:36:42 PM PDT 24
Peak memory	284684 kb
Host	smart-6f6643aa-a806-4eb4-b885-853b48cf5dd5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890210238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla sh_ctrl_intr_rd.3890210238
Directory	/workspace/11.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1927867711
Short name	T29
Test name
Test status
Simulation time	168512890400 ps
CPU time	234.93 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:40:59 PM PDT 24
Peak memory	293876 kb
Host	smart-9e581d39-eada-4e3f-aea6-32d678968310
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927867711 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.1927867711
Directory	/workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1891007131
Short name	T876
Test name
Test status
Simulation time	15370300 ps
CPU time	13.64 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:37:17 PM PDT 24
Peak memory	264992 kb
Host	smart-cc012d6f-4cce-478f-bb2f-f6174bc25f03
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891007131 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.1891007131
Directory	/workspace/11.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/11.flash_ctrl_mp_regions.337077895
Short name	T123
Test name
Test status
Simulation time	336197521100 ps
CPU time	494.03 seconds
Started	Jul 16 05:36:57 PM PDT 24
Finished	Jul 16 05:45:12 PM PDT 24
Peak memory	274656 kb
Host	smart-ca8d57fa-6b99-4f01-beed-20150f631731
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337077895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.337077895
Directory	/workspace/11.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/11.flash_ctrl_otp_reset.3231979155
Short name	T898
Test name
Test status
Simulation time	145840300 ps
CPU time	109.81 seconds
Started	Jul 16 05:33:22 PM PDT 24
Finished	Jul 16 05:35:13 PM PDT 24
Peak memory	260048 kb
Host	smart-12e78b2a-c7a2-48cb-9802-f592218d8926
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231979155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o tp_reset.3231979155
Directory	/workspace/11.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_phy_arb.3582048032
Short name	T420
Test name
Test status
Simulation time	129843600 ps
CPU time	110.52 seconds
Started	Jul 16 05:32:59 PM PDT 24
Finished	Jul 16 05:34:49 PM PDT 24
Peak memory	263256 kb
Host	smart-5204582f-ebdb-4c6b-a338-95cf6c5b733a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3582048032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.3582048032
Directory	/workspace/11.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/11.flash_ctrl_prog_reset.840291707
Short name	T532
Test name
Test status
Simulation time	26408500 ps
CPU time	13.28 seconds
Started	Jul 16 05:33:06 PM PDT 24
Finished	Jul 16 05:33:20 PM PDT 24
Peak memory	259200 kb
Host	smart-efa8c4d4-f872-49bf-9065-e8496fab46ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840291707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.flash_ctrl_prog_reset.840291707
Directory	/workspace/11.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rand_ops.2236461071
Short name	T132
Test name
Test status
Simulation time	431936300 ps
CPU time	434.45 seconds
Started	Jul 16 05:33:00 PM PDT 24
Finished	Jul 16 05:40:15 PM PDT 24
Peak memory	281648 kb
Host	smart-1a0ff0d9-13ef-4054-9256-2512c18aa099
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2236461071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.2236461071
Directory	/workspace/11.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/11.flash_ctrl_re_evict.426870296
Short name	T973
Test name
Test status
Simulation time	245156900 ps
CPU time	35.17 seconds
Started	Jul 16 05:33:10 PM PDT 24
Finished	Jul 16 05:33:45 PM PDT 24
Peak memory	275652 kb
Host	smart-2002a6fe-c126-44f7-9012-d5fc3762846e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426870296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla sh_ctrl_re_evict.426870296
Directory	/workspace/11.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_ro.316356526
Short name	T710
Test name
Test status
Simulation time	1070992600 ps
CPU time	116.44 seconds
Started	Jul 16 05:33:03 PM PDT 24
Finished	Jul 16 05:35:00 PM PDT 24
Peak memory	289932 kb
Host	smart-ebfc4065-a4d6-4a6c-afd9-9291049c4d6f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316356526 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.flash_ctrl_ro.316356526
Directory	/workspace/11.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw.3579827772
Short name	T749
Test name
Test status
Simulation time	15114577800 ps
CPU time	458.26 seconds
Started	Jul 16 05:33:00 PM PDT 24
Finished	Jul 16 05:40:38 PM PDT 24
Peak memory	309952 kb
Host	smart-7ffcf424-dec9-4dec-9408-a0cd48886126
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579827772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.flash_ctrl_rw.3579827772
Directory	/workspace/11.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict.1876616829
Short name	T206
Test name
Test status
Simulation time	262283600 ps
CPU time	30.43 seconds
Started	Jul 16 05:33:05 PM PDT 24
Finished	Jul 16 05:33:36 PM PDT 24
Peak memory	275664 kb
Host	smart-464a6707-87a2-41e4-aab0-3e3bdaf953d3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876616829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_rw_evict.1876616829
Directory	/workspace/11.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_sec_info_access.357083234
Short name	T808
Test name
Test status
Simulation time	365975200 ps
CPU time	55.43 seconds
Started	Jul 16 05:37:10 PM PDT 24
Finished	Jul 16 05:38:07 PM PDT 24
Peak memory	263740 kb
Host	smart-b8a1a827-7e31-4db1-a78f-698434246cb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357083234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.357083234
Directory	/workspace/11.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/11.flash_ctrl_smoke.566980517
Short name	T446
Test name
Test status
Simulation time	18891000 ps
CPU time	144.53 seconds
Started	Jul 16 05:33:02 PM PDT 24
Finished	Jul 16 05:35:26 PM PDT 24
Peak memory	269936 kb
Host	smart-94f773fa-002e-4e0c-a275-8449e8eb9991
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566980517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.566980517
Directory	/workspace/11.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.flash_ctrl_wo.1213398773
Short name	T130
Test name
Test status
Simulation time	12071946500 ps
CPU time	132.95 seconds
Started	Jul 16 05:33:01 PM PDT 24
Finished	Jul 16 05:35:14 PM PDT 24
Peak memory	259900 kb
Host	smart-d422f174-4acf-428d-9af1-cc4998d498a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213398773 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.flash_ctrl_wo.1213398773
Directory	/workspace/11.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/12.flash_ctrl_alert_test.958595198
Short name	T691
Test name
Test status
Simulation time	81470400 ps
CPU time	13.69 seconds
Started	Jul 16 05:33:07 PM PDT 24
Finished	Jul 16 05:33:21 PM PDT 24
Peak memory	258376 kb
Host	smart-b266241c-5b6e-46a8-bed7-3140ac6f28e9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958595198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.958595198
Directory	/workspace/12.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.flash_ctrl_connect.454430146
Short name	T788
Test name
Test status
Simulation time	27731600 ps
CPU time	13.56 seconds
Started	Jul 16 05:33:11 PM PDT 24
Finished	Jul 16 05:33:25 PM PDT 24
Peak memory	284160 kb
Host	smart-c165aa8b-6aa5-4e43-ada7-d45ccd968f6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=454430146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.454430146
Directory	/workspace/12.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3028811595
Short name	T883
Test name
Test status
Simulation time	10012212700 ps
CPU time	123.67 seconds
Started	Jul 16 05:33:07 PM PDT 24
Finished	Jul 16 05:35:11 PM PDT 24
Peak memory	322020 kb
Host	smart-d3397b33-cc84-4723-af3b-1b6673ffa1cb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028811595 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.3028811595
Directory	/workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.144429629
Short name	T1005
Test name
Test status
Simulation time	25913200 ps
CPU time	13.23 seconds
Started	Jul 16 05:33:08 PM PDT 24
Finished	Jul 16 05:33:21 PM PDT 24
Peak memory	265452 kb
Host	smart-3d898f65-0fd1-4ff6-94e8-b6dd783e0518
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144429629 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.144429629
Directory	/workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.447206590
Short name	T177
Test name
Test status
Simulation time	40127980600 ps
CPU time	836.01 seconds
Started	Jul 16 05:33:05 PM PDT 24
Finished	Jul 16 05:47:01 PM PDT 24
Peak memory	264364 kb
Host	smart-89fe0c06-13cf-4e3a-a9ea-f8bbfcb3cdc2
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447206590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.flash_ctrl_hw_rma_reset.447206590
Directory	/workspace/12.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_sec_otp.3508571414
Short name	T686
Test name
Test status
Simulation time	1738367100 ps
CPU time	80.06 seconds
Started	Jul 16 05:33:09 PM PDT 24
Finished	Jul 16 05:34:30 PM PDT 24
Peak memory	260820 kb
Host	smart-bf3b2ab2-1da9-47aa-8623-bedc809d9e6e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508571414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ hw_sec_otp.3508571414
Directory	/workspace/12.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd.1825846653
Short name	T564
Test name
Test status
Simulation time	2574645400 ps
CPU time	214.64 seconds
Started	Jul 16 05:33:00 PM PDT 24
Finished	Jul 16 05:36:35 PM PDT 24
Peak memory	284960 kb
Host	smart-5d4d8fc2-d346-4ed1-b2cb-baf59ff0138c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825846653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_intr_rd.1825846653
Directory	/workspace/12.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.1808947478
Short name	T842
Test name
Test status
Simulation time	23687606300 ps
CPU time	145.9 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:39:29 PM PDT 24
Peak memory	293140 kb
Host	smart-1320a5d0-da4d-41d7-ab55-e23dac6a8b97
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808947478 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.1808947478
Directory	/workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/12.flash_ctrl_invalid_op.4049578031
Short name	T72
Test name
Test status
Simulation time	4397765200 ps
CPU time	89.42 seconds
Started	Jul 16 05:33:02 PM PDT 24
Finished	Jul 16 05:34:32 PM PDT 24
Peak memory	263492 kb
Host	smart-12082533-b154-4ad6-8a98-1bc09a43fe69
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049578031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.4 049578031
Directory	/workspace/12.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1562587407
Short name	T852
Test name
Test status
Simulation time	15603900 ps
CPU time	13.32 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:37:04 PM PDT 24
Peak memory	264992 kb
Host	smart-96039b31-81a0-4d3f-942f-3ff0cb96cffa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562587407 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.1562587407
Directory	/workspace/12.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/12.flash_ctrl_mp_regions.3249677822
Short name	T1011
Test name
Test status
Simulation time	12243631100 ps
CPU time	208.41 seconds
Started	Jul 16 05:33:00 PM PDT 24
Finished	Jul 16 05:36:29 PM PDT 24
Peak memory	265160 kb
Host	smart-3c203c26-264a-4663-b404-e7a7235c24aa
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249677822 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.3249677822
Directory	/workspace/12.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/12.flash_ctrl_otp_reset.1877571412
Short name	T974
Test name
Test status
Simulation time	158414900 ps
CPU time	130.3 seconds
Started	Jul 16 05:33:04 PM PDT 24
Finished	Jul 16 05:35:15 PM PDT 24
Peak memory	260080 kb
Host	smart-70e7d0ad-0c50-4943-992b-53ca1737a919
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877571412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o tp_reset.1877571412
Directory	/workspace/12.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_phy_arb.3645275196
Short name	T245
Test name
Test status
Simulation time	265106600 ps
CPU time	276.48 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:41:40 PM PDT 24
Peak memory	263240 kb
Host	smart-b1b1a665-81c9-4d63-8296-9a7a59323495
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3645275196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.3645275196
Directory	/workspace/12.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/12.flash_ctrl_prog_reset.30808821
Short name	T636
Test name
Test status
Simulation time	86876800 ps
CPU time	13.49 seconds
Started	Jul 16 05:36:47 PM PDT 24
Finished	Jul 16 05:37:01 PM PDT 24
Peak memory	258992 kb
Host	smart-776fdd98-e670-42f6-b7f8-20922c60b4d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30808821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U VM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_prog_reset.30808821
Directory	/workspace/12.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rand_ops.690166085
Short name	T133
Test name
Test status
Simulation time	858142700 ps
CPU time	659 seconds
Started	Jul 16 05:33:02 PM PDT 24
Finished	Jul 16 05:44:01 PM PDT 24
Peak memory	282812 kb
Host	smart-6a0a9c0a-9346-44ce-86ab-86316be64631
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690166085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.690166085
Directory	/workspace/12.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/12.flash_ctrl_ro.4079355179
Short name	T849
Test name
Test status
Simulation time	589630900 ps
CPU time	94.73 seconds
Started	Jul 16 05:33:05 PM PDT 24
Finished	Jul 16 05:34:41 PM PDT 24
Peak memory	291428 kb
Host	smart-ad834382-e052-41af-b3b6-da1bfcb444fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079355179 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 12.flash_ctrl_ro.4079355179
Directory	/workspace/12.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw.1589760775
Short name	T771
Test name
Test status
Simulation time	13480543000 ps
CPU time	585.14 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:46:36 PM PDT 24
Peak memory	317652 kb
Host	smart-3da0f60e-464e-4e03-ae3c-48d25975ccb0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589760775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.flash_ctrl_rw.1589760775
Directory	/workspace/12.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict.3560408131
Short name	T351
Test name
Test status
Simulation time	27861700 ps
CPU time	30.95 seconds
Started	Jul 16 05:33:04 PM PDT 24
Finished	Jul 16 05:33:36 PM PDT 24
Peak memory	275636 kb
Host	smart-b9bda870-2fcb-4fce-8e7d-f23eb9bf4df6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560408131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_rw_evict.3560408131
Directory	/workspace/12.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.3929002100
Short name	T638
Test name
Test status
Simulation time	53183500 ps
CPU time	30.62 seconds
Started	Jul 16 05:36:25 PM PDT 24
Finished	Jul 16 05:36:56 PM PDT 24
Peak memory	273664 kb
Host	smart-c48d9046-f246-406e-bb09-bd0786e7903f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929002100 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.3929002100
Directory	/workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/12.flash_ctrl_smoke.1393151009
Short name	T670
Test name
Test status
Simulation time	40285500 ps
CPU time	145.77 seconds
Started	Jul 16 05:33:00 PM PDT 24
Finished	Jul 16 05:35:27 PM PDT 24
Peak memory	278252 kb
Host	smart-96793857-9671-444a-8d50-a7f972832624
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1393151009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1393151009
Directory	/workspace/12.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.flash_ctrl_wo.131873161
Short name	T869
Test name
Test status
Simulation time	10232585100 ps
CPU time	207.67 seconds
Started	Jul 16 05:32:58 PM PDT 24
Finished	Jul 16 05:36:26 PM PDT 24
Peak memory	265124 kb
Host	smart-2b985093-39e5-4ddf-afce-38182e60dbd7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131873161 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 12.flash_ctrl_wo.131873161
Directory	/workspace/12.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/13.flash_ctrl_alert_test.3872179035
Short name	T729
Test name
Test status
Simulation time	43235200 ps
CPU time	13.61 seconds
Started	Jul 16 05:37:09 PM PDT 24
Finished	Jul 16 05:37:23 PM PDT 24
Peak memory	258280 kb
Host	smart-99b09f05-f30c-4676-8946-af0f07810d9a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872179035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test. 3872179035
Directory	/workspace/13.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.flash_ctrl_connect.1072565678
Short name	T1075
Test name
Test status
Simulation time	52610500 ps
CPU time	15.73 seconds
Started	Jul 16 05:33:20 PM PDT 24
Finished	Jul 16 05:33:36 PM PDT 24
Peak memory	284244 kb
Host	smart-e038c2c1-ccff-4c31-a2fb-fafcaab0b513
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072565678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1072565678
Directory	/workspace/13.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2131118033
Short name	T735
Test name
Test status
Simulation time	10021047000 ps
CPU time	91.06 seconds
Started	Jul 16 05:33:30 PM PDT 24
Finished	Jul 16 05:35:02 PM PDT 24
Peak memory	323328 kb
Host	smart-7d7e4f30-facb-4a19-b886-630a88e897bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131118033 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2131118033
Directory	/workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3152813796
Short name	T918
Test name
Test status
Simulation time	46946400 ps
CPU time	13.29 seconds
Started	Jul 16 05:36:47 PM PDT 24
Finished	Jul 16 05:37:01 PM PDT 24
Peak memory	265032 kb
Host	smart-1bf25a14-7160-4e96-8833-afaa59a393ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152813796 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3152813796
Directory	/workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2335853667
Short name	T179
Test name
Test status
Simulation time	80154973500 ps
CPU time	917.15 seconds
Started	Jul 16 05:33:09 PM PDT 24
Finished	Jul 16 05:48:27 PM PDT 24
Peak memory	264280 kb
Host	smart-17d2ec75-830f-4a5b-aa68-e7486100b822
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335853667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.flash_ctrl_hw_rma_reset.2335853667
Directory	/workspace/13.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.1848470296
Short name	T540
Test name
Test status
Simulation time	14210616900 ps
CPU time	92.31 seconds
Started	Jul 16 05:36:25 PM PDT 24
Finished	Jul 16 05:37:58 PM PDT 24
Peak memory	262832 kb
Host	smart-b8c41f21-6e32-427c-b2d7-9f541b859273
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848470296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ hw_sec_otp.1848470296
Directory	/workspace/13.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd.2890383224
Short name	T937
Test name
Test status
Simulation time	1843035400 ps
CPU time	136.48 seconds
Started	Jul 16 05:33:10 PM PDT 24
Finished	Jul 16 05:35:27 PM PDT 24
Peak memory	291040 kb
Host	smart-079ebd0a-3432-4aeb-8583-1422ac1f3b9d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890383224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_intr_rd.2890383224
Directory	/workspace/13.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.4068599966
Short name	T744
Test name
Test status
Simulation time	240376204100 ps
CPU time	384.47 seconds
Started	Jul 16 05:33:11 PM PDT 24
Finished	Jul 16 05:39:36 PM PDT 24
Peak memory	289960 kb
Host	smart-243ee688-a27c-4ff1-a52b-5461a106579b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068599966 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.4068599966
Directory	/workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/13.flash_ctrl_invalid_op.1496777664
Short name	T313
Test name
Test status
Simulation time	996785600 ps
CPU time	86.59 seconds
Started	Jul 16 05:33:09 PM PDT 24
Finished	Jul 16 05:34:36 PM PDT 24
Peak memory	263388 kb
Host	smart-18cc8a4a-95c4-4337-a5a3-f54b64a0c49d
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496777664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.1 496777664
Directory	/workspace/13.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/13.flash_ctrl_mp_regions.2930323040
Short name	T129
Test name
Test status
Simulation time	3505957100 ps
CPU time	132.53 seconds
Started	Jul 16 05:36:46 PM PDT 24
Finished	Jul 16 05:38:59 PM PDT 24
Peak memory	265092 kb
Host	smart-1299d6fa-b41e-42c1-bcce-0d7dc81a2ffe
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930323040 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.2930323040
Directory	/workspace/13.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/13.flash_ctrl_otp_reset.448113003
Short name	T707
Test name
Test status
Simulation time	41150300 ps
CPU time	133.52 seconds
Started	Jul 16 05:33:09 PM PDT 24
Finished	Jul 16 05:35:22 PM PDT 24
Peak memory	261128 kb
Host	smart-96e0b433-657d-4f5b-b3df-1323758474da
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448113003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ot p_reset.448113003
Directory	/workspace/13.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_phy_arb.618584344
Short name	T688
Test name
Test status
Simulation time	82535100 ps
CPU time	154.23 seconds
Started	Jul 16 05:37:18 PM PDT 24
Finished	Jul 16 05:39:53 PM PDT 24
Peak memory	263156 kb
Host	smart-e6076873-f6d2-41bb-89dd-7f3d2f41af2e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=618584344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.618584344
Directory	/workspace/13.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/13.flash_ctrl_prog_reset.2350714102
Short name	T716
Test name
Test status
Simulation time	63251900 ps
CPU time	13.71 seconds
Started	Jul 16 05:33:09 PM PDT 24
Finished	Jul 16 05:33:23 PM PDT 24
Peak memory	259020 kb
Host	smart-83c00ede-b2b3-4e24-a991-daf19d5234df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350714102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.flash_ctrl_prog_reset.2350714102
Directory	/workspace/13.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rand_ops.362520716
Short name	T601
Test name
Test status
Simulation time	710171000 ps
CPU time	1312.64 seconds
Started	Jul 16 05:33:11 PM PDT 24
Finished	Jul 16 05:55:04 PM PDT 24
Peak memory	289320 kb
Host	smart-ee631315-0010-43f2-b91a-7249e984ac3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=362520716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.362520716
Directory	/workspace/13.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/13.flash_ctrl_ro.1644979966
Short name	T432
Test name
Test status
Simulation time	1703647300 ps
CPU time	122.72 seconds
Started	Jul 16 05:33:06 PM PDT 24
Finished	Jul 16 05:35:09 PM PDT 24
Peak memory	281576 kb
Host	smart-f33f346f-38a1-448f-ba84-e30fb951c618
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644979966 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 13.flash_ctrl_ro.1644979966
Directory	/workspace/13.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.3036184010
Short name	T269
Test name
Test status
Simulation time	153794800 ps
CPU time	28.63 seconds
Started	Jul 16 05:33:08 PM PDT 24
Finished	Jul 16 05:33:37 PM PDT 24
Peak memory	268500 kb
Host	smart-9850f466-7a70-4cb5-add8-be610dcebf9d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036184010 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.3036184010
Directory	/workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/13.flash_ctrl_sec_info_access.4187172323
Short name	T113
Test name
Test status
Simulation time	4463162800 ps
CPU time	79.9 seconds
Started	Jul 16 05:33:21 PM PDT 24
Finished	Jul 16 05:34:41 PM PDT 24
Peak memory	263664 kb
Host	smart-0e20a223-4dc1-49e5-b3d7-41ef7ccca3dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187172323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.4187172323
Directory	/workspace/13.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/13.flash_ctrl_smoke.1470074537
Short name	T483
Test name
Test status
Simulation time	696077000 ps
CPU time	219.93 seconds
Started	Jul 16 05:33:11 PM PDT 24
Finished	Jul 16 05:36:52 PM PDT 24
Peak memory	281604 kb
Host	smart-c87e72a6-905e-4fa5-8d88-c4568591b127
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470074537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.1470074537
Directory	/workspace/13.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.flash_ctrl_wo.4235819691
Short name	T460
Test name
Test status
Simulation time	3956587800 ps
CPU time	162.96 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:39:38 PM PDT 24
Peak memory	265252 kb
Host	smart-1460e494-903e-4ec5-ac80-b3a3d40ac23a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235819691 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.flash_ctrl_wo.4235819691
Directory	/workspace/13.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/14.flash_ctrl_alert_test.2523225729
Short name	T892
Test name
Test status
Simulation time	360360300 ps
CPU time	13.73 seconds
Started	Jul 16 05:36:37 PM PDT 24
Finished	Jul 16 05:36:52 PM PDT 24
Peak memory	265076 kb
Host	smart-2cf58280-a961-4772-ae04-a590f342c6fb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523225729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test. 2523225729
Directory	/workspace/14.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.flash_ctrl_connect.2860914200
Short name	T580
Test name
Test status
Simulation time	32821900 ps
CPU time	15.92 seconds
Started	Jul 16 05:33:30 PM PDT 24
Finished	Jul 16 05:33:47 PM PDT 24
Peak memory	284152 kb
Host	smart-529aadc7-e8f4-451b-9779-c360d8b66d86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2860914200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.2860914200
Directory	/workspace/14.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/14.flash_ctrl_disable.1744144977
Short name	T863
Test name
Test status
Simulation time	10790300 ps
CPU time	21.26 seconds
Started	Jul 16 05:37:11 PM PDT 24
Finished	Jul 16 05:37:33 PM PDT 24
Peak memory	272768 kb
Host	smart-e15263da-acf7-4250-aa6d-35b3d5a669e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744144977 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_disable.1744144977
Directory	/workspace/14.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.3978999295
Short name	T165
Test name
Test status
Simulation time	10012068900 ps
CPU time	128.29 seconds
Started	Jul 16 05:33:27 PM PDT 24
Finished	Jul 16 05:35:36 PM PDT 24
Peak memory	359208 kb
Host	smart-c2379d7a-df81-438f-b3e3-bffee88f6a4b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978999295 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.3978999295
Directory	/workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.54733129
Short name	T112
Test name
Test status
Simulation time	15308700 ps
CPU time	13.32 seconds
Started	Jul 16 05:33:30 PM PDT 24
Finished	Jul 16 05:33:44 PM PDT 24
Peak memory	258440 kb
Host	smart-9bde225f-e875-46a8-a493-f0c256250201
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54733129 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.54733129
Directory	/workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_rma_reset.2964497652
Short name	T157
Test name
Test status
Simulation time	160172979500 ps
CPU time	955.63 seconds
Started	Jul 16 05:33:19 PM PDT 24
Finished	Jul 16 05:49:15 PM PDT 24
Peak memory	264944 kb
Host	smart-fcd03931-09fb-4cd5-b1de-7bf8e95ebfc6
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964497652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.flash_ctrl_hw_rma_reset.2964497652
Directory	/workspace/14.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.4187852215
Short name	T315
Test name
Test status
Simulation time	9396790900 ps
CPU time	170.81 seconds
Started	Jul 16 05:36:33 PM PDT 24
Finished	Jul 16 05:39:25 PM PDT 24
Peak memory	262004 kb
Host	smart-8e7b31aa-c2ca-4d33-a173-86d63e60bb27
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187852215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ hw_sec_otp.4187852215
Directory	/workspace/14.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd.1603529835
Short name	T699
Test name
Test status
Simulation time	4039413800 ps
CPU time	199.17 seconds
Started	Jul 16 05:37:10 PM PDT 24
Finished	Jul 16 05:40:30 PM PDT 24
Peak memory	284836 kb
Host	smart-b9815e8c-ba02-455f-bb83-413c3e208754
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603529835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla sh_ctrl_intr_rd.1603529835
Directory	/workspace/14.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3208270181
Short name	T610
Test name
Test status
Simulation time	7045311100 ps
CPU time	157.75 seconds
Started	Jul 16 05:33:24 PM PDT 24
Finished	Jul 16 05:36:02 PM PDT 24
Peak memory	294028 kb
Host	smart-29b53598-33eb-4e2c-9322-c1163463f3cc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208270181 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.3208270181
Directory	/workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/14.flash_ctrl_invalid_op.1919732433
Short name	T416
Test name
Test status
Simulation time	3355500200 ps
CPU time	66.4 seconds
Started	Jul 16 05:36:37 PM PDT 24
Finished	Jul 16 05:37:45 PM PDT 24
Peak memory	262620 kb
Host	smart-8f19a11d-257a-47d4-99fb-1d1bc2386c56
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919732433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1 919732433
Directory	/workspace/14.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.3477236139
Short name	T924
Test name
Test status
Simulation time	44696900 ps
CPU time	13.37 seconds
Started	Jul 16 05:33:29 PM PDT 24
Finished	Jul 16 05:33:43 PM PDT 24
Peak memory	259944 kb
Host	smart-3fd938c6-b5d5-4d92-a6c0-d6f20b0e9950
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477236139 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.3477236139
Directory	/workspace/14.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/14.flash_ctrl_mp_regions.1337410407
Short name	T600
Test name
Test status
Simulation time	7056966100 ps
CPU time	106.21 seconds
Started	Jul 16 05:33:27 PM PDT 24
Finished	Jul 16 05:35:14 PM PDT 24
Peak memory	265168 kb
Host	smart-c1207de5-a1ef-47bb-872d-f85081845541
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337410407 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.1337410407
Directory	/workspace/14.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/14.flash_ctrl_otp_reset.2812494392
Short name	T455
Test name
Test status
Simulation time	39886200 ps
CPU time	132.08 seconds
Started	Jul 16 05:33:21 PM PDT 24
Finished	Jul 16 05:35:33 PM PDT 24
Peak memory	265056 kb
Host	smart-198427a5-4e51-4a8e-94e4-a0a10fd81d44
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812494392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o tp_reset.2812494392
Directory	/workspace/14.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_phy_arb.92775823
Short name	T457
Test name
Test status
Simulation time	76268600 ps
CPU time	317.12 seconds
Started	Jul 16 05:37:11 PM PDT 24
Finished	Jul 16 05:42:30 PM PDT 24
Peak memory	262952 kb
Host	smart-72e0e50e-d75c-45ad-aedf-d8e9bdb534d8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=92775823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.92775823
Directory	/workspace/14.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/14.flash_ctrl_prog_reset.1817801222
Short name	T1058
Test name
Test status
Simulation time	76165000 ps
CPU time	13.34 seconds
Started	Jul 16 05:33:20 PM PDT 24
Finished	Jul 16 05:33:34 PM PDT 24
Peak memory	258988 kb
Host	smart-1817be97-30e2-47eb-9f55-ea5a05fdf9df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817801222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.flash_ctrl_prog_reset.1817801222
Directory	/workspace/14.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rand_ops.3422054712
Short name	T762
Test name
Test status
Simulation time	95919700 ps
CPU time	376.57 seconds
Started	Jul 16 05:33:24 PM PDT 24
Finished	Jul 16 05:39:41 PM PDT 24
Peak memory	282668 kb
Host	smart-efe54474-63d8-4000-a217-7a15e96ad1f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422054712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3422054712
Directory	/workspace/14.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/14.flash_ctrl_re_evict.932526097
Short name	T776
Test name
Test status
Simulation time	490006400 ps
CPU time	35.87 seconds
Started	Jul 16 05:33:28 PM PDT 24
Finished	Jul 16 05:34:04 PM PDT 24
Peak memory	275684 kb
Host	smart-b4588afe-79ff-4aaf-8e8a-87e851de49f3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932526097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla sh_ctrl_re_evict.932526097
Directory	/workspace/14.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_ro.851238317
Short name	T1097
Test name
Test status
Simulation time	567488200 ps
CPU time	115.9 seconds
Started	Jul 16 05:33:20 PM PDT 24
Finished	Jul 16 05:35:16 PM PDT 24
Peak memory	281760 kb
Host	smart-3d984b82-324c-4248-8b92-535f333f83d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851238317 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.flash_ctrl_ro.851238317
Directory	/workspace/14.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw.3084990056
Short name	T573
Test name
Test status
Simulation time	10085575300 ps
CPU time	596.8 seconds
Started	Jul 16 05:33:30 PM PDT 24
Finished	Jul 16 05:43:28 PM PDT 24
Peak memory	309448 kb
Host	smart-308a1a28-88cc-4781-8a73-148884fa622c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084990056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.flash_ctrl_rw.3084990056
Directory	/workspace/14.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict.1196517598
Short name	T668
Test name
Test status
Simulation time	39767900 ps
CPU time	29.71 seconds
Started	Jul 16 05:33:18 PM PDT 24
Finished	Jul 16 05:33:48 PM PDT 24
Peak memory	268468 kb
Host	smart-eb2fb96f-e60f-4189-8a66-e7afd96c0d96
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196517598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_rw_evict.1196517598
Directory	/workspace/14.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3218630841
Short name	T676
Test name
Test status
Simulation time	70970400 ps
CPU time	27.32 seconds
Started	Jul 16 05:33:16 PM PDT 24
Finished	Jul 16 05:33:44 PM PDT 24
Peak memory	268580 kb
Host	smart-e9798230-7870-43c2-909d-f6f3ee84facd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218630841 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3218630841
Directory	/workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/14.flash_ctrl_sec_info_access.1293083130
Short name	T28
Test name
Test status
Simulation time	2854547900 ps
CPU time	61.08 seconds
Started	Jul 16 05:33:24 PM PDT 24
Finished	Jul 16 05:34:26 PM PDT 24
Peak memory	263600 kb
Host	smart-ada5c067-17f0-4265-9e53-682f8b910157
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293083130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1293083130
Directory	/workspace/14.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/14.flash_ctrl_smoke.3807979470
Short name	T865
Test name
Test status
Simulation time	353502800 ps
CPU time	189.35 seconds
Started	Jul 16 05:33:30 PM PDT 24
Finished	Jul 16 05:36:40 PM PDT 24
Peak memory	277512 kb
Host	smart-80d027b9-64d0-4c0a-8c81-c41402e7114b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807979470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3807979470
Directory	/workspace/14.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.flash_ctrl_wo.4167674956
Short name	T779
Test name
Test status
Simulation time	1669788700 ps
CPU time	142.13 seconds
Started	Jul 16 05:33:19 PM PDT 24
Finished	Jul 16 05:35:42 PM PDT 24
Peak memory	265120 kb
Host	smart-1c8cca75-0ba7-4f86-921f-3d48d1042fd1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167674956 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.flash_ctrl_wo.4167674956
Directory	/workspace/14.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/15.flash_ctrl_alert_test.2943238164
Short name	T895
Test name
Test status
Simulation time	69879900 ps
CPU time	13.4 seconds
Started	Jul 16 05:33:31 PM PDT 24
Finished	Jul 16 05:33:45 PM PDT 24
Peak memory	265240 kb
Host	smart-ed04f8d8-1997-4c8f-ab71-4a118e39d154
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943238164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test. 2943238164
Directory	/workspace/15.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.flash_ctrl_connect.2304510820
Short name	T524
Test name
Test status
Simulation time	33149600 ps
CPU time	16.16 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:37:07 PM PDT 24
Peak memory	284136 kb
Host	smart-4f2bb719-6e68-418b-8623-5aab8bc9724f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304510820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.2304510820
Directory	/workspace/15.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/15.flash_ctrl_disable.2221125601
Short name	T93
Test name
Test status
Simulation time	15318000 ps
CPU time	21.65 seconds
Started	Jul 16 05:33:30 PM PDT 24
Finished	Jul 16 05:33:53 PM PDT 24
Peak memory	265720 kb
Host	smart-437fa08f-5fae-414d-a77c-6effd3e56d23
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221125601 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_disable.2221125601
Directory	/workspace/15.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3684991050
Short name	T1090
Test name
Test status
Simulation time	10019568900 ps
CPU time	74.05 seconds
Started	Jul 16 05:34:31 PM PDT 24
Finished	Jul 16 05:35:46 PM PDT 24
Peak memory	313588 kb
Host	smart-a727af12-9463-4e00-ab25-5763a53077f1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684991050 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3684991050
Directory	/workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.2248737279
Short name	T150
Test name
Test status
Simulation time	26732000 ps
CPU time	13.29 seconds
Started	Jul 16 05:37:21 PM PDT 24
Finished	Jul 16 05:37:35 PM PDT 24
Peak memory	260236 kb
Host	smart-1a9f6b0e-4c4d-4613-b0fc-203c7fe8a9c1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248737279 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.2248737279
Directory	/workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_rma_reset.940633897
Short name	T98
Test name
Test status
Simulation time	290289161900 ps
CPU time	981.51 seconds
Started	Jul 16 05:33:29 PM PDT 24
Finished	Jul 16 05:49:51 PM PDT 24
Peak memory	260904 kb
Host	smart-d8440863-fb1e-45ab-857f-afcf44d2152d
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940633897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.flash_ctrl_hw_rma_reset.940633897
Directory	/workspace/15.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_sec_otp.2095999410
Short name	T712
Test name
Test status
Simulation time	2512196100 ps
CPU time	203.98 seconds
Started	Jul 16 05:33:27 PM PDT 24
Finished	Jul 16 05:36:52 PM PDT 24
Peak memory	262776 kb
Host	smart-ba4bfe15-e8b0-4aa6-9193-73f82737d471
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095999410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ hw_sec_otp.2095999410
Directory	/workspace/15.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd.3105768701
Short name	T20
Test name
Test status
Simulation time	1575158700 ps
CPU time	205.28 seconds
Started	Jul 16 05:33:30 PM PDT 24
Finished	Jul 16 05:36:56 PM PDT 24
Peak memory	284812 kb
Host	smart-d3e350dd-fb6b-46a8-830e-401fa8702a3f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105768701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_intr_rd.3105768701
Directory	/workspace/15.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3481715090
Short name	T1077
Test name
Test status
Simulation time	13300707500 ps
CPU time	303.74 seconds
Started	Jul 16 05:33:29 PM PDT 24
Finished	Jul 16 05:38:33 PM PDT 24
Peak memory	293916 kb
Host	smart-9508e60f-860b-43bb-ad6e-fbec431d58a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481715090 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.3481715090
Directory	/workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/15.flash_ctrl_invalid_op.1239737604
Short name	T622
Test name
Test status
Simulation time	7049570800 ps
CPU time	79.01 seconds
Started	Jul 16 05:33:18 PM PDT 24
Finished	Jul 16 05:34:38 PM PDT 24
Peak memory	262660 kb
Host	smart-af261285-a569-4d1c-960e-7d032c0464a5
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239737604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1 239737604
Directory	/workspace/15.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.1932284870
Short name	T662
Test name
Test status
Simulation time	48575200 ps
CPU time	13.52 seconds
Started	Jul 16 05:36:46 PM PDT 24
Finished	Jul 16 05:37:01 PM PDT 24
Peak memory	260000 kb
Host	smart-daa1788f-407a-404a-a38d-f514e16fbd0f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932284870 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.1932284870
Directory	/workspace/15.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/15.flash_ctrl_mp_regions.378920895
Short name	T124
Test name
Test status
Simulation time	12956993800 ps
CPU time	297.27 seconds
Started	Jul 16 05:36:37 PM PDT 24
Finished	Jul 16 05:41:36 PM PDT 24
Peak memory	274696 kb
Host	smart-a135258b-8545-4b38-a96e-f75c7b5ca9eb
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378920895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.378920895
Directory	/workspace/15.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/15.flash_ctrl_otp_reset.974762554
Short name	T66
Test name
Test status
Simulation time	133512500 ps
CPU time	131.83 seconds
Started	Jul 16 05:33:26 PM PDT 24
Finished	Jul 16 05:35:38 PM PDT 24
Peak memory	261148 kb
Host	smart-3d415965-96cf-4af6-9bcc-53e1271580ab
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974762554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ot p_reset.974762554
Directory	/workspace/15.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_phy_arb.190816199
Short name	T1104
Test name
Test status
Simulation time	863995300 ps
CPU time	167.34 seconds
Started	Jul 16 05:36:46 PM PDT 24
Finished	Jul 16 05:39:34 PM PDT 24
Peak memory	263276 kb
Host	smart-324e47d2-ac86-4fc8-a370-b3cd860fd9ee
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=190816199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.190816199
Directory	/workspace/15.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/15.flash_ctrl_prog_reset.2870988210
Short name	T713
Test name
Test status
Simulation time	67236900 ps
CPU time	13.38 seconds
Started	Jul 16 05:36:37 PM PDT 24
Finished	Jul 16 05:36:52 PM PDT 24
Peak memory	265204 kb
Host	smart-c8bfed54-4851-439e-9ac0-c99e7e40f7f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870988210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.flash_ctrl_prog_reset.2870988210
Directory	/workspace/15.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rand_ops.2104560291
Short name	T1050
Test name
Test status
Simulation time	3631900500 ps
CPU time	169.45 seconds
Started	Jul 16 05:33:29 PM PDT 24
Finished	Jul 16 05:36:19 PM PDT 24
Peak memory	279432 kb
Host	smart-70c2734d-fe2d-41eb-9bb8-77b5754e4964
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104560291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.2104560291
Directory	/workspace/15.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/15.flash_ctrl_re_evict.3138619655
Short name	T354
Test name
Test status
Simulation time	237270600 ps
CPU time	34.86 seconds
Started	Jul 16 05:33:26 PM PDT 24
Finished	Jul 16 05:34:01 PM PDT 24
Peak memory	275688 kb
Host	smart-d63858a3-5a6b-4d98-8ca6-94d146fa1747
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138619655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_re_evict.3138619655
Directory	/workspace/15.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_ro.4046473285
Short name	T651
Test name
Test status
Simulation time	578807000 ps
CPU time	118.01 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:39:02 PM PDT 24
Peak memory	281048 kb
Host	smart-9617e5db-6543-4e88-98c5-da124919e046
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046473285 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 15.flash_ctrl_ro.4046473285
Directory	/workspace/15.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.1062314689
Short name	T360
Test name
Test status
Simulation time	50034000 ps
CPU time	28.18 seconds
Started	Jul 16 05:33:18 PM PDT 24
Finished	Jul 16 05:33:47 PM PDT 24
Peak memory	275544 kb
Host	smart-7c4939ef-fdc4-4818-82bf-29929023fa8f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062314689 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.1062314689
Directory	/workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/15.flash_ctrl_sec_info_access.762365297
Short name	T1032
Test name
Test status
Simulation time	1421923100 ps
CPU time	68.73 seconds
Started	Jul 16 05:37:21 PM PDT 24
Finished	Jul 16 05:38:31 PM PDT 24
Peak memory	263896 kb
Host	smart-d074697b-f005-4a83-9182-9f78c7ca3315
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762365297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.762365297
Directory	/workspace/15.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/15.flash_ctrl_smoke.1924955982
Short name	T693
Test name
Test status
Simulation time	30930400 ps
CPU time	100.94 seconds
Started	Jul 16 05:33:20 PM PDT 24
Finished	Jul 16 05:35:01 PM PDT 24
Peak memory	275864 kb
Host	smart-0ea06284-1107-42cb-b5de-72b8541d7834
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924955982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1924955982
Directory	/workspace/15.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.flash_ctrl_wo.3008206459
Short name	T803
Test name
Test status
Simulation time	4637749700 ps
CPU time	195.74 seconds
Started	Jul 16 05:33:29 PM PDT 24
Finished	Jul 16 05:36:45 PM PDT 24
Peak memory	265328 kb
Host	smart-5761321a-e2a0-44a4-a57c-e94f0ef8cd70
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008206459 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.flash_ctrl_wo.3008206459
Directory	/workspace/15.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/16.flash_ctrl_alert_test.2124711000
Short name	T656
Test name
Test status
Simulation time	106936600 ps
CPU time	14.05 seconds
Started	Jul 16 05:33:45 PM PDT 24
Finished	Jul 16 05:33:59 PM PDT 24
Peak memory	265152 kb
Host	smart-dd3fc9d7-f72e-4840-92ce-c420293b5dcb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124711000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test. 2124711000
Directory	/workspace/16.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.flash_ctrl_connect.1147067507
Short name	T731
Test name
Test status
Simulation time	28812200 ps
CPU time	16.13 seconds
Started	Jul 16 05:33:40 PM PDT 24
Finished	Jul 16 05:33:57 PM PDT 24
Peak memory	274920 kb
Host	smart-3198335d-cb07-461a-bb6a-4bc4d958272d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1147067507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1147067507
Directory	/workspace/16.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/16.flash_ctrl_disable.1910496062
Short name	T375
Test name
Test status
Simulation time	94074700 ps
CPU time	21.49 seconds
Started	Jul 16 05:36:51 PM PDT 24
Finished	Jul 16 05:37:14 PM PDT 24
Peak memory	273508 kb
Host	smart-b8dfb8be-7afe-49a8-bb85-04a1f6edff04
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910496062 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_disable.1910496062
Directory	/workspace/16.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2608374734
Short name	T242
Test name
Test status
Simulation time	10067103600 ps
CPU time	40.24 seconds
Started	Jul 16 05:33:43 PM PDT 24
Finished	Jul 16 05:34:24 PM PDT 24
Peak memory	270224 kb
Host	smart-5bfa4c09-5ce0-463c-aeee-2d5f1d79f14c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608374734 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2608374734
Directory	/workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.874766798
Short name	T189
Test name
Test status
Simulation time	15983300 ps
CPU time	13.29 seconds
Started	Jul 16 05:33:44 PM PDT 24
Finished	Jul 16 05:33:58 PM PDT 24
Peak memory	258296 kb
Host	smart-9cf35e60-206b-4363-a307-807d45614c27
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874766798 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.874766798
Directory	/workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_rma_reset.4136375584
Short name	T1082
Test name
Test status
Simulation time	40117227900 ps
CPU time	842.22 seconds
Started	Jul 16 05:37:21 PM PDT 24
Finished	Jul 16 05:51:24 PM PDT 24
Peak memory	264312 kb
Host	smart-26e95041-9d99-4015-876b-d509b356c9f9
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136375584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 16.flash_ctrl_hw_rma_reset.4136375584
Directory	/workspace/16.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3678840697
Short name	T608
Test name
Test status
Simulation time	16938709600 ps
CPU time	171.79 seconds
Started	Jul 16 05:33:30 PM PDT 24
Finished	Jul 16 05:36:23 PM PDT 24
Peak memory	260896 kb
Host	smart-1232cc06-a383-4236-a91b-c546762f5021
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678840697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ hw_sec_otp.3678840697
Directory	/workspace/16.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/16.flash_ctrl_invalid_op.3340363513
Short name	T523
Test name
Test status
Simulation time	3881424500 ps
CPU time	66.49 seconds
Started	Jul 16 05:33:31 PM PDT 24
Finished	Jul 16 05:34:38 PM PDT 24
Peak memory	263176 kb
Host	smart-cbefec33-0647-4ad9-8576-d029f87bdc23
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340363513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3 340363513
Directory	/workspace/16.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/16.flash_ctrl_lcmgr_intg.794082995
Short name	T635
Test name
Test status
Simulation time	45975400 ps
CPU time	13.42 seconds
Started	Jul 16 05:33:39 PM PDT 24
Finished	Jul 16 05:33:53 PM PDT 24
Peak memory	260756 kb
Host	smart-cc029e0d-00b7-4eee-a59a-bb4b8b62fdee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794082995 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.794082995
Directory	/workspace/16.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/16.flash_ctrl_mp_regions.2364509702
Short name	T1112
Test name
Test status
Simulation time	7561914300 ps
CPU time	237.56 seconds
Started	Jul 16 05:33:27 PM PDT 24
Finished	Jul 16 05:37:25 PM PDT 24
Peak memory	273948 kb
Host	smart-394a5439-bed3-434b-988a-137e13a87cf0
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364509702 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.2364509702
Directory	/workspace/16.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/16.flash_ctrl_otp_reset.3726770669
Short name	T850
Test name
Test status
Simulation time	581772900 ps
CPU time	112.08 seconds
Started	Jul 16 05:33:32 PM PDT 24
Finished	Jul 16 05:35:25 PM PDT 24
Peak memory	261060 kb
Host	smart-cc843d0f-5f1c-4907-9765-b625a3c1f5a4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726770669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o tp_reset.3726770669
Directory	/workspace/16.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_phy_arb.2912746120
Short name	T1041
Test name
Test status
Simulation time	68710800 ps
CPU time	361.54 seconds
Started	Jul 16 05:33:31 PM PDT 24
Finished	Jul 16 05:39:33 PM PDT 24
Peak memory	263180 kb
Host	smart-18c55396-283a-40cd-9ecc-a4c80a929fb2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2912746120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.2912746120
Directory	/workspace/16.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/16.flash_ctrl_prog_reset.3243808204
Short name	T964
Test name
Test status
Simulation time	34098800 ps
CPU time	13.63 seconds
Started	Jul 16 05:36:37 PM PDT 24
Finished	Jul 16 05:36:52 PM PDT 24
Peak memory	259008 kb
Host	smart-fa9d4c28-d538-4bcb-8192-fe4d7795c744
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243808204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.flash_ctrl_prog_reset.3243808204
Directory	/workspace/16.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rand_ops.756509589
Short name	T1083
Test name
Test status
Simulation time	66461000 ps
CPU time	560.5 seconds
Started	Jul 16 05:33:30 PM PDT 24
Finished	Jul 16 05:42:51 PM PDT 24
Peak memory	284344 kb
Host	smart-fab2aba3-878b-42b2-8bd8-29bc69502bac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756509589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.756509589
Directory	/workspace/16.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/16.flash_ctrl_re_evict.3530050721
Short name	T1078
Test name
Test status
Simulation time	127152800 ps
CPU time	33.98 seconds
Started	Jul 16 05:37:18 PM PDT 24
Finished	Jul 16 05:37:53 PM PDT 24
Peak memory	275596 kb
Host	smart-62629efc-438f-4202-a0e3-7d2932d57a54
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530050721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl ash_ctrl_re_evict.3530050721
Directory	/workspace/16.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_ro.2116290411
Short name	T603
Test name
Test status
Simulation time	2214979800 ps
CPU time	110.15 seconds
Started	Jul 16 05:36:48 PM PDT 24
Finished	Jul 16 05:38:39 PM PDT 24
Peak memory	291536 kb
Host	smart-61543c23-4cb0-4de2-b8f4-a61d6d71387e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116290411 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 16.flash_ctrl_ro.2116290411
Directory	/workspace/16.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw.1485120800
Short name	T853
Test name
Test status
Simulation time	3632668600 ps
CPU time	529.78 seconds
Started	Jul 16 05:33:33 PM PDT 24
Finished	Jul 16 05:42:23 PM PDT 24
Peak memory	314580 kb
Host	smart-42f455b3-368d-4356-9b32-ab318dcf28bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485120800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.flash_ctrl_rw.1485120800
Directory	/workspace/16.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict.3764744061
Short name	T932
Test name
Test status
Simulation time	74988300 ps
CPU time	30.64 seconds
Started	Jul 16 05:33:28 PM PDT 24
Finished	Jul 16 05:34:00 PM PDT 24
Peak memory	275760 kb
Host	smart-6ebaa0f3-4d94-444e-909e-28172bedc48e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764744061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl ash_ctrl_rw_evict.3764744061
Directory	/workspace/16.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_sec_info_access.1553840616
Short name	T800
Test name
Test status
Simulation time	7187943900 ps
CPU time	65.39 seconds
Started	Jul 16 05:33:40 PM PDT 24
Finished	Jul 16 05:34:46 PM PDT 24
Peak memory	262060 kb
Host	smart-7cb7a99e-cfb0-42b8-b2a4-83a935ae751d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553840616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.1553840616
Directory	/workspace/16.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/16.flash_ctrl_smoke.1957587593
Short name	T719
Test name
Test status
Simulation time	25837500 ps
CPU time	97.29 seconds
Started	Jul 16 05:33:30 PM PDT 24
Finished	Jul 16 05:35:08 PM PDT 24
Peak memory	275880 kb
Host	smart-042fa22c-8e05-4645-a53d-35e57c01360d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957587593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1957587593
Directory	/workspace/16.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.flash_ctrl_wo.2201136926
Short name	T1046
Test name
Test status
Simulation time	2354677000 ps
CPU time	189.37 seconds
Started	Jul 16 05:33:29 PM PDT 24
Finished	Jul 16 05:36:39 PM PDT 24
Peak memory	265084 kb
Host	smart-9dde5fdf-042e-4dda-a81a-821cd84eaaa5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201136926 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.flash_ctrl_wo.2201136926
Directory	/workspace/16.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/17.flash_ctrl_alert_test.1003156283
Short name	T552
Test name
Test status
Simulation time	140419100 ps
CPU time	13.92 seconds
Started	Jul 16 05:33:50 PM PDT 24
Finished	Jul 16 05:34:04 PM PDT 24
Peak memory	265184 kb
Host	smart-785e50ca-405e-49e6-809e-dfc98c1ac033
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003156283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test. 1003156283
Directory	/workspace/17.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.flash_ctrl_connect.3152014365
Short name	T493
Test name
Test status
Simulation time	32935600 ps
CPU time	16.37 seconds
Started	Jul 16 05:33:47 PM PDT 24
Finished	Jul 16 05:34:04 PM PDT 24
Peak memory	284248 kb
Host	smart-2ef52a1e-0bf6-4929-bbb1-0b502a8aca1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152014365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.3152014365
Directory	/workspace/17.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/17.flash_ctrl_disable.3921372943
Short name	T885
Test name
Test status
Simulation time	16422400 ps
CPU time	21.62 seconds
Started	Jul 16 05:33:49 PM PDT 24
Finished	Jul 16 05:34:11 PM PDT 24
Peak memory	273520 kb
Host	smart-ad5feaac-c256-4f29-8ee6-493fb76bf62d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921372943 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_disable.3921372943
Directory	/workspace/17.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.1021377589
Short name	T161
Test name
Test status
Simulation time	10013014500 ps
CPU time	325.61 seconds
Started	Jul 16 05:33:55 PM PDT 24
Finished	Jul 16 05:39:21 PM PDT 24
Peak memory	324848 kb
Host	smart-2de1d4e7-b3fe-4359-a779-17ca6c7c8539
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021377589 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.1021377589
Directory	/workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.3813981964
Short name	T880
Test name
Test status
Simulation time	37470600 ps
CPU time	13.73 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:37:17 PM PDT 24
Peak memory	258664 kb
Host	smart-b2569395-653d-4f7d-9508-8314c3a22d8e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813981964 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.3813981964
Directory	/workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2790812405
Short name	T1103
Test name
Test status
Simulation time	60128226300 ps
CPU time	856.6 seconds
Started	Jul 16 05:33:43 PM PDT 24
Finished	Jul 16 05:48:00 PM PDT 24
Peak memory	264476 kb
Host	smart-f8248277-7ab2-417d-9c67-1c2b63538dcf
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790812405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 17.flash_ctrl_hw_rma_reset.2790812405
Directory	/workspace/17.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.1611838061
Short name	T866
Test name
Test status
Simulation time	1689017400 ps
CPU time	122.15 seconds
Started	Jul 16 05:36:18 PM PDT 24
Finished	Jul 16 05:38:21 PM PDT 24
Peak memory	262808 kb
Host	smart-8eab62a6-c00a-49b3-a2f5-3e53a8fbb0be
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611838061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ hw_sec_otp.1611838061
Directory	/workspace/17.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd.360098685
Short name	T988
Test name
Test status
Simulation time	8322066900 ps
CPU time	238.89 seconds
Started	Jul 16 05:36:51 PM PDT 24
Finished	Jul 16 05:40:51 PM PDT 24
Peak memory	291276 kb
Host	smart-fc3f976d-2111-467a-94c4-32a40016b96f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360098685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flas h_ctrl_intr_rd.360098685
Directory	/workspace/17.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.3215619969
Short name	T839
Test name
Test status
Simulation time	24542316100 ps
CPU time	303.2 seconds
Started	Jul 16 05:33:51 PM PDT 24
Finished	Jul 16 05:38:54 PM PDT 24
Peak memory	291872 kb
Host	smart-8ea9e9a1-686a-43f5-87f4-af2d11cf932a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215619969 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.3215619969
Directory	/workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.589061886
Short name	T288
Test name
Test status
Simulation time	14976800 ps
CPU time	13.38 seconds
Started	Jul 16 05:33:46 PM PDT 24
Finished	Jul 16 05:33:59 PM PDT 24
Peak memory	259992 kb
Host	smart-1b1ea2a6-d762-4c1a-9070-c3a61ef092e4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589061886 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.589061886
Directory	/workspace/17.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/17.flash_ctrl_mp_regions.2552672734
Short name	T1004
Test name
Test status
Simulation time	4056571500 ps
CPU time	174.98 seconds
Started	Jul 16 05:33:46 PM PDT 24
Finished	Jul 16 05:36:42 PM PDT 24
Peak memory	265080 kb
Host	smart-193b7bfa-a7dd-4986-9407-20e4caa225a4
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552672734 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.2552672734
Directory	/workspace/17.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/17.flash_ctrl_phy_arb.720611862
Short name	T218
Test name
Test status
Simulation time	756263800 ps
CPU time	414.06 seconds
Started	Jul 16 05:33:41 PM PDT 24
Finished	Jul 16 05:40:35 PM PDT 24
Peak memory	263148 kb
Host	smart-114f16b5-1837-430b-8414-0e337b637123
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=720611862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.720611862
Directory	/workspace/17.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/17.flash_ctrl_prog_reset.2809182639
Short name	T3
Test name
Test status
Simulation time	20917600 ps
CPU time	13.48 seconds
Started	Jul 16 05:33:48 PM PDT 24
Finished	Jul 16 05:34:01 PM PDT 24
Peak memory	265328 kb
Host	smart-92589e41-eed8-4186-8c84-52d90da6004f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809182639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.flash_ctrl_prog_reset.2809182639
Directory	/workspace/17.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rand_ops.3708426019
Short name	T796
Test name
Test status
Simulation time	105549100 ps
CPU time	877.66 seconds
Started	Jul 16 05:33:41 PM PDT 24
Finished	Jul 16 05:48:20 PM PDT 24
Peak memory	285296 kb
Host	smart-3bd870f0-21c9-40c3-9ad2-cd7560dd9181
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708426019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.3708426019
Directory	/workspace/17.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw.1050578184
Short name	T987
Test name
Test status
Simulation time	5095797600 ps
CPU time	610.95 seconds
Started	Jul 16 05:33:39 PM PDT 24
Finished	Jul 16 05:43:50 PM PDT 24
Peak memory	326108 kb
Host	smart-e84bd323-e29e-44c9-b5e3-cc528f456406
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050578184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.flash_ctrl_rw.1050578184
Directory	/workspace/17.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict.2779177862
Short name	T958
Test name
Test status
Simulation time	29267500 ps
CPU time	28.65 seconds
Started	Jul 16 05:33:51 PM PDT 24
Finished	Jul 16 05:34:20 PM PDT 24
Peak memory	275624 kb
Host	smart-81afa813-97f6-4b5e-9794-025fa62e1393
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779177862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl ash_ctrl_rw_evict.2779177862
Directory	/workspace/17.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.1931026099
Short name	T738
Test name
Test status
Simulation time	235647000 ps
CPU time	30.68 seconds
Started	Jul 16 05:34:55 PM PDT 24
Finished	Jul 16 05:35:26 PM PDT 24
Peak memory	268160 kb
Host	smart-214eaf17-37a6-4d91-b3c6-3e676031fc95
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931026099 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.1931026099
Directory	/workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/17.flash_ctrl_sec_info_access.954061169
Short name	T920
Test name
Test status
Simulation time	1008816100 ps
CPU time	61.92 seconds
Started	Jul 16 05:33:54 PM PDT 24
Finished	Jul 16 05:34:56 PM PDT 24
Peak memory	264752 kb
Host	smart-b066bcaa-c1ae-4f20-a471-2e62aa2e102a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954061169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.954061169
Directory	/workspace/17.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/17.flash_ctrl_smoke.275352640
Short name	T755
Test name
Test status
Simulation time	17656900 ps
CPU time	124.34 seconds
Started	Jul 16 05:36:47 PM PDT 24
Finished	Jul 16 05:38:52 PM PDT 24
Peak memory	277296 kb
Host	smart-a5e4f625-7a59-4d39-b301-15bac5a45038
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275352640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.275352640
Directory	/workspace/17.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.flash_ctrl_wo.926144597
Short name	T818
Test name
Test status
Simulation time	9258097700 ps
CPU time	199.01 seconds
Started	Jul 16 05:33:44 PM PDT 24
Finished	Jul 16 05:37:03 PM PDT 24
Peak memory	265248 kb
Host	smart-bf7fa5e2-32fe-43e7-ae6c-a5928df3b69a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926144597 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 17.flash_ctrl_wo.926144597
Directory	/workspace/17.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/18.flash_ctrl_alert_test.2885338314
Short name	T419
Test name
Test status
Simulation time	40498100 ps
CPU time	13.53 seconds
Started	Jul 16 05:34:09 PM PDT 24
Finished	Jul 16 05:34:23 PM PDT 24
Peak memory	265192 kb
Host	smart-1f864dbf-ea62-4675-a184-6922ab150f0a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885338314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test. 2885338314
Directory	/workspace/18.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.flash_ctrl_connect.1420849667
Short name	T492
Test name
Test status
Simulation time	36655500 ps
CPU time	16.13 seconds
Started	Jul 16 05:37:10 PM PDT 24
Finished	Jul 16 05:37:27 PM PDT 24
Peak memory	274920 kb
Host	smart-b1e4b3b1-e366-4ab0-b997-7d0d188cd0fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420849667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.1420849667
Directory	/workspace/18.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/18.flash_ctrl_disable.1498178101
Short name	T787
Test name
Test status
Simulation time	12998400 ps
CPU time	21.58 seconds
Started	Jul 16 05:34:08 PM PDT 24
Finished	Jul 16 05:34:30 PM PDT 24
Peak memory	273512 kb
Host	smart-06b98b4e-8c24-48d1-a458-12177c630e2e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498178101 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_disable.1498178101
Directory	/workspace/18.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3158785182
Short name	T786
Test name
Test status
Simulation time	10018518900 ps
CPU time	82.15 seconds
Started	Jul 16 05:34:08 PM PDT 24
Finished	Jul 16 05:35:30 PM PDT 24
Peak memory	293456 kb
Host	smart-f4fa2b19-8a87-4b8c-a992-7845141a25ee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158785182 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3158785182
Directory	/workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.56031732
Short name	T282
Test name
Test status
Simulation time	15814400 ps
CPU time	13.35 seconds
Started	Jul 16 05:34:07 PM PDT 24
Finished	Jul 16 05:34:21 PM PDT 24
Peak memory	264960 kb
Host	smart-776e201b-c502-4796-981f-a711218ec469
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56031732 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.56031732
Directory	/workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_rma_reset.1406945634
Short name	T159
Test name
Test status
Simulation time	40122914600 ps
CPU time	799.31 seconds
Started	Jul 16 05:33:58 PM PDT 24
Finished	Jul 16 05:47:18 PM PDT 24
Peak memory	264344 kb
Host	smart-0ad63b76-0c9f-4779-a235-e087407a8931
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406945634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 18.flash_ctrl_hw_rma_reset.1406945634
Directory	/workspace/18.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.245197615
Short name	T678
Test name
Test status
Simulation time	5817254000 ps
CPU time	125.65 seconds
Started	Jul 16 05:33:56 PM PDT 24
Finished	Jul 16 05:36:02 PM PDT 24
Peak memory	263112 kb
Host	smart-adc80274-8592-475c-81ac-269d2b7e0a35
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245197615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_h w_sec_otp.245197615
Directory	/workspace/18.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd.709754491
Short name	T1055
Test name
Test status
Simulation time	4672625700 ps
CPU time	134.88 seconds
Started	Jul 16 05:34:07 PM PDT 24
Finished	Jul 16 05:36:22 PM PDT 24
Peak memory	293584 kb
Host	smart-51f24338-75e7-4667-b762-21c96057f0f1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709754491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flas h_ctrl_intr_rd.709754491
Directory	/workspace/18.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.914779387
Short name	T538
Test name
Test status
Simulation time	22171400300 ps
CPU time	130.79 seconds
Started	Jul 16 05:34:08 PM PDT 24
Finished	Jul 16 05:36:20 PM PDT 24
Peak memory	292984 kb
Host	smart-6ac73e38-0094-41e6-b82d-840a47164bf0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914779387 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.914779387
Directory	/workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/18.flash_ctrl_invalid_op.369853002
Short name	T620
Test name
Test status
Simulation time	4272323300 ps
CPU time	68.74 seconds
Started	Jul 16 05:33:57 PM PDT 24
Finished	Jul 16 05:35:06 PM PDT 24
Peak memory	263352 kb
Host	smart-fdf81215-c1fe-455d-847c-d7126a0f1938
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369853002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.369853002
Directory	/workspace/18.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2677488414
Short name	T734
Test name
Test status
Simulation time	48718200 ps
CPU time	13.38 seconds
Started	Jul 16 05:34:06 PM PDT 24
Finished	Jul 16 05:34:20 PM PDT 24
Peak memory	264972 kb
Host	smart-aae388e3-d734-476b-a40f-db5139f1185a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677488414 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2677488414
Directory	/workspace/18.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/18.flash_ctrl_mp_regions.3471087831
Short name	T140
Test name
Test status
Simulation time	8111946100 ps
CPU time	564.69 seconds
Started	Jul 16 05:36:46 PM PDT 24
Finished	Jul 16 05:46:11 PM PDT 24
Peak memory	274696 kb
Host	smart-ce15115e-9379-4955-9049-925619ef32e6
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471087831 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.3471087831
Directory	/workspace/18.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/18.flash_ctrl_otp_reset.1086597445
Short name	T126
Test name
Test status
Simulation time	38631200 ps
CPU time	109.64 seconds
Started	Jul 16 05:33:56 PM PDT 24
Finished	Jul 16 05:35:46 PM PDT 24
Peak memory	260208 kb
Host	smart-ecf60faf-18c5-4f1d-98cf-af2da132aa47
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086597445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o tp_reset.1086597445
Directory	/workspace/18.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_phy_arb.2119532863
Short name	T1033
Test name
Test status
Simulation time	2785931600 ps
CPU time	390.82 seconds
Started	Jul 16 05:33:47 PM PDT 24
Finished	Jul 16 05:40:18 PM PDT 24
Peak memory	263092 kb
Host	smart-18a09e2a-115c-4fec-b640-8d3b48b6beea
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2119532863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2119532863
Directory	/workspace/18.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/18.flash_ctrl_prog_reset.2151074962
Short name	T307
Test name
Test status
Simulation time	3496786300 ps
CPU time	184.8 seconds
Started	Jul 16 05:34:08 PM PDT 24
Finished	Jul 16 05:37:14 PM PDT 24
Peak memory	260592 kb
Host	smart-ee4a4dbe-176f-4fb4-83f1-f8f42cfc3407
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151074962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.flash_ctrl_prog_reset.2151074962
Directory	/workspace/18.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rand_ops.1985128670
Short name	T748
Test name
Test status
Simulation time	6238849800 ps
CPU time	899.63 seconds
Started	Jul 16 05:33:51 PM PDT 24
Finished	Jul 16 05:48:51 PM PDT 24
Peak memory	289032 kb
Host	smart-2b74799f-e922-4200-af0a-d903d8d92887
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985128670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1985128670
Directory	/workspace/18.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/18.flash_ctrl_re_evict.3203057707
Short name	T644
Test name
Test status
Simulation time	59700400 ps
CPU time	31.09 seconds
Started	Jul 16 05:34:05 PM PDT 24
Finished	Jul 16 05:34:37 PM PDT 24
Peak memory	275624 kb
Host	smart-6a7ea6ec-0928-43f3-a72b-3eca29a96cc4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203057707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_re_evict.3203057707
Directory	/workspace/18.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_ro.3445128993
Short name	T674
Test name
Test status
Simulation time	513628700 ps
CPU time	108.75 seconds
Started	Jul 16 05:33:57 PM PDT 24
Finished	Jul 16 05:35:46 PM PDT 24
Peak memory	281744 kb
Host	smart-e76a3ab1-4dcf-4e45-9a88-ba4b26037cad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445128993 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 18.flash_ctrl_ro.3445128993
Directory	/workspace/18.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw.3721319637
Short name	T833
Test name
Test status
Simulation time	17630976900 ps
CPU time	506.74 seconds
Started	Jul 16 05:34:06 PM PDT 24
Finished	Jul 16 05:42:33 PM PDT 24
Peak memory	310784 kb
Host	smart-53f08cd5-911c-439f-abf8-13d7b1c3db7e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721319637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.flash_ctrl_rw.3721319637
Directory	/workspace/18.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict.1793192415
Short name	T861
Test name
Test status
Simulation time	58804300 ps
CPU time	29.86 seconds
Started	Jul 16 05:34:08 PM PDT 24
Finished	Jul 16 05:34:39 PM PDT 24
Peak memory	273548 kb
Host	smart-bb0bc364-0491-44bb-afc0-b1347c606803
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793192415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_rw_evict.1793192415
Directory	/workspace/18.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2680926362
Short name	T697
Test name
Test status
Simulation time	27669100 ps
CPU time	31.17 seconds
Started	Jul 16 05:34:08 PM PDT 24
Finished	Jul 16 05:34:40 PM PDT 24
Peak memory	275560 kb
Host	smart-fd711fe1-b7af-4245-965e-18819ba7bc98
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680926362 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.2680926362
Directory	/workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/18.flash_ctrl_smoke.2587459357
Short name	T231
Test name
Test status
Simulation time	144366900 ps
CPU time	149.65 seconds
Started	Jul 16 05:33:51 PM PDT 24
Finished	Jul 16 05:36:21 PM PDT 24
Peak memory	268736 kb
Host	smart-b03a2c38-4021-4300-9dcf-ae93303586eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587459357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2587459357
Directory	/workspace/18.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.flash_ctrl_wo.246079501
Short name	T463
Test name
Test status
Simulation time	34754520600 ps
CPU time	237.28 seconds
Started	Jul 16 05:34:00 PM PDT 24
Finished	Jul 16 05:37:57 PM PDT 24
Peak memory	260044 kb
Host	smart-b3409af8-0154-414c-a6a6-4044aef9731e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246079501 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 18.flash_ctrl_wo.246079501
Directory	/workspace/18.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/19.flash_ctrl_alert_test.1453851513
Short name	T468
Test name
Test status
Simulation time	79787500 ps
CPU time	13.62 seconds
Started	Jul 16 05:34:26 PM PDT 24
Finished	Jul 16 05:34:40 PM PDT 24
Peak memory	258256 kb
Host	smart-b4423e4f-1e83-4ab2-ac4f-6a411fe6de98
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453851513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test. 1453851513
Directory	/workspace/19.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.flash_ctrl_connect.377650002
Short name	T19
Test name
Test status
Simulation time	23488000 ps
CPU time	15.91 seconds
Started	Jul 16 05:34:17 PM PDT 24
Finished	Jul 16 05:34:34 PM PDT 24
Peak memory	284348 kb
Host	smart-81ffedf6-1586-4704-8739-9fc87d248bde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=377650002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.377650002
Directory	/workspace/19.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/19.flash_ctrl_disable.2716732678
Short name	T176
Test name
Test status
Simulation time	25429300 ps
CPU time	20.08 seconds
Started	Jul 16 05:34:16 PM PDT 24
Finished	Jul 16 05:34:36 PM PDT 24
Peak memory	273508 kb
Host	smart-740d4649-d84e-4a0b-a244-a6197231f268
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716732678 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_disable.2716732678
Directory	/workspace/19.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3778400768
Short name	T114
Test name
Test status
Simulation time	10156672300 ps
CPU time	42.22 seconds
Started	Jul 16 05:34:29 PM PDT 24
Finished	Jul 16 05:35:12 PM PDT 24
Peak memory	265272 kb
Host	smart-a0bd7af0-f48e-4343-9803-46e7aac32a25
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778400768 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.3778400768
Directory	/workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1738526899
Short name	T766
Test name
Test status
Simulation time	19783700 ps
CPU time	13.56 seconds
Started	Jul 16 05:34:19 PM PDT 24
Finished	Jul 16 05:34:33 PM PDT 24
Peak memory	264904 kb
Host	smart-b45525c0-d864-4dcc-9f97-547ec3230d3e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738526899 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1738526899
Directory	/workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_rma_reset.3714660740
Short name	T894
Test name
Test status
Simulation time	50124411500 ps
CPU time	881.9 seconds
Started	Jul 16 05:34:14 PM PDT 24
Finished	Jul 16 05:48:57 PM PDT 24
Peak memory	264312 kb
Host	smart-da1511f6-4476-4c11-bac8-072ad345b1f4
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714660740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.flash_ctrl_hw_rma_reset.3714660740
Directory	/workspace/19.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.3885591150
Short name	T1073
Test name
Test status
Simulation time	3167140900 ps
CPU time	243.79 seconds
Started	Jul 16 05:35:15 PM PDT 24
Finished	Jul 16 05:39:20 PM PDT 24
Peak memory	260744 kb
Host	smart-e6b88bc2-242a-49ab-81f4-dd7a3a490224
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885591150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ hw_sec_otp.3885591150
Directory	/workspace/19.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd.2768298769
Short name	T1000
Test name
Test status
Simulation time	2863296800 ps
CPU time	183.41 seconds
Started	Jul 16 05:34:18 PM PDT 24
Finished	Jul 16 05:37:22 PM PDT 24
Peak memory	284932 kb
Host	smart-094c3948-1901-4d65-8a40-ee40d3fe205b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768298769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_intr_rd.2768298769
Directory	/workspace/19.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.842181720
Short name	T854
Test name
Test status
Simulation time	6092101600 ps
CPU time	123.24 seconds
Started	Jul 16 05:34:18 PM PDT 24
Finished	Jul 16 05:36:22 PM PDT 24
Peak memory	293124 kb
Host	smart-ffe4f1d2-0dca-4875-8f5c-d7216b82b2fe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842181720 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.842181720
Directory	/workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/19.flash_ctrl_invalid_op.322368049
Short name	T927
Test name
Test status
Simulation time	3757910200 ps
CPU time	59.92 seconds
Started	Jul 16 05:34:22 PM PDT 24
Finished	Jul 16 05:35:23 PM PDT 24
Peak memory	262936 kb
Host	smart-5115e0c0-5aef-43f9-832f-6874170b0db1
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322368049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.322368049
Directory	/workspace/19.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.2168304570
Short name	T663
Test name
Test status
Simulation time	15809000 ps
CPU time	13.68 seconds
Started	Jul 16 05:34:17 PM PDT 24
Finished	Jul 16 05:34:31 PM PDT 24
Peak memory	265060 kb
Host	smart-952363fb-4ef8-4544-af34-bd7a3de5b203
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168304570 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.2168304570
Directory	/workspace/19.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/19.flash_ctrl_otp_reset.3361609177
Short name	T934
Test name
Test status
Simulation time	33331400 ps
CPU time	111.31 seconds
Started	Jul 16 05:36:47 PM PDT 24
Finished	Jul 16 05:38:39 PM PDT 24
Peak memory	264224 kb
Host	smart-90d6e59c-ffff-407b-ac6d-d1b99a6570c4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361609177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o tp_reset.3361609177
Directory	/workspace/19.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_phy_arb.1986435783
Short name	T547
Test name
Test status
Simulation time	1445573700 ps
CPU time	508.82 seconds
Started	Jul 16 05:34:18 PM PDT 24
Finished	Jul 16 05:42:47 PM PDT 24
Peak memory	263156 kb
Host	smart-2634f211-2894-495c-a2e9-8ab4f4d3ac01
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1986435783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1986435783
Directory	/workspace/19.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/19.flash_ctrl_prog_reset.4154268525
Short name	T857
Test name
Test status
Simulation time	20968600 ps
CPU time	13.3 seconds
Started	Jul 16 05:37:03 PM PDT 24
Finished	Jul 16 05:37:17 PM PDT 24
Peak memory	265272 kb
Host	smart-e26fb002-0989-4111-a374-f7ea9db0d9c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154268525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.flash_ctrl_prog_reset.4154268525
Directory	/workspace/19.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rand_ops.3020060675
Short name	T138
Test name
Test status
Simulation time	1608123100 ps
CPU time	1339.01 seconds
Started	Jul 16 05:34:08 PM PDT 24
Finished	Jul 16 05:56:28 PM PDT 24
Peak memory	284716 kb
Host	smart-38d9d5de-d5ef-4c3b-ba7c-433047321e99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020060675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.3020060675
Directory	/workspace/19.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/19.flash_ctrl_re_evict.202000815
Short name	T1037
Test name
Test status
Simulation time	62484400 ps
CPU time	31.19 seconds
Started	Jul 16 05:36:35 PM PDT 24
Finished	Jul 16 05:37:08 PM PDT 24
Peak memory	275336 kb
Host	smart-0a6e35d6-8bb2-4745-96b8-20ea69a493f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202000815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_re_evict.202000815
Directory	/workspace/19.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_ro.682562400
Short name	T870
Test name
Test status
Simulation time	630925300 ps
CPU time	108.8 seconds
Started	Jul 16 05:34:18 PM PDT 24
Finished	Jul 16 05:36:07 PM PDT 24
Peak memory	281708 kb
Host	smart-ccbedf17-3cff-4852-8c9c-c5e2a4390da9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682562400 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.flash_ctrl_ro.682562400
Directory	/workspace/19.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw.2424669714
Short name	T916
Test name
Test status
Simulation time	6763149400 ps
CPU time	512.55 seconds
Started	Jul 16 05:34:18 PM PDT 24
Finished	Jul 16 05:42:51 PM PDT 24
Peak memory	309768 kb
Host	smart-423d2446-a3b6-4aea-8a2d-d755859d4e9a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424669714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.flash_ctrl_rw.2424669714
Directory	/workspace/19.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict.155936580
Short name	T1054
Test name
Test status
Simulation time	29735700 ps
CPU time	30.63 seconds
Started	Jul 16 05:36:35 PM PDT 24
Finished	Jul 16 05:37:07 PM PDT 24
Peak memory	275604 kb
Host	smart-bbbf687f-161a-46ea-a5e7-124fb65120cd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155936580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_rw_evict.155936580
Directory	/workspace/19.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.2734552379
Short name	T24
Test name
Test status
Simulation time	74235900 ps
CPU time	28.99 seconds
Started	Jul 16 05:37:03 PM PDT 24
Finished	Jul 16 05:37:33 PM PDT 24
Peak memory	268480 kb
Host	smart-160766f5-1593-4854-846a-3da408eacfe3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734552379 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.2734552379
Directory	/workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/19.flash_ctrl_sec_info_access.3049187444
Short name	T412
Test name
Test status
Simulation time	2153223400 ps
CPU time	73.34 seconds
Started	Jul 16 05:34:17 PM PDT 24
Finished	Jul 16 05:35:31 PM PDT 24
Peak memory	263704 kb
Host	smart-299b317a-8fba-48f7-a677-5f92d8a0c762
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3049187444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3049187444
Directory	/workspace/19.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/19.flash_ctrl_smoke.553993517
Short name	T244
Test name
Test status
Simulation time	69178600 ps
CPU time	99.11 seconds
Started	Jul 16 05:34:08 PM PDT 24
Finished	Jul 16 05:35:48 PM PDT 24
Peak memory	276096 kb
Host	smart-68913c2f-b7d9-47ca-b7e4-731c5fa8206f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553993517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.553993517
Directory	/workspace/19.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.flash_ctrl_wo.3308454695
Short name	T502
Test name
Test status
Simulation time	12709742600 ps
CPU time	149.73 seconds
Started	Jul 16 05:34:17 PM PDT 24
Finished	Jul 16 05:36:47 PM PDT 24
Peak memory	265236 kb
Host	smart-46385ccb-a381-4f75-80a0-a8f09be0431f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308454695 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.flash_ctrl_wo.3308454695
Directory	/workspace/19.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_access_after_disable.4281533411
Short name	T23
Test name
Test status
Simulation time	23933000 ps
CPU time	13.57 seconds
Started	Jul 16 05:30:13 PM PDT 24
Finished	Jul 16 05:30:28 PM PDT 24
Peak memory	261292 kb
Host	smart-2ecdab91-a761-45e2-b8ff-8254b71e82fe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281533411 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.4281533411
Directory	/workspace/2.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_alert_test.1672009104
Short name	T997
Test name
Test status
Simulation time	141548100 ps
CPU time	13.63 seconds
Started	Jul 16 05:30:18 PM PDT 24
Finished	Jul 16 05:30:33 PM PDT 24
Peak memory	265184 kb
Host	smart-ea9bb950-e354-4a94-919e-31ff6ebaa069
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672009104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.1 672009104
Directory	/workspace/2.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.flash_ctrl_config_regwen.2933043187
Short name	T1106
Test name
Test status
Simulation time	41040600 ps
CPU time	13.81 seconds
Started	Jul 16 05:30:13 PM PDT 24
Finished	Jul 16 05:30:28 PM PDT 24
Peak memory	261492 kb
Host	smart-592224f9-4790-4a62-b992-ee30633deced
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933043187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .flash_ctrl_config_regwen.2933043187
Directory	/workspace/2.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/2.flash_ctrl_connect.3977466256
Short name	T480
Test name
Test status
Simulation time	78001500 ps
CPU time	13.19 seconds
Started	Jul 16 05:30:17 PM PDT 24
Finished	Jul 16 05:30:32 PM PDT 24
Peak memory	274924 kb
Host	smart-d12bc238-85af-4237-a874-a5bb3883b702
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3977466256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3977466256
Directory	/workspace/2.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/2.flash_ctrl_disable.815810910
Short name	T754
Test name
Test status
Simulation time	28395000 ps
CPU time	21.54 seconds
Started	Jul 16 05:30:17 PM PDT 24
Finished	Jul 16 05:30:40 PM PDT 24
Peak memory	265480 kb
Host	smart-7e68c6b7-14ce-41c7-8c75-54c79be2785a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815810910 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_disable.815810910
Directory	/workspace/2.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_erase_suspend.4293506202
Short name	T184
Test name
Test status
Simulation time	758338100 ps
CPU time	292.34 seconds
Started	Jul 16 05:34:53 PM PDT 24
Finished	Jul 16 05:39:46 PM PDT 24
Peak memory	263416 kb
Host	smart-230765b1-4ae9-42ed-bf6c-e04299a4d490
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4293506202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.4293506202
Directory	/workspace/2.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_mp.3891881836
Short name	T746
Test name
Test status
Simulation time	19993510100 ps
CPU time	2496.6 seconds
Started	Jul 16 05:29:55 PM PDT 24
Finished	Jul 16 06:11:32 PM PDT 24
Peak memory	265244 kb
Host	smart-76453af8-da78-4535-a6dc-2e0999b2080d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3891881836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.3891881836
Directory	/workspace/2.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_win.3514445276
Short name	T1006
Test name
Test status
Simulation time	1689620000 ps
CPU time	889.96 seconds
Started	Jul 16 05:30:03 PM PDT 24
Finished	Jul 16 05:44:54 PM PDT 24
Peak memory	273352 kb
Host	smart-194401d4-f813-473f-90eb-e7045ec87656
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514445276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.3514445276
Directory	/workspace/2.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fetch_code.3853769379
Short name	T45
Test name
Test status
Simulation time	442691500 ps
CPU time	20.92 seconds
Started	Jul 16 05:29:56 PM PDT 24
Finished	Jul 16 05:30:18 PM PDT 24
Peak memory	262504 kb
Host	smart-aef8c10f-3ecd-427a-9bf1-f8ddaba49a25
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853769379 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.3853769379
Directory	/workspace/2.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fs_sup.1260418591
Short name	T76
Test name
Test status
Simulation time	722549900 ps
CPU time	40.95 seconds
Started	Jul 16 05:30:08 PM PDT 24
Finished	Jul 16 05:30:50 PM PDT 24
Peak memory	263036 kb
Host	smart-e651ea3b-d665-4be5-8b58-0e710f7e0369
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260418591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.flash_ctrl_fs_sup.1260418591
Directory	/workspace/2.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/2.flash_ctrl_full_mem_access.1104143625
Short name	T900
Test name
Test status
Simulation time	94986064700 ps
CPU time	2549.46 seconds
Started	Jul 16 05:36:52 PM PDT 24
Finished	Jul 16 06:19:23 PM PDT 24
Peak memory	273232 kb
Host	smart-632bb53e-96a6-47d0-aa32-e104d39eb365
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104143625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c trl_full_mem_access.1104143625
Directory	/workspace/2.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_addr_infection.2229677399
Short name	T666
Test name
Test status
Simulation time	248865900 ps
CPU time	31 seconds
Started	Jul 16 05:32:25 PM PDT 24
Finished	Jul 16 05:32:57 PM PDT 24
Peak memory	268312 kb
Host	smart-5b3e099e-8c1b-43cb-990d-62dd8a3131cb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229677399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_host_addr_infection.2229677399
Directory	/workspace/2.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3998618229
Short name	T879
Test name
Test status
Simulation time	10036060600 ps
CPU time	99.76 seconds
Started	Jul 16 05:35:17 PM PDT 24
Finished	Jul 16 05:36:57 PM PDT 24
Peak memory	269856 kb
Host	smart-3eee893c-51e7-4108-930a-5b6baa30567a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998618229 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3998618229
Directory	/workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.82051494
Short name	T342
Test name
Test status
Simulation time	25918100 ps
CPU time	13.12 seconds
Started	Jul 16 05:30:28 PM PDT 24
Finished	Jul 16 05:30:42 PM PDT 24
Peak memory	260204 kb
Host	smart-7c909e00-72b1-4784-8887-1c3b8839215e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82051494 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.82051494
Directory	/workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.3302107137
Short name	T1003
Test name
Test status
Simulation time	160173782000 ps
CPU time	976.3 seconds
Started	Jul 16 05:34:18 PM PDT 24
Finished	Jul 16 05:50:35 PM PDT 24
Peak memory	264220 kb
Host	smart-88fc7edd-a2f3-4e5e-ac0f-b3556a628d40
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302107137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.flash_ctrl_hw_rma_reset.3302107137
Directory	/workspace/2.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2370141433
Short name	T980
Test name
Test status
Simulation time	4271862500 ps
CPU time	149.74 seconds
Started	Jul 16 05:34:21 PM PDT 24
Finished	Jul 16 05:36:51 PM PDT 24
Peak memory	260548 kb
Host	smart-714c3c58-4e65-4bf0-825c-0f2763a60284
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370141433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h w_sec_otp.2370141433
Directory	/workspace/2.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_integrity.4017395881
Short name	T868
Test name
Test status
Simulation time	17143743900 ps
CPU time	699.48 seconds
Started	Jul 16 05:30:10 PM PDT 24
Finished	Jul 16 05:41:51 PM PDT 24
Peak memory	339624 kb
Host	smart-15bff36e-fead-4a8b-bc38-c8feeaf1a2c6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017395881 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_integrity.4017395881
Directory	/workspace/2.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd.2084706729
Short name	T268
Test name
Test status
Simulation time	3688299000 ps
CPU time	220.89 seconds
Started	Jul 16 05:30:09 PM PDT 24
Finished	Jul 16 05:33:51 PM PDT 24
Peak memory	291396 kb
Host	smart-acc4423d-557b-4b7d-a237-26278fc54961
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084706729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_intr_rd.2084706729
Directory	/workspace/2.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.1231545065
Short name	T1089
Test name
Test status
Simulation time	48197337200 ps
CPU time	152.73 seconds
Started	Jul 16 05:30:13 PM PDT 24
Finished	Jul 16 05:32:47 PM PDT 24
Peak memory	289888 kb
Host	smart-ae0c4b38-92fe-44e6-b138-c965f5198e7b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231545065 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.1231545065
Directory	/workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr.2814053140
Short name	T791
Test name
Test status
Simulation time	2412957900 ps
CPU time	66.51 seconds
Started	Jul 16 05:30:13 PM PDT 24
Finished	Jul 16 05:31:20 PM PDT 24
Peak memory	265216 kb
Host	smart-e054cf51-4867-4272-8688-8aa0dd71b71e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814053140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_intr_wr.2814053140
Directory	/workspace/2.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.3146239926
Short name	T25
Test name
Test status
Simulation time	467988102500 ps
CPU time	266.72 seconds
Started	Jul 16 05:35:13 PM PDT 24
Finished	Jul 16 05:39:40 PM PDT 24
Peak memory	261052 kb
Host	smart-846b8641-b21e-43b9-a4bf-0cf7bc543f3d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314 6239926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.3146239926
Directory	/workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_invalid_op.3773736087
Short name	T1052
Test name
Test status
Simulation time	1664662600 ps
CPU time	65.05 seconds
Started	Jul 16 05:30:03 PM PDT 24
Finished	Jul 16 05:31:09 PM PDT 24
Peak memory	262492 kb
Host	smart-5aa01407-3673-4c68-a418-fadc431d577e
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773736087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3773736087
Directory	/workspace/2.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1432244822
Short name	T1080
Test name
Test status
Simulation time	95759000 ps
CPU time	13.41 seconds
Started	Jul 16 05:30:18 PM PDT 24
Finished	Jul 16 05:30:33 PM PDT 24
Peak memory	265308 kb
Host	smart-704bb407-2bf4-4b33-b5ce-acc641395eee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432244822 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.1432244822
Directory	/workspace/2.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mp_regions.2613840854
Short name	T743
Test name
Test status
Simulation time	31218692400 ps
CPU time	121.34 seconds
Started	Jul 16 05:29:54 PM PDT 24
Finished	Jul 16 05:31:56 PM PDT 24
Peak memory	265120 kb
Host	smart-a96ba230-3910-49f7-b522-f1525e3da410
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613840854 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.2613840854
Directory	/workspace/2.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/2.flash_ctrl_otp_reset.81893092
Short name	T167
Test name
Test status
Simulation time	117874300 ps
CPU time	132.64 seconds
Started	Jul 16 05:29:55 PM PDT 24
Finished	Jul 16 05:32:08 PM PDT 24
Peak memory	265076 kb
Host	smart-9843f9f5-19b3-458b-8d15-f78645690c66
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81893092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_ reset.81893092
Directory	/workspace/2.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_oversize_error.1449927112
Short name	T41
Test name
Test status
Simulation time	2960256000 ps
CPU time	196.57 seconds
Started	Jul 16 05:30:11 PM PDT 24
Finished	Jul 16 05:33:29 PM PDT 24
Peak memory	281684 kb
Host	smart-7d3e381e-ad04-41ae-a37c-133e35126054
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449927112 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.1449927112
Directory	/workspace/2.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.3654323512
Short name	T214
Test name
Test status
Simulation time	26451800 ps
CPU time	13.91 seconds
Started	Jul 16 05:30:10 PM PDT 24
Finished	Jul 16 05:30:25 PM PDT 24
Peak memory	261160 kb
Host	smart-7b7ad3e3-3acb-47f3-a4fe-83ce14b00ec9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3654323512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.3654323512
Directory	/workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb.1424123199
Short name	T1009
Test name
Test status
Simulation time	75287800 ps
CPU time	151.37 seconds
Started	Jul 16 05:29:54 PM PDT 24
Finished	Jul 16 05:32:26 PM PDT 24
Peak memory	263232 kb
Host	smart-a876baab-474c-4351-846c-730fa797d673
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1424123199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1424123199
Directory	/workspace/2.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.386167600
Short name	T212
Test name
Test status
Simulation time	17126100 ps
CPU time	14.09 seconds
Started	Jul 16 05:32:25 PM PDT 24
Finished	Jul 16 05:32:40 PM PDT 24
Peak memory	262540 kb
Host	smart-ed1830c3-e7d4-4ee2-a201-9e99e3fd9f27
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386167600 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.386167600
Directory	/workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_prog_reset.2607840452
Short name	T681
Test name
Test status
Simulation time	12046072900 ps
CPU time	187.37 seconds
Started	Jul 16 05:30:08 PM PDT 24
Finished	Jul 16 05:33:17 PM PDT 24
Peak memory	260636 kb
Host	smart-76cac7fa-9942-49b7-a2d9-d0bba9293b37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607840452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.flash_ctrl_prog_reset.2607840452
Directory	/workspace/2.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rand_ops.1783771582
Short name	T147
Test name
Test status
Simulation time	128649000 ps
CPU time	274.36 seconds
Started	Jul 16 05:34:59 PM PDT 24
Finished	Jul 16 05:39:34 PM PDT 24
Peak memory	281568 kb
Host	smart-4e6a145d-3fc1-42d6-a291-3145da5dd4ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783771582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1783771582
Directory	/workspace/2.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_buff_evict.2001151496
Short name	T1020
Test name
Test status
Simulation time	79775300 ps
CPU time	101.79 seconds
Started	Jul 16 05:30:03 PM PDT 24
Finished	Jul 16 05:31:45 PM PDT 24
Peak memory	262828 kb
Host	smart-e0dccce7-5470-482e-8af4-c6262e085d4e
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2001151496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2001151496
Directory	/workspace/2.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_intg.705120823
Short name	T278
Test name
Test status
Simulation time	67335100 ps
CPU time	31.46 seconds
Started	Jul 16 05:30:16 PM PDT 24
Finished	Jul 16 05:30:49 PM PDT 24
Peak memory	276664 kb
Host	smart-b62f2236-79b6-4f2f-9cc8-d446546de470
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705120823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.flash_ctrl_rd_intg.705120823
Directory	/workspace/2.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_re_evict.4197178670
Short name	T345
Test name
Test status
Simulation time	233835200 ps
CPU time	32.06 seconds
Started	Jul 16 05:37:03 PM PDT 24
Finished	Jul 16 05:37:36 PM PDT 24
Peak memory	276700 kb
Host	smart-7839e906-7c9d-4954-8d08-fae38ebb8694
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197178670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_re_evict.4197178670
Directory	/workspace/2.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.2343476492
Short name	T583
Test name
Test status
Simulation time	43387600 ps
CPU time	21.19 seconds
Started	Jul 16 05:30:13 PM PDT 24
Finished	Jul 16 05:30:35 PM PDT 24
Peak memory	265316 kb
Host	smart-56d0677f-7b72-487d-b868-af66c9a10511
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343476492 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.2343476492
Directory	/workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.1502083638
Short name	T745
Test name
Test status
Simulation time	42067300 ps
CPU time	21.14 seconds
Started	Jul 16 05:30:08 PM PDT 24
Finished	Jul 16 05:30:30 PM PDT 24
Peak memory	265120 kb
Host	smart-0345c5ba-fa3b-4521-a772-4d6a5b9e9625
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502083638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_read_word_sweep_serr.1502083638
Directory	/workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rma_err.1235174787
Short name	T162
Test name
Test status
Simulation time	83063312400 ps
CPU time	946.55 seconds
Started	Jul 16 05:30:18 PM PDT 24
Finished	Jul 16 05:46:06 PM PDT 24
Peak memory	261312 kb
Host	smart-a47ddcbd-7781-4427-8513-6fb44cc720c0
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235174787 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.1235174787
Directory	/workspace/2.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro.1411406857
Short name	T823
Test name
Test status
Simulation time	959500600 ps
CPU time	115.17 seconds
Started	Jul 16 05:35:00 PM PDT 24
Finished	Jul 16 05:36:55 PM PDT 24
Peak memory	281024 kb
Host	smart-70feee6f-65a1-43c5-8812-34c27b2c8300
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411406857 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_ro.1411406857
Directory	/workspace/2.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_derr.1458310970
Short name	T873
Test name
Test status
Simulation time	2351344400 ps
CPU time	134.6 seconds
Started	Jul 16 05:30:17 PM PDT 24
Finished	Jul 16 05:32:33 PM PDT 24
Peak memory	281860 kb
Host	smart-0ebbb0cc-33dd-4165-8524-9c5e70cb7a5a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1458310970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1458310970
Directory	/workspace/2.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_serr.713885769
Short name	T488
Test name
Test status
Simulation time	8259197400 ps
CPU time	139.15 seconds
Started	Jul 16 05:30:16 PM PDT 24
Finished	Jul 16 05:32:37 PM PDT 24
Peak memory	281736 kb
Host	smart-c5391ab6-07e2-4358-9c4d-4f53d72f87e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713885769 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.713885769
Directory	/workspace/2.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw.4150365717
Short name	T897
Test name
Test status
Simulation time	4499092700 ps
CPU time	630.19 seconds
Started	Jul 16 05:30:07 PM PDT 24
Finished	Jul 16 05:40:38 PM PDT 24
Peak memory	318860 kb
Host	smart-3374956b-3967-43b7-a681-020e4c89e055
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150365717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.flash_ctrl_rw.4150365717
Directory	/workspace/2.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_derr.3080991130
Short name	T978
Test name
Test status
Simulation time	16606412900 ps
CPU time	745.08 seconds
Started	Jul 16 05:30:03 PM PDT 24
Finished	Jul 16 05:42:29 PM PDT 24
Peak memory	337504 kb
Host	smart-f29bc501-58b6-409e-a2b3-00e6d4fefcf7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080991130 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_rw_derr.3080991130
Directory	/workspace/2.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict.2607500795
Short name	T204
Test name
Test status
Simulation time	42266500 ps
CPU time	30.8 seconds
Started	Jul 16 05:30:02 PM PDT 24
Finished	Jul 16 05:30:33 PM PDT 24
Peak memory	275608 kb
Host	smart-82f831ce-a43d-4865-87c9-aef237a0ed4d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607500795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_rw_evict.2607500795
Directory	/workspace/2.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.1464649845
Short name	T530
Test name
Test status
Simulation time	70044400 ps
CPU time	30.53 seconds
Started	Jul 16 05:30:18 PM PDT 24
Finished	Jul 16 05:30:50 PM PDT 24
Peak memory	268452 kb
Host	smart-81f0f269-3e0a-465a-96e3-fbc0b4dae88c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464649845 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.1464649845
Directory	/workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_serr.3806839903
Short name	T471
Test name
Test status
Simulation time	29882413700 ps
CPU time	677.89 seconds
Started	Jul 16 05:30:07 PM PDT 24
Finished	Jul 16 05:41:25 PM PDT 24
Peak memory	314460 kb
Host	smart-99b7bf13-2542-4035-ba78-e0ca05624abb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806839903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s err.3806839903
Directory	/workspace/2.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_cm.2029803960
Short name	T105
Test name
Test status
Simulation time	2028769000 ps
CPU time	4773 seconds
Started	Jul 16 05:36:09 PM PDT 24
Finished	Jul 16 06:55:43 PM PDT 24
Peak memory	284744 kb
Host	smart-35969efc-a2a9-493f-bbfe-716cd7f680ac
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029803960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.2029803960
Directory	/workspace/2.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_info_access.2995342698
Short name	T726
Test name
Test status
Simulation time	2956300200 ps
CPU time	67.4 seconds
Started	Jul 16 05:35:12 PM PDT 24
Finished	Jul 16 05:36:20 PM PDT 24
Peak memory	264716 kb
Host	smart-1c1d3728-5e0d-44a4-b867-15157034b666
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2995342698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.2995342698
Directory	/workspace/2.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_address.100008957
Short name	T658
Test name
Test status
Simulation time	5677987700 ps
CPU time	66.98 seconds
Started	Jul 16 05:30:03 PM PDT 24
Finished	Jul 16 05:31:11 PM PDT 24
Peak memory	273724 kb
Host	smart-7ac5a1e1-288c-4cb7-b318-65d9fe2d9f7b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100008957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_serr_address.100008957
Directory	/workspace/2.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_counter.758467896
Short name	T551
Test name
Test status
Simulation time	850812900 ps
CPU time	62.43 seconds
Started	Jul 16 05:30:10 PM PDT 24
Finished	Jul 16 05:31:14 PM PDT 24
Peak memory	265288 kb
Host	smart-91c476ec-b67e-4a59-b4c2-dd9918137f4d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758467896 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_serr_counter.758467896
Directory	/workspace/2.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke.2893386560
Short name	T536
Test name
Test status
Simulation time	120115400 ps
CPU time	51.96 seconds
Started	Jul 16 05:29:55 PM PDT 24
Finished	Jul 16 05:30:48 PM PDT 24
Peak memory	269712 kb
Host	smart-0d71b40d-d768-43f7-9b2c-0b1a26f05696
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2893386560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2893386560
Directory	/workspace/2.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke_hw.40996762
Short name	T559
Test name
Test status
Simulation time	29526900 ps
CPU time	26.07 seconds
Started	Jul 16 05:29:59 PM PDT 24
Finished	Jul 16 05:30:26 PM PDT 24
Peak memory	259740 kb
Host	smart-7df9e572-223f-4a53-9efe-4212f42a93ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40996762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.40996762
Directory	/workspace/2.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_stress_all.1945109241
Short name	T569
Test name
Test status
Simulation time	108762000 ps
CPU time	286.22 seconds
Started	Jul 16 05:30:12 PM PDT 24
Finished	Jul 16 05:35:00 PM PDT 24
Peak memory	278644 kb
Host	smart-12f88193-df28-40bc-9580-21278fe292b3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945109241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres s_all.1945109241
Directory	/workspace/2.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sw_op.1821403756
Short name	T971
Test name
Test status
Simulation time	91674500 ps
CPU time	26.37 seconds
Started	Jul 16 05:30:00 PM PDT 24
Finished	Jul 16 05:30:27 PM PDT 24
Peak memory	262256 kb
Host	smart-a9842282-6e2e-4b50-8945-6f2013eb4a71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1821403756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.1821403756
Directory	/workspace/2.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wo.784317816
Short name	T490
Test name
Test status
Simulation time	10412790800 ps
CPU time	187.59 seconds
Started	Jul 16 05:30:11 PM PDT 24
Finished	Jul 16 05:33:19 PM PDT 24
Peak memory	259376 kb
Host	smart-d5996db0-e79f-4fc9-bb4e-8538d5152913
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784317816 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.flash_ctrl_wo.784317816
Directory	/workspace/2.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wr_intg.390915542
Short name	T250
Test name
Test status
Simulation time	83301900 ps
CPU time	15.23 seconds
Started	Jul 16 05:30:08 PM PDT 24
Finished	Jul 16 05:30:24 PM PDT 24
Peak memory	264956 kb
Host	smart-27f40edf-9979-419e-9404-b44cfeb4acfb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390915542 -assert nopostproc +UVM _TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.390915542
Directory	/workspace/2.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/20.flash_ctrl_alert_test.2581234597
Short name	T618
Test name
Test status
Simulation time	141062500 ps
CPU time	13.63 seconds
Started	Jul 16 05:34:25 PM PDT 24
Finished	Jul 16 05:34:40 PM PDT 24
Peak memory	265240 kb
Host	smart-86f7664c-74ed-48dd-a5df-146ddae37a38
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581234597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test. 2581234597
Directory	/workspace/20.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.flash_ctrl_connect.874716974
Short name	T1018
Test name
Test status
Simulation time	15621000 ps
CPU time	15.87 seconds
Started	Jul 16 05:34:31 PM PDT 24
Finished	Jul 16 05:34:48 PM PDT 24
Peak memory	274872 kb
Host	smart-31b09171-8dd1-4916-b4fd-a4f5c4af82f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=874716974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.874716974
Directory	/workspace/20.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/20.flash_ctrl_disable.3100033099
Short name	T1096
Test name
Test status
Simulation time	11756200 ps
CPU time	20.01 seconds
Started	Jul 16 05:34:27 PM PDT 24
Finished	Jul 16 05:34:48 PM PDT 24
Peak memory	273524 kb
Host	smart-6bd3352f-12ce-4319-9e92-0c69283dbd7b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100033099 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_disable.3100033099
Directory	/workspace/20.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.3121821948
Short name	T306
Test name
Test status
Simulation time	2152015800 ps
CPU time	53.33 seconds
Started	Jul 16 05:36:35 PM PDT 24
Finished	Jul 16 05:37:30 PM PDT 24
Peak memory	260476 kb
Host	smart-e0f4bcd9-9af2-4123-9703-7fdc3cba3a54
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121821948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ hw_sec_otp.3121821948
Directory	/workspace/20.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd.4064798798
Short name	T489
Test name
Test status
Simulation time	2856416100 ps
CPU time	142.38 seconds
Started	Jul 16 05:34:32 PM PDT 24
Finished	Jul 16 05:36:55 PM PDT 24
Peak memory	285228 kb
Host	smart-683fb88e-4302-450d-a6cb-049c5a0ef6ec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064798798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla sh_ctrl_intr_rd.4064798798
Directory	/workspace/20.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.1557145212
Short name	T669
Test name
Test status
Simulation time	52232618600 ps
CPU time	333.55 seconds
Started	Jul 16 05:34:32 PM PDT 24
Finished	Jul 16 05:40:06 PM PDT 24
Peak memory	290920 kb
Host	smart-e8796f69-4011-473e-8d3b-2b589952c20b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557145212 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.1557145212
Directory	/workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/20.flash_ctrl_otp_reset.3653407939
Short name	T470
Test name
Test status
Simulation time	145451400 ps
CPU time	129.96 seconds
Started	Jul 16 05:34:27 PM PDT 24
Finished	Jul 16 05:36:38 PM PDT 24
Peak memory	261004 kb
Host	smart-48da56ad-71b6-4109-b061-9d1b472ae85b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653407939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o tp_reset.3653407939
Directory	/workspace/20.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_prog_reset.628670787
Short name	T520
Test name
Test status
Simulation time	74725300 ps
CPU time	13.11 seconds
Started	Jul 16 05:34:27 PM PDT 24
Finished	Jul 16 05:34:42 PM PDT 24
Peak memory	259024 kb
Host	smart-b1b2adbc-722c-4c72-9e4d-60bf11f53363
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628670787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.flash_ctrl_prog_reset.628670787
Directory	/workspace/20.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.3660418868
Short name	T827
Test name
Test status
Simulation time	46065700 ps
CPU time	29.18 seconds
Started	Jul 16 05:34:29 PM PDT 24
Finished	Jul 16 05:34:58 PM PDT 24
Peak memory	275640 kb
Host	smart-0400166c-14e2-4e62-9e24-8c6742762491
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660418868 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.3660418868
Directory	/workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/20.flash_ctrl_sec_info_access.1367243840
Short name	T584
Test name
Test status
Simulation time	4500300000 ps
CPU time	74.76 seconds
Started	Jul 16 05:34:29 PM PDT 24
Finished	Jul 16 05:35:44 PM PDT 24
Peak memory	263124 kb
Host	smart-77a9bedb-3913-4fda-9132-6bf409348ee4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1367243840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1367243840
Directory	/workspace/20.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/20.flash_ctrl_smoke.1204395038
Short name	T597
Test name
Test status
Simulation time	34915500 ps
CPU time	195.33 seconds
Started	Jul 16 05:34:25 PM PDT 24
Finished	Jul 16 05:37:41 PM PDT 24
Peak memory	277660 kb
Host	smart-29c0124e-d2c5-43b4-be87-7d5842ec26ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204395038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.1204395038
Directory	/workspace/20.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.flash_ctrl_alert_test.1698385566
Short name	T627
Test name
Test status
Simulation time	52516500 ps
CPU time	13.63 seconds
Started	Jul 16 05:36:30 PM PDT 24
Finished	Jul 16 05:36:44 PM PDT 24
Peak memory	258184 kb
Host	smart-f85d97f0-5fc3-4243-9be5-51e1becce125
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698385566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test. 1698385566
Directory	/workspace/21.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.flash_ctrl_connect.2138914423
Short name	T461
Test name
Test status
Simulation time	204840000 ps
CPU time	16.07 seconds
Started	Jul 16 05:34:36 PM PDT 24
Finished	Jul 16 05:34:53 PM PDT 24
Peak memory	284528 kb
Host	smart-a35ab9f3-03ba-42ba-b47c-4d0ef3596231
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138914423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.2138914423
Directory	/workspace/21.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/21.flash_ctrl_disable.2708105492
Short name	T392
Test name
Test status
Simulation time	28240600 ps
CPU time	21.93 seconds
Started	Jul 16 05:34:35 PM PDT 24
Finished	Jul 16 05:34:58 PM PDT 24
Peak memory	273644 kb
Host	smart-75ea63ef-dc0c-4ec1-99d2-243f1fef77dd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708105492 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_disable.2708105492
Directory	/workspace/21.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2539633603
Short name	T319
Test name
Test status
Simulation time	8213267400 ps
CPU time	142.85 seconds
Started	Jul 16 05:34:28 PM PDT 24
Finished	Jul 16 05:36:52 PM PDT 24
Peak memory	260972 kb
Host	smart-5673b40f-cc28-413e-bea3-c09c87638447
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539633603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ hw_sec_otp.2539633603
Directory	/workspace/21.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd.1562811438
Short name	T856
Test name
Test status
Simulation time	6169041700 ps
CPU time	175.93 seconds
Started	Jul 16 05:34:27 PM PDT 24
Finished	Jul 16 05:37:24 PM PDT 24
Peak memory	291480 kb
Host	smart-deb4c3b2-ee0a-44ef-9ec8-719a0b5f1514
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562811438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla sh_ctrl_intr_rd.1562811438
Directory	/workspace/21.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.3953244131
Short name	T739
Test name
Test status
Simulation time	145743663100 ps
CPU time	382.5 seconds
Started	Jul 16 05:34:30 PM PDT 24
Finished	Jul 16 05:40:53 PM PDT 24
Peak memory	290876 kb
Host	smart-ba7052bb-0d18-4d9a-8518-1aee3ad9e8c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953244131 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.3953244131
Directory	/workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/21.flash_ctrl_otp_reset.211854235
Short name	T146
Test name
Test status
Simulation time	37822000 ps
CPU time	131.88 seconds
Started	Jul 16 05:34:32 PM PDT 24
Finished	Jul 16 05:36:44 PM PDT 24
Peak memory	260056 kb
Host	smart-a39e1e1c-6458-4211-bb93-f9be4405046c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211854235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ot p_reset.211854235
Directory	/workspace/21.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_prog_reset.1177794130
Short name	T730
Test name
Test status
Simulation time	81226600 ps
CPU time	13.45 seconds
Started	Jul 16 05:34:27 PM PDT 24
Finished	Jul 16 05:34:42 PM PDT 24
Peak memory	265260 kb
Host	smart-62ad4965-ae65-440b-abc2-cc0fa734df52
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177794130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.flash_ctrl_prog_reset.1177794130
Directory	/workspace/21.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict.2459243724
Short name	T111
Test name
Test status
Simulation time	74171400 ps
CPU time	30.78 seconds
Started	Jul 16 05:34:26 PM PDT 24
Finished	Jul 16 05:34:57 PM PDT 24
Peak memory	275548 kb
Host	smart-8d087de5-8b6a-44e1-8935-cefbd6dd2425
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459243724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl ash_ctrl_rw_evict.2459243724
Directory	/workspace/21.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.1041746630
Short name	T832
Test name
Test status
Simulation time	67151800 ps
CPU time	30.16 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:37:21 PM PDT 24
Peak memory	273640 kb
Host	smart-246957dc-ed23-45c8-9bbe-45bfc010be45
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041746630 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.1041746630
Directory	/workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/21.flash_ctrl_sec_info_access.3203504161
Short name	T406
Test name
Test status
Simulation time	4248614000 ps
CPU time	55.68 seconds
Started	Jul 16 05:34:36 PM PDT 24
Finished	Jul 16 05:35:33 PM PDT 24
Peak memory	264724 kb
Host	smart-b2693fb0-c82a-46af-876a-d96c205f9f63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3203504161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3203504161
Directory	/workspace/21.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/21.flash_ctrl_smoke.1291118459
Short name	T478
Test name
Test status
Simulation time	29805300 ps
CPU time	74.81 seconds
Started	Jul 16 05:34:30 PM PDT 24
Finished	Jul 16 05:35:46 PM PDT 24
Peak memory	275932 kb
Host	smart-251200d9-f4e8-4562-860e-fbbebefb7c51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291118459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.1291118459
Directory	/workspace/21.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.flash_ctrl_alert_test.2851842285
Short name	T309
Test name
Test status
Simulation time	55435800 ps
CPU time	13.84 seconds
Started	Jul 16 05:34:48 PM PDT 24
Finished	Jul 16 05:35:03 PM PDT 24
Peak memory	258264 kb
Host	smart-0d3159fa-20de-4e17-87af-bc40e5dd7bf0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851842285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test. 2851842285
Directory	/workspace/22.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.flash_ctrl_connect.2832185347
Short name	T1051
Test name
Test status
Simulation time	16260700 ps
CPU time	13.91 seconds
Started	Jul 16 05:36:47 PM PDT 24
Finished	Jul 16 05:37:02 PM PDT 24
Peak memory	274916 kb
Host	smart-2ff9cf39-a085-42b9-94b7-ca185deeac09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2832185347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2832185347
Directory	/workspace/22.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/22.flash_ctrl_disable.2620319242
Short name	T649
Test name
Test status
Simulation time	11533600 ps
CPU time	20.28 seconds
Started	Jul 16 05:36:17 PM PDT 24
Finished	Jul 16 05:36:38 PM PDT 24
Peak memory	273504 kb
Host	smart-734ee2e4-92da-4baa-95e0-c31b5c8d6526
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620319242 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_disable.2620319242
Directory	/workspace/22.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.1828590167
Short name	T90
Test name
Test status
Simulation time	3855732900 ps
CPU time	114.45 seconds
Started	Jul 16 05:34:36 PM PDT 24
Finished	Jul 16 05:36:31 PM PDT 24
Peak memory	260972 kb
Host	smart-64ff2567-2392-4bf3-aac5-32a31656c560
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828590167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ hw_sec_otp.1828590167
Directory	/workspace/22.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd.2890356186
Short name	T747
Test name
Test status
Simulation time	20897584100 ps
CPU time	209.79 seconds
Started	Jul 16 05:34:36 PM PDT 24
Finished	Jul 16 05:38:07 PM PDT 24
Peak memory	284764 kb
Host	smart-7684a78a-aaab-432d-ae52-b45f16f2f198
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890356186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla sh_ctrl_intr_rd.2890356186
Directory	/workspace/22.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.675600512
Short name	T590
Test name
Test status
Simulation time	28375331000 ps
CPU time	264.76 seconds
Started	Jul 16 05:34:36 PM PDT 24
Finished	Jul 16 05:39:02 PM PDT 24
Peak memory	284540 kb
Host	smart-da8664c0-cda2-4ce4-a09f-e746357f183d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675600512 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.675600512
Directory	/workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/22.flash_ctrl_otp_reset.2620412671
Short name	T545
Test name
Test status
Simulation time	69747700 ps
CPU time	131.83 seconds
Started	Jul 16 05:34:35 PM PDT 24
Finished	Jul 16 05:36:47 PM PDT 24
Peak memory	260232 kb
Host	smart-3dd2f7af-8c61-46d8-9219-779c2fcaa3e7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620412671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o tp_reset.2620412671
Directory	/workspace/22.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_prog_reset.3846608613
Short name	T910
Test name
Test status
Simulation time	34221300 ps
CPU time	13.28 seconds
Started	Jul 16 05:34:48 PM PDT 24
Finished	Jul 16 05:35:01 PM PDT 24
Peak memory	259248 kb
Host	smart-9df48b45-9c4a-4ecc-939c-1396ba885083
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846608613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.flash_ctrl_prog_reset.3846608613
Directory	/workspace/22.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict.4144265550
Short name	T612
Test name
Test status
Simulation time	27895800 ps
CPU time	30.42 seconds
Started	Jul 16 05:37:00 PM PDT 24
Finished	Jul 16 05:37:32 PM PDT 24
Peak memory	275564 kb
Host	smart-75811128-daa1-482d-be61-d383737154e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144265550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl ash_ctrl_rw_evict.4144265550
Directory	/workspace/22.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/22.flash_ctrl_sec_info_access.311809757
Short name	T593
Test name
Test status
Simulation time	6214326800 ps
CPU time	76.1 seconds
Started	Jul 16 05:34:48 PM PDT 24
Finished	Jul 16 05:36:04 PM PDT 24
Peak memory	263144 kb
Host	smart-025d5af8-7b74-4de7-9a09-d26b653948da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=311809757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.311809757
Directory	/workspace/22.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/22.flash_ctrl_smoke.807762780
Short name	T1012
Test name
Test status
Simulation time	222064200 ps
CPU time	120.75 seconds
Started	Jul 16 05:34:35 PM PDT 24
Finished	Jul 16 05:36:37 PM PDT 24
Peak memory	277524 kb
Host	smart-1691f1ff-fa9d-4160-bd98-6c34a185646a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807762780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.807762780
Directory	/workspace/22.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.flash_ctrl_alert_test.352453336
Short name	T438
Test name
Test status
Simulation time	327413500 ps
CPU time	15.02 seconds
Started	Jul 16 05:34:51 PM PDT 24
Finished	Jul 16 05:35:06 PM PDT 24
Peak memory	258372 kb
Host	smart-8c55e32e-b50e-413e-a16a-e12fd4710f18
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352453336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.352453336
Directory	/workspace/23.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.flash_ctrl_connect.585996827
Short name	T809
Test name
Test status
Simulation time	16079100 ps
CPU time	15.86 seconds
Started	Jul 16 05:34:51 PM PDT 24
Finished	Jul 16 05:35:07 PM PDT 24
Peak memory	274876 kb
Host	smart-312c1e68-7c43-4ac1-8e4b-9d1ee8466174
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=585996827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.585996827
Directory	/workspace/23.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/23.flash_ctrl_disable.2011663735
Short name	T963
Test name
Test status
Simulation time	22627600 ps
CPU time	21.92 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:37:19 PM PDT 24
Peak memory	273588 kb
Host	smart-4f598837-cc7e-49f8-bf6d-ac19ad8282ca
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011663735 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_disable.2011663735
Directory	/workspace/23.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/23.flash_ctrl_hw_sec_otp.3367646627
Short name	T435
Test name
Test status
Simulation time	1790383000 ps
CPU time	71.66 seconds
Started	Jul 16 05:34:46 PM PDT 24
Finished	Jul 16 05:35:58 PM PDT 24
Peak memory	262404 kb
Host	smart-deace71e-dd3f-4aaa-84a8-39f074054ba9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367646627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_ hw_sec_otp.3367646627
Directory	/workspace/23.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd.1671073552
Short name	T338
Test name
Test status
Simulation time	4757781800 ps
CPU time	121 seconds
Started	Jul 16 05:34:50 PM PDT 24
Finished	Jul 16 05:36:51 PM PDT 24
Peak memory	293784 kb
Host	smart-e9df9b7d-d75d-4dcd-bc4e-6c089c65640b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671073552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla sh_ctrl_intr_rd.1671073552
Directory	/workspace/23.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2810018888
Short name	T586
Test name
Test status
Simulation time	80711448000 ps
CPU time	233.5 seconds
Started	Jul 16 05:34:49 PM PDT 24
Finished	Jul 16 05:38:43 PM PDT 24
Peak memory	293108 kb
Host	smart-1b73eb3d-da13-43b1-87a9-3d2990b60255
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810018888 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2810018888
Directory	/workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/23.flash_ctrl_otp_reset.3080023336
Short name	T720
Test name
Test status
Simulation time	41415500 ps
CPU time	110.89 seconds
Started	Jul 16 05:34:47 PM PDT 24
Finished	Jul 16 05:36:38 PM PDT 24
Peak memory	259844 kb
Host	smart-0902d63d-97ba-4dcb-8bda-3154060f7f5a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080023336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o tp_reset.3080023336
Directory	/workspace/23.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_prog_reset.2586856833
Short name	T572
Test name
Test status
Simulation time	21972800 ps
CPU time	13.44 seconds
Started	Jul 16 05:34:50 PM PDT 24
Finished	Jul 16 05:35:04 PM PDT 24
Peak memory	259096 kb
Host	smart-96624e09-45de-4fab-b9b0-bf588e8c129f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586856833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.flash_ctrl_prog_reset.2586856833
Directory	/workspace/23.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict.2562680213
Short name	T703
Test name
Test status
Simulation time	67132200 ps
CPU time	30.39 seconds
Started	Jul 16 05:36:33 PM PDT 24
Finished	Jul 16 05:37:04 PM PDT 24
Peak memory	273624 kb
Host	smart-3becfef8-7a1a-4ab2-b3e3-d853a26b8575
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562680213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl ash_ctrl_rw_evict.2562680213
Directory	/workspace/23.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.1544707459
Short name	T37
Test name
Test status
Simulation time	27153500 ps
CPU time	31.25 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:37:26 PM PDT 24
Peak memory	275636 kb
Host	smart-08bd74e2-5117-4159-a2d6-1657517c7218
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544707459 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.1544707459
Directory	/workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/23.flash_ctrl_sec_info_access.3300607215
Short name	T824
Test name
Test status
Simulation time	1754020500 ps
CPU time	57.23 seconds
Started	Jul 16 05:34:52 PM PDT 24
Finished	Jul 16 05:35:50 PM PDT 24
Peak memory	264920 kb
Host	smart-1f135dc2-360b-4474-82cb-59dfca4fc82d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300607215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.3300607215
Directory	/workspace/23.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/23.flash_ctrl_smoke.1621043737
Short name	T521
Test name
Test status
Simulation time	34205800 ps
CPU time	170.85 seconds
Started	Jul 16 05:34:48 PM PDT 24
Finished	Jul 16 05:37:39 PM PDT 24
Peak memory	277428 kb
Host	smart-6da97293-5866-4ee1-beb9-6d2bd42ba299
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1621043737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.1621043737
Directory	/workspace/23.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.flash_ctrl_alert_test.1699247495
Short name	T476
Test name
Test status
Simulation time	23622300 ps
CPU time	13.66 seconds
Started	Jul 16 05:35:02 PM PDT 24
Finished	Jul 16 05:35:17 PM PDT 24
Peak memory	265232 kb
Host	smart-0e5b906d-a276-484e-9d07-c6a6ff81bd3d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699247495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test. 1699247495
Directory	/workspace/24.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.flash_ctrl_connect.3066925590
Short name	T517
Test name
Test status
Simulation time	15594400 ps
CPU time	16.56 seconds
Started	Jul 16 05:35:00 PM PDT 24
Finished	Jul 16 05:35:17 PM PDT 24
Peak memory	284320 kb
Host	smart-c961859c-a455-44f3-aa87-c07e4f01d0ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066925590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3066925590
Directory	/workspace/24.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/24.flash_ctrl_hw_sec_otp.2923650546
Short name	T982
Test name
Test status
Simulation time	2152320100 ps
CPU time	61.1 seconds
Started	Jul 16 05:34:49 PM PDT 24
Finished	Jul 16 05:35:51 PM PDT 24
Peak memory	262664 kb
Host	smart-8505c789-54d2-4115-b52b-83a1a677b853
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923650546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ hw_sec_otp.2923650546
Directory	/workspace/24.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd.1024087345
Short name	T828
Test name
Test status
Simulation time	536017000 ps
CPU time	142.82 seconds
Started	Jul 16 05:34:48 PM PDT 24
Finished	Jul 16 05:37:11 PM PDT 24
Peak memory	290900 kb
Host	smart-50fe4011-74e9-4f33-8bc7-c70c1687a880
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024087345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla sh_ctrl_intr_rd.1024087345
Directory	/workspace/24.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2805791239
Short name	T1021
Test name
Test status
Simulation time	11509681100 ps
CPU time	130.54 seconds
Started	Jul 16 05:34:49 PM PDT 24
Finished	Jul 16 05:37:00 PM PDT 24
Peak memory	293164 kb
Host	smart-1c917a83-2778-4402-954a-51f7f074a270
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805791239 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.2805791239
Directory	/workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/24.flash_ctrl_otp_reset.1310185081
Short name	T986
Test name
Test status
Simulation time	193406200 ps
CPU time	107.94 seconds
Started	Jul 16 05:34:48 PM PDT 24
Finished	Jul 16 05:36:36 PM PDT 24
Peak memory	261144 kb
Host	smart-7865fb76-ea74-4382-9f1b-8fbec448e42e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310185081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o tp_reset.1310185081
Directory	/workspace/24.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_prog_reset.2380296263
Short name	T750
Test name
Test status
Simulation time	38899872300 ps
CPU time	208.01 seconds
Started	Jul 16 05:34:52 PM PDT 24
Finished	Jul 16 05:38:21 PM PDT 24
Peak memory	261648 kb
Host	smart-3418246d-24eb-4e44-87f6-5c7fcbb35de4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380296263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.flash_ctrl_prog_reset.2380296263
Directory	/workspace/24.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict.1081902215
Short name	T1092
Test name
Test status
Simulation time	149690100 ps
CPU time	31.76 seconds
Started	Jul 16 05:34:50 PM PDT 24
Finished	Jul 16 05:35:23 PM PDT 24
Peak memory	268520 kb
Host	smart-ffdb9561-81c5-45b6-b9f6-d10fec05f442
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081902215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl ash_ctrl_rw_evict.1081902215
Directory	/workspace/24.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.1557246942
Short name	T877
Test name
Test status
Simulation time	34805200 ps
CPU time	28.57 seconds
Started	Jul 16 05:34:49 PM PDT 24
Finished	Jul 16 05:35:18 PM PDT 24
Peak memory	268460 kb
Host	smart-00e88a1c-a082-48d5-ba6d-b15757725082
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557246942 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.1557246942
Directory	/workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/24.flash_ctrl_sec_info_access.3007450180
Short name	T1086
Test name
Test status
Simulation time	1463283300 ps
CPU time	68.53 seconds
Started	Jul 16 05:35:03 PM PDT 24
Finished	Jul 16 05:36:12 PM PDT 24
Peak memory	264684 kb
Host	smart-143c5806-bd81-465c-ae7a-efd1915f8aec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3007450180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3007450180
Directory	/workspace/24.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/24.flash_ctrl_smoke.1746138889
Short name	T423
Test name
Test status
Simulation time	43036400 ps
CPU time	194.14 seconds
Started	Jul 16 05:34:47 PM PDT 24
Finished	Jul 16 05:38:01 PM PDT 24
Peak memory	277728 kb
Host	smart-802e550a-9cf4-4556-b51a-5809bfb2ddc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746138889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1746138889
Directory	/workspace/24.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.flash_ctrl_alert_test.1883727152
Short name	T769
Test name
Test status
Simulation time	40344400 ps
CPU time	13.89 seconds
Started	Jul 16 05:37:00 PM PDT 24
Finished	Jul 16 05:37:15 PM PDT 24
Peak memory	258184 kb
Host	smart-2cba991f-2efa-4da5-b724-4d2276461264
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883727152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test. 1883727152
Directory	/workspace/25.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.flash_ctrl_disable.1981181786
Short name	T1019
Test name
Test status
Simulation time	41559600 ps
CPU time	21.03 seconds
Started	Jul 16 05:35:02 PM PDT 24
Finished	Jul 16 05:35:23 PM PDT 24
Peak memory	265524 kb
Host	smart-6eb9be14-1858-453e-b744-8b8b7ff95563
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981181786 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_disable.1981181786
Directory	/workspace/25.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/25.flash_ctrl_hw_sec_otp.3491045683
Short name	T582
Test name
Test status
Simulation time	4613274400 ps
CPU time	246.42 seconds
Started	Jul 16 05:35:00 PM PDT 24
Finished	Jul 16 05:39:07 PM PDT 24
Peak memory	263088 kb
Host	smart-0fd9967a-6f24-436f-ab7a-58fdf88f0c9b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491045683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ hw_sec_otp.3491045683
Directory	/workspace/25.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd.3433562891
Short name	T30
Test name
Test status
Simulation time	2001468700 ps
CPU time	189.12 seconds
Started	Jul 16 05:34:58 PM PDT 24
Finished	Jul 16 05:38:08 PM PDT 24
Peak memory	291396 kb
Host	smart-67d1abd6-18e1-450c-b23e-4aae685a29ff
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433562891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla sh_ctrl_intr_rd.3433562891
Directory	/workspace/25.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.2121943129
Short name	T926
Test name
Test status
Simulation time	25914767900 ps
CPU time	349.06 seconds
Started	Jul 16 05:35:03 PM PDT 24
Finished	Jul 16 05:40:52 PM PDT 24
Peak memory	293776 kb
Host	smart-b63dc4cc-b5b2-4671-ba99-91fcd7be21bf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121943129 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.2121943129
Directory	/workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/25.flash_ctrl_otp_reset.969473608
Short name	T661
Test name
Test status
Simulation time	141851900 ps
CPU time	131.29 seconds
Started	Jul 16 05:35:02 PM PDT 24
Finished	Jul 16 05:37:14 PM PDT 24
Peak memory	260912 kb
Host	smart-1809e732-655a-4b11-9784-c875dcf291d8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969473608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ot p_reset.969473608
Directory	/workspace/25.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_prog_reset.1642626864
Short name	T425
Test name
Test status
Simulation time	7298388800 ps
CPU time	161.29 seconds
Started	Jul 16 05:37:00 PM PDT 24
Finished	Jul 16 05:39:43 PM PDT 24
Peak memory	265092 kb
Host	smart-498068d4-531b-4cae-82af-cbf535799a7d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642626864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.flash_ctrl_prog_reset.1642626864
Directory	/workspace/25.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict.862716988
Short name	T878
Test name
Test status
Simulation time	74201000 ps
CPU time	31.48 seconds
Started	Jul 16 05:35:03 PM PDT 24
Finished	Jul 16 05:35:34 PM PDT 24
Peak memory	275692 kb
Host	smart-9eec914b-1956-49ce-9f56-6d7878e4faa6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862716988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla sh_ctrl_rw_evict.862716988
Directory	/workspace/25.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/25.flash_ctrl_sec_info_access.3419831841
Short name	T1007
Test name
Test status
Simulation time	2761739300 ps
CPU time	67.36 seconds
Started	Jul 16 05:35:03 PM PDT 24
Finished	Jul 16 05:36:10 PM PDT 24
Peak memory	263892 kb
Host	smart-c576ff0e-f622-4eb9-b1ce-02fb846275c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3419831841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.3419831841
Directory	/workspace/25.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/25.flash_ctrl_smoke.347993615
Short name	T308
Test name
Test status
Simulation time	58927900 ps
CPU time	72.76 seconds
Started	Jul 16 05:35:00 PM PDT 24
Finished	Jul 16 05:36:13 PM PDT 24
Peak memory	276568 kb
Host	smart-0be351cd-d476-46d6-90f6-2a52ab9cbd2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347993615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.347993615
Directory	/workspace/25.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.flash_ctrl_alert_test.3939622694
Short name	T453
Test name
Test status
Simulation time	101461600 ps
CPU time	13.84 seconds
Started	Jul 16 05:35:10 PM PDT 24
Finished	Jul 16 05:35:24 PM PDT 24
Peak memory	258232 kb
Host	smart-3aab2b8e-e9a0-4fe5-b6af-01e0cc65aebf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939622694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test. 3939622694
Directory	/workspace/26.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.flash_ctrl_connect.2719320146
Short name	T884
Test name
Test status
Simulation time	16142100 ps
CPU time	13.17 seconds
Started	Jul 16 05:36:52 PM PDT 24
Finished	Jul 16 05:37:06 PM PDT 24
Peak memory	274924 kb
Host	smart-4678e73a-8a5a-4f4b-a2ca-cfd8bc2bbb5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2719320146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.2719320146
Directory	/workspace/26.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/26.flash_ctrl_hw_sec_otp.1762141037
Short name	T450
Test name
Test status
Simulation time	17243716600 ps
CPU time	156.99 seconds
Started	Jul 16 05:35:02 PM PDT 24
Finished	Jul 16 05:37:39 PM PDT 24
Peak memory	260892 kb
Host	smart-8dc1fa03-fb99-452e-8a2c-6a8c263d4fc2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762141037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ hw_sec_otp.1762141037
Directory	/workspace/26.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd.3536484658
Short name	T777
Test name
Test status
Simulation time	1466380500 ps
CPU time	220.47 seconds
Started	Jul 16 05:36:12 PM PDT 24
Finished	Jul 16 05:39:53 PM PDT 24
Peak memory	284828 kb
Host	smart-0a55cf07-e55e-48c3-8c97-db966d7a7816
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536484658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla sh_ctrl_intr_rd.3536484658
Directory	/workspace/26.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.2480002490
Short name	T727
Test name
Test status
Simulation time	49807728200 ps
CPU time	280.59 seconds
Started	Jul 16 05:35:12 PM PDT 24
Finished	Jul 16 05:39:53 PM PDT 24
Peak memory	290904 kb
Host	smart-708bec3c-cc5a-4e8d-abce-3661c66b8cb0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480002490 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.2480002490
Directory	/workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/26.flash_ctrl_otp_reset.3089106437
Short name	T65
Test name
Test status
Simulation time	361313600 ps
CPU time	109.97 seconds
Started	Jul 16 05:35:11 PM PDT 24
Finished	Jul 16 05:37:02 PM PDT 24
Peak memory	261024 kb
Host	smart-497f0fa3-fc57-481a-951d-c53ea362a299
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089106437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o tp_reset.3089106437
Directory	/workspace/26.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_prog_reset.2281371863
Short name	T484
Test name
Test status
Simulation time	21186700 ps
CPU time	14.14 seconds
Started	Jul 16 05:35:07 PM PDT 24
Finished	Jul 16 05:35:22 PM PDT 24
Peak memory	265260 kb
Host	smart-f4685a62-327a-42b9-8434-12fccd0b9b37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281371863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.flash_ctrl_prog_reset.2281371863
Directory	/workspace/26.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.1415937867
Short name	T896
Test name
Test status
Simulation time	68658000 ps
CPU time	30.78 seconds
Started	Jul 16 05:35:14 PM PDT 24
Finished	Jul 16 05:35:45 PM PDT 24
Peak memory	268376 kb
Host	smart-d06a999d-de16-4c55-ad39-7786db891667
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415937867 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.1415937867
Directory	/workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/26.flash_ctrl_sec_info_access.1217210130
Short name	T396
Test name
Test status
Simulation time	5882383300 ps
CPU time	73.8 seconds
Started	Jul 16 05:35:09 PM PDT 24
Finished	Jul 16 05:36:23 PM PDT 24
Peak memory	263508 kb
Host	smart-1ca27c08-c0a4-44a4-9736-bf29b76b46db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217210130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.1217210130
Directory	/workspace/26.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/26.flash_ctrl_smoke.2237454308
Short name	T507
Test name
Test status
Simulation time	6108941800 ps
CPU time	186.39 seconds
Started	Jul 16 05:35:03 PM PDT 24
Finished	Jul 16 05:38:10 PM PDT 24
Peak memory	281512 kb
Host	smart-9a97744f-53fb-4ac8-8a87-69b784ae0544
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2237454308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.2237454308
Directory	/workspace/26.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.flash_ctrl_alert_test.396336909
Short name	T475
Test name
Test status
Simulation time	172676100 ps
CPU time	13.33 seconds
Started	Jul 16 05:35:12 PM PDT 24
Finished	Jul 16 05:35:26 PM PDT 24
Peak memory	258472 kb
Host	smart-cb5d0a9b-5588-47a2-8c1b-6cc7bc963f34
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396336909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.396336909
Directory	/workspace/27.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.flash_ctrl_connect.2745069249
Short name	T793
Test name
Test status
Simulation time	23715400 ps
CPU time	15.96 seconds
Started	Jul 16 05:35:09 PM PDT 24
Finished	Jul 16 05:35:26 PM PDT 24
Peak memory	274824 kb
Host	smart-503e2e36-cff5-4ae4-8fab-9dde86fa84f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745069249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.2745069249
Directory	/workspace/27.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/27.flash_ctrl_disable.1583719242
Short name	T379
Test name
Test status
Simulation time	15318300 ps
CPU time	21.79 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:37:18 PM PDT 24
Peak memory	273488 kb
Host	smart-9b03722d-4aef-4671-8098-50df787eb607
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583719242 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_disable.1583719242
Directory	/workspace/27.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3936563812
Short name	T418
Test name
Test status
Simulation time	18106321900 ps
CPU time	216.26 seconds
Started	Jul 16 05:35:12 PM PDT 24
Finished	Jul 16 05:38:49 PM PDT 24
Peak memory	262376 kb
Host	smart-a9a19dcf-8bcf-4101-bb67-c46a013aeb00
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936563812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ hw_sec_otp.3936563812
Directory	/workspace/27.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd.2905161119
Short name	T822
Test name
Test status
Simulation time	1975804000 ps
CPU time	164.31 seconds
Started	Jul 16 05:35:08 PM PDT 24
Finished	Jul 16 05:37:52 PM PDT 24
Peak memory	294232 kb
Host	smart-3135cb10-07f3-466c-8469-28834b745986
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905161119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla sh_ctrl_intr_rd.2905161119
Directory	/workspace/27.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.907796067
Short name	T647
Test name
Test status
Simulation time	11635573200 ps
CPU time	143.13 seconds
Started	Jul 16 05:35:08 PM PDT 24
Finished	Jul 16 05:37:32 PM PDT 24
Peak memory	284908 kb
Host	smart-814d451a-9dd9-449e-b75c-493872be3277
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907796067 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.907796067
Directory	/workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/27.flash_ctrl_otp_reset.4002540325
Short name	T751
Test name
Test status
Simulation time	41347000 ps
CPU time	134.2 seconds
Started	Jul 16 05:37:00 PM PDT 24
Finished	Jul 16 05:39:16 PM PDT 24
Peak memory	260944 kb
Host	smart-2bfd0c2a-efd2-4133-9c33-da3b0d3508d9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002540325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o tp_reset.4002540325
Directory	/workspace/27.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_prog_reset.3765111207
Short name	T465
Test name
Test status
Simulation time	4088209500 ps
CPU time	170.68 seconds
Started	Jul 16 05:35:12 PM PDT 24
Finished	Jul 16 05:38:03 PM PDT 24
Peak memory	265224 kb
Host	smart-ad1d1a7a-8837-41b8-b5b2-ae9421a4f535
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765111207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.flash_ctrl_prog_reset.3765111207
Directory	/workspace/27.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict.2521847026
Short name	T526
Test name
Test status
Simulation time	28738100 ps
CPU time	30.92 seconds
Started	Jul 16 05:35:08 PM PDT 24
Finished	Jul 16 05:35:40 PM PDT 24
Peak memory	273512 kb
Host	smart-6b3e3fb9-a7b3-4d82-8a9a-26af6b0921bd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521847026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl ash_ctrl_rw_evict.2521847026
Directory	/workspace/27.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/27.flash_ctrl_smoke.699917103
Short name	T246
Test name
Test status
Simulation time	141312900 ps
CPU time	166.24 seconds
Started	Jul 16 05:35:09 PM PDT 24
Finished	Jul 16 05:37:56 PM PDT 24
Peak memory	277320 kb
Host	smart-a3ecb4b1-7296-43a5-ab0b-37305403828e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699917103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.699917103
Directory	/workspace/27.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.flash_ctrl_connect.2473237751
Short name	T556
Test name
Test status
Simulation time	61265800 ps
CPU time	15.63 seconds
Started	Jul 16 05:36:48 PM PDT 24
Finished	Jul 16 05:37:04 PM PDT 24
Peak memory	284344 kb
Host	smart-f4e4ecf1-a0af-4276-a414-43943adf7105
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473237751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.2473237751
Directory	/workspace/28.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/28.flash_ctrl_disable.3484744435
Short name	T91
Test name
Test status
Simulation time	29501700 ps
CPU time	22.03 seconds
Started	Jul 16 05:35:21 PM PDT 24
Finished	Jul 16 05:35:44 PM PDT 24
Peak memory	274244 kb
Host	smart-b3017b86-7d57-4612-916c-25ac7e149b56
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484744435 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_disable.3484744435
Directory	/workspace/28.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2595467283
Short name	T913
Test name
Test status
Simulation time	6678618300 ps
CPU time	80.72 seconds
Started	Jul 16 05:36:46 PM PDT 24
Finished	Jul 16 05:38:08 PM PDT 24
Peak memory	263220 kb
Host	smart-4fb4bf74-0a8f-4460-9a9d-49b6d5ba2969
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595467283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ hw_sec_otp.2595467283
Directory	/workspace/28.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd.3969761010
Short name	T279
Test name
Test status
Simulation time	2890830700 ps
CPU time	134.63 seconds
Started	Jul 16 05:35:12 PM PDT 24
Finished	Jul 16 05:37:27 PM PDT 24
Peak memory	293424 kb
Host	smart-3ccc6e61-4aea-4c59-944c-73e46c40daa2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969761010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla sh_ctrl_intr_rd.3969761010
Directory	/workspace/28.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.619495600
Short name	T33
Test name
Test status
Simulation time	210250203000 ps
CPU time	325.22 seconds
Started	Jul 16 05:36:47 PM PDT 24
Finished	Jul 16 05:42:13 PM PDT 24
Peak memory	291776 kb
Host	smart-f5956dd6-68ac-4c6d-aada-e47fe90e81c2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619495600 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.619495600
Directory	/workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/28.flash_ctrl_otp_reset.410726428
Short name	T714
Test name
Test status
Simulation time	36957200 ps
CPU time	131.34 seconds
Started	Jul 16 05:36:53 PM PDT 24
Finished	Jul 16 05:39:05 PM PDT 24
Peak memory	262256 kb
Host	smart-ee1d4569-5043-440f-8bab-3c4bf8007c67
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410726428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ot p_reset.410726428
Directory	/workspace/28.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_prog_reset.2427606035
Short name	T687
Test name
Test status
Simulation time	57844900 ps
CPU time	13.84 seconds
Started	Jul 16 05:35:25 PM PDT 24
Finished	Jul 16 05:35:40 PM PDT 24
Peak memory	265344 kb
Host	smart-2d95c80d-fe6e-4117-878e-09518e87b8f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427606035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.flash_ctrl_prog_reset.2427606035
Directory	/workspace/28.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict.3148762676
Short name	T513
Test name
Test status
Simulation time	30992600 ps
CPU time	31.24 seconds
Started	Jul 16 05:35:20 PM PDT 24
Finished	Jul 16 05:35:51 PM PDT 24
Peak memory	275592 kb
Host	smart-13bcf9fe-7eb9-48b9-82b4-b9ab3eef643e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148762676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl ash_ctrl_rw_evict.3148762676
Directory	/workspace/28.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.2965273204
Short name	T968
Test name
Test status
Simulation time	27029800 ps
CPU time	31 seconds
Started	Jul 16 05:35:21 PM PDT 24
Finished	Jul 16 05:35:53 PM PDT 24
Peak memory	275636 kb
Host	smart-aba4399b-0ec1-4d6f-820d-35b502d53414
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965273204 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.2965273204
Directory	/workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/28.flash_ctrl_sec_info_access.3408805445
Short name	T797
Test name
Test status
Simulation time	1189473900 ps
CPU time	61.72 seconds
Started	Jul 16 05:35:19 PM PDT 24
Finished	Jul 16 05:36:21 PM PDT 24
Peak memory	263576 kb
Host	smart-ee3e7f53-7414-4779-82f6-804ef22245ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408805445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.3408805445
Directory	/workspace/28.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/28.flash_ctrl_smoke.2783212299
Short name	T548
Test name
Test status
Simulation time	1361399500 ps
CPU time	242.84 seconds
Started	Jul 16 05:35:12 PM PDT 24
Finished	Jul 16 05:39:15 PM PDT 24
Peak memory	281648 kb
Host	smart-73f4aa94-dd9b-4606-a549-b219e3fd6459
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783212299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2783212299
Directory	/workspace/28.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.flash_ctrl_alert_test.4086089476
Short name	T742
Test name
Test status
Simulation time	56339900 ps
CPU time	14.05 seconds
Started	Jul 16 05:35:22 PM PDT 24
Finished	Jul 16 05:35:36 PM PDT 24
Peak memory	258124 kb
Host	smart-8522e96b-889f-4271-ae01-8850942c6e8e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086089476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test. 4086089476
Directory	/workspace/29.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.flash_ctrl_connect.3857878859
Short name	T706
Test name
Test status
Simulation time	15376700 ps
CPU time	15.77 seconds
Started	Jul 16 05:35:27 PM PDT 24
Finished	Jul 16 05:35:43 PM PDT 24
Peak memory	284352 kb
Host	smart-e9d52cbb-50ef-488f-a4e9-fb748882047e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857878859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.3857878859
Directory	/workspace/29.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/29.flash_ctrl_disable.3306442406
Short name	T389
Test name
Test status
Simulation time	72334500 ps
CPU time	21.98 seconds
Started	Jul 16 05:35:21 PM PDT 24
Finished	Jul 16 05:35:43 PM PDT 24
Peak memory	273720 kb
Host	smart-f83e2cad-bd15-49d1-b901-df59b69c45ef
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306442406 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_disable.3306442406
Directory	/workspace/29.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.4192949273
Short name	T1063
Test name
Test status
Simulation time	19735864800 ps
CPU time	140.69 seconds
Started	Jul 16 05:35:21 PM PDT 24
Finished	Jul 16 05:37:42 PM PDT 24
Peak memory	260872 kb
Host	smart-ef343886-04a9-4dfd-a71b-88aa547f8577
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192949273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ hw_sec_otp.4192949273
Directory	/workspace/29.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd.3204171840
Short name	T1074
Test name
Test status
Simulation time	4849281500 ps
CPU time	235.62 seconds
Started	Jul 16 05:35:21 PM PDT 24
Finished	Jul 16 05:39:17 PM PDT 24
Peak memory	291536 kb
Host	smart-fdf3a60d-f850-412b-89f4-c37586259f99
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204171840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla sh_ctrl_intr_rd.3204171840
Directory	/workspace/29.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.3546166520
Short name	T675
Test name
Test status
Simulation time	11929942500 ps
CPU time	283.39 seconds
Started	Jul 16 05:37:00 PM PDT 24
Finished	Jul 16 05:41:45 PM PDT 24
Peak memory	291920 kb
Host	smart-9b0b9404-1cca-4917-8e88-09eef79573e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546166520 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.3546166520
Directory	/workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/29.flash_ctrl_otp_reset.67753910
Short name	T992
Test name
Test status
Simulation time	73240100 ps
CPU time	131.44 seconds
Started	Jul 16 05:35:21 PM PDT 24
Finished	Jul 16 05:37:33 PM PDT 24
Peak memory	259968 kb
Host	smart-467bef41-19c6-4276-958f-5ccae696ea73
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67753910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp _reset.67753910
Directory	/workspace/29.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_prog_reset.375803401
Short name	T1048
Test name
Test status
Simulation time	200767400 ps
CPU time	13.72 seconds
Started	Jul 16 05:35:21 PM PDT 24
Finished	Jul 16 05:35:35 PM PDT 24
Peak memory	259120 kb
Host	smart-19e5f43e-7487-4298-bee2-1ff3aed96a17
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375803401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.flash_ctrl_prog_reset.375803401
Directory	/workspace/29.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict.328904539
Short name	T732
Test name
Test status
Simulation time	106495700 ps
CPU time	30.2 seconds
Started	Jul 16 05:35:20 PM PDT 24
Finished	Jul 16 05:35:51 PM PDT 24
Peak memory	275640 kb
Host	smart-a2a8ed2f-610b-4986-bdbd-d3c3132ae353
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328904539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla sh_ctrl_rw_evict.328904539
Directory	/workspace/29.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.1131068107
Short name	T357
Test name
Test status
Simulation time	46419800 ps
CPU time	27.96 seconds
Started	Jul 16 05:36:45 PM PDT 24
Finished	Jul 16 05:37:14 PM PDT 24
Peak memory	275708 kb
Host	smart-8044faa3-0039-4276-8d77-201290e73606
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131068107 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.1131068107
Directory	/workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/29.flash_ctrl_sec_info_access.3354278808
Short name	T611
Test name
Test status
Simulation time	1692858700 ps
CPU time	78.46 seconds
Started	Jul 16 05:35:24 PM PDT 24
Finished	Jul 16 05:36:43 PM PDT 24
Peak memory	263712 kb
Host	smart-f2942e85-a179-4b5d-bfdc-cc47f0a44e19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3354278808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3354278808
Directory	/workspace/29.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/29.flash_ctrl_smoke.4050819647
Short name	T437
Test name
Test status
Simulation time	102954100 ps
CPU time	99.9 seconds
Started	Jul 16 05:35:20 PM PDT 24
Finished	Jul 16 05:37:00 PM PDT 24
Peak memory	276108 kb
Host	smart-8d5e4efa-c0a0-4bf9-a99e-1d3d6da3ce65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050819647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.4050819647
Directory	/workspace/29.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_alert_test.3026108441
Short name	T516
Test name
Test status
Simulation time	155021300 ps
CPU time	14.57 seconds
Started	Jul 16 05:30:55 PM PDT 24
Finished	Jul 16 05:31:10 PM PDT 24
Peak memory	258376 kb
Host	smart-81d565fb-3b2d-4130-a874-d26fe4e3aceb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026108441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.3 026108441
Directory	/workspace/3.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.flash_ctrl_config_regwen.3690113260
Short name	T1079
Test name
Test status
Simulation time	22454600 ps
CPU time	13.81 seconds
Started	Jul 16 05:31:40 PM PDT 24
Finished	Jul 16 05:31:55 PM PDT 24
Peak memory	264888 kb
Host	smart-c87eb44e-f009-46ce-9bae-bbb3d0a69981
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690113260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .flash_ctrl_config_regwen.3690113260
Directory	/workspace/3.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/3.flash_ctrl_connect.3278914032
Short name	T383
Test name
Test status
Simulation time	13352500 ps
CPU time	15.59 seconds
Started	Jul 16 05:30:42 PM PDT 24
Finished	Jul 16 05:30:58 PM PDT 24
Peak memory	274884 kb
Host	smart-06cb7431-0025-4cff-8a4d-61a749e484ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3278914032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.3278914032
Directory	/workspace/3.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/3.flash_ctrl_disable.1884499673
Short name	T1057
Test name
Test status
Simulation time	46187200 ps
CPU time	20.93 seconds
Started	Jul 16 05:32:34 PM PDT 24
Finished	Jul 16 05:32:56 PM PDT 24
Peak memory	273560 kb
Host	smart-34b8e9a2-9174-47e3-8692-2bac1d4fab18
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884499673 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_disable.1884499673
Directory	/workspace/3.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_mp.814488849
Short name	T951
Test name
Test status
Simulation time	12708725800 ps
CPU time	2369.87 seconds
Started	Jul 16 05:30:29 PM PDT 24
Finished	Jul 16 06:10:00 PM PDT 24
Peak memory	262812 kb
Host	smart-8299a705-3680-4ad5-8331-6565728a3527
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=814488849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.814488849
Directory	/workspace/3.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_type.1136488484
Short name	T79
Test name
Test status
Simulation time	3532669900 ps
CPU time	2216.51 seconds
Started	Jul 16 05:30:30 PM PDT 24
Finished	Jul 16 06:07:27 PM PDT 24
Peak memory	265008 kb
Host	smart-a171eb97-7843-4248-8b11-54a4c3113e07
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136488484 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.1136488484
Directory	/workspace/3.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fetch_code.2842397517
Short name	T561
Test name
Test status
Simulation time	280381600 ps
CPU time	22.28 seconds
Started	Jul 16 05:30:30 PM PDT 24
Finished	Jul 16 05:30:54 PM PDT 24
Peak memory	263556 kb
Host	smart-60a8348a-cc5e-4ef7-b6db-c80678f80c11
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842397517 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.2842397517
Directory	/workspace/3.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fs_sup.1503329733
Short name	T77
Test name
Test status
Simulation time	746433300 ps
CPU time	41.32 seconds
Started	Jul 16 05:30:43 PM PDT 24
Finished	Jul 16 05:31:25 PM PDT 24
Peak memory	262868 kb
Host	smart-8d7fab5e-8b52-45d2-90b7-f8aab7d362b7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503329733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 3.flash_ctrl_fs_sup.1503329733
Directory	/workspace/3.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/3.flash_ctrl_full_mem_access.843190575
Short name	T137
Test name
Test status
Simulation time	325513182100 ps
CPU time	2878.35 seconds
Started	Jul 16 05:34:24 PM PDT 24
Finished	Jul 16 06:22:24 PM PDT 24
Peak memory	265136 kb
Host	smart-b9c75214-ab3e-48b7-ac9d-7e410d420396
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843190575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct rl_full_mem_access.843190575
Directory	/workspace/3.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_dir_rd.3754473692
Short name	T646
Test name
Test status
Simulation time	109465300 ps
CPU time	35.16 seconds
Started	Jul 16 05:30:17 PM PDT 24
Finished	Jul 16 05:30:53 PM PDT 24
Peak memory	265224 kb
Host	smart-8a48691a-9a9b-41ad-9439-ea62e6a794a8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3754473692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3754473692
Directory	/workspace/3.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3374990984
Short name	T285
Test name
Test status
Simulation time	10011747300 ps
CPU time	118.97 seconds
Started	Jul 16 05:35:29 PM PDT 24
Finished	Jul 16 05:37:28 PM PDT 24
Peak memory	322180 kb
Host	smart-507b30f2-6e5f-4288-b330-178dc33b45b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374990984 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.3374990984
Directory	/workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.1977390151
Short name	T283
Test name
Test status
Simulation time	33738900 ps
CPU time	13.37 seconds
Started	Jul 16 05:30:59 PM PDT 24
Finished	Jul 16 05:31:13 PM PDT 24
Peak memory	258564 kb
Host	smart-9a596438-4787-4834-826f-0f2631ae0f51
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977390151 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.1977390151
Directory	/workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_rma_reset.3469886388
Short name	T178
Test name
Test status
Simulation time	40120992300 ps
CPU time	833.29 seconds
Started	Jul 16 05:30:16 PM PDT 24
Finished	Jul 16 05:44:11 PM PDT 24
Peak memory	264640 kb
Host	smart-6268ec63-4383-4c0b-aed6-d31a6c4597a5
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469886388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 3.flash_ctrl_hw_rma_reset.3469886388
Directory	/workspace/3.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1292669848
Short name	T949
Test name
Test status
Simulation time	1130574700 ps
CPU time	33.57 seconds
Started	Jul 16 05:30:17 PM PDT 24
Finished	Jul 16 05:30:52 PM PDT 24
Peak memory	262220 kb
Host	smart-a0eaaa2a-21a0-4ce0-b4ad-1bea053562ff
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292669848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h w_sec_otp.1292669848
Directory	/workspace/3.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_integrity.2682018556
Short name	T238
Test name
Test status
Simulation time	19811530300 ps
CPU time	752.76 seconds
Started	Jul 16 05:30:44 PM PDT 24
Finished	Jul 16 05:43:18 PM PDT 24
Peak memory	342264 kb
Host	smart-2f54780e-440e-45f8-977e-48fb2c9bac93
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682018556 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_integrity.2682018556
Directory	/workspace/3.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd.3833524592
Short name	T332
Test name
Test status
Simulation time	7095970300 ps
CPU time	254.34 seconds
Started	Jul 16 05:30:44 PM PDT 24
Finished	Jul 16 05:35:00 PM PDT 24
Peak memory	291416 kb
Host	smart-5fae9835-b75c-4f87-bcc5-4b2b4305d898
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833524592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_intr_rd.3833524592
Directory	/workspace/3.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1755443194
Short name	T1105
Test name
Test status
Simulation time	44185426800 ps
CPU time	298.08 seconds
Started	Jul 16 05:30:42 PM PDT 24
Finished	Jul 16 05:35:41 PM PDT 24
Peak memory	290960 kb
Host	smart-b6ae4d54-b29e-42b0-b00a-7e68845f8ac8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755443194 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.1755443194
Directory	/workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr.136698485
Short name	T141
Test name
Test status
Simulation time	4310803000 ps
CPU time	64.62 seconds
Started	Jul 16 05:34:14 PM PDT 24
Finished	Jul 16 05:35:19 PM PDT 24
Peak memory	260684 kb
Host	smart-2137207d-3248-4d7c-b387-930e43277ad7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136698485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.flash_ctrl_intr_wr.136698485
Directory	/workspace/3.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3585082117
Short name	T959
Test name
Test status
Simulation time	26261106900 ps
CPU time	193.38 seconds
Started	Jul 16 05:30:45 PM PDT 24
Finished	Jul 16 05:33:59 PM PDT 24
Peak memory	265364 kb
Host	smart-fb2cad0d-f07b-406f-ae67-7275e926d1a2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358 5082117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3585082117
Directory	/workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_invalid_op.310332198
Short name	T445
Test name
Test status
Simulation time	7490710000 ps
CPU time	80.77 seconds
Started	Jul 16 05:30:28 PM PDT 24
Finished	Jul 16 05:31:50 PM PDT 24
Peak memory	260604 kb
Host	smart-a6350d50-09f4-424a-87af-16979731e6ab
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310332198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.310332198
Directory	/workspace/3.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_lcmgr_intg.1746795345
Short name	T289
Test name
Test status
Simulation time	28629600 ps
CPU time	13.29 seconds
Started	Jul 16 05:30:58 PM PDT 24
Finished	Jul 16 05:31:12 PM PDT 24
Peak memory	259952 kb
Host	smart-ae2c4fcd-ea16-4ee0-a19a-63d9af5ba185
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746795345 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.1746795345
Directory	/workspace/3.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mid_op_rst.2963357616
Short name	T85
Test name
Test status
Simulation time	5477069500 ps
CPU time	74.17 seconds
Started	Jul 16 05:30:25 PM PDT 24
Finished	Jul 16 05:31:41 PM PDT 24
Peak memory	260664 kb
Host	smart-af10fd01-70f4-4eba-9ed2-bd802d331e04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963357616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.2963357616
Directory	/workspace/3.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mp_regions.2500174976
Short name	T938
Test name
Test status
Simulation time	20406174400 ps
CPU time	239.3 seconds
Started	Jul 16 05:30:29 PM PDT 24
Finished	Jul 16 05:34:30 PM PDT 24
Peak memory	274220 kb
Host	smart-54485f0c-1914-4bd8-8a66-e7a2c25c134c
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500174976 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.2500174976
Directory	/workspace/3.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/3.flash_ctrl_otp_reset.4233320217
Short name	T805
Test name
Test status
Simulation time	50509300 ps
CPU time	132.62 seconds
Started	Jul 16 05:30:16 PM PDT 24
Finished	Jul 16 05:32:30 PM PDT 24
Peak memory	265068 kb
Host	smart-16c8c511-90ad-4469-8c43-0af838d95706
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233320217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot p_reset.4233320217
Directory	/workspace/3.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_oversize_error.1885270719
Short name	T522
Test name
Test status
Simulation time	3938130000 ps
CPU time	243.5 seconds
Started	Jul 16 05:30:25 PM PDT 24
Finished	Jul 16 05:34:30 PM PDT 24
Peak memory	281704 kb
Host	smart-b004a76e-5a45-48c1-9247-8065c4bf216a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885270719 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.1885270719
Directory	/workspace/3.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.1614351730
Short name	T215
Test name
Test status
Simulation time	45490400 ps
CPU time	15.01 seconds
Started	Jul 16 05:30:54 PM PDT 24
Finished	Jul 16 05:31:10 PM PDT 24
Peak memory	265052 kb
Host	smart-6132c99d-7aab-44cc-8887-8c997d690bee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1614351730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1614351730
Directory	/workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb.3429872307
Short name	T1036
Test name
Test status
Simulation time	104553500 ps
CPU time	403.05 seconds
Started	Jul 16 05:30:30 PM PDT 24
Finished	Jul 16 05:37:14 PM PDT 24
Peak memory	263024 kb
Host	smart-670343eb-a4f1-429a-9a85-6d01b164fa0f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3429872307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.3429872307
Directory	/workspace/3.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.2462783502
Short name	T69
Test name
Test status
Simulation time	857362100 ps
CPU time	16.85 seconds
Started	Jul 16 05:31:39 PM PDT 24
Finished	Jul 16 05:31:57 PM PDT 24
Peak memory	265396 kb
Host	smart-221c94e5-8c7d-4db2-83f3-a6b64d7c71ee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462783502 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.2462783502
Directory	/workspace/3.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/3.flash_ctrl_prog_reset.3557276861
Short name	T639
Test name
Test status
Simulation time	77850800 ps
CPU time	13.79 seconds
Started	Jul 16 05:30:43 PM PDT 24
Finished	Jul 16 05:30:58 PM PDT 24
Peak memory	259412 kb
Host	smart-00a91fbc-1614-4caa-95f8-f682b4eb197a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557276861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.flash_ctrl_prog_reset.3557276861
Directory	/workspace/3.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rand_ops.770942039
Short name	T615
Test name
Test status
Simulation time	947907400 ps
CPU time	789.45 seconds
Started	Jul 16 05:30:21 PM PDT 24
Finished	Jul 16 05:43:31 PM PDT 24
Peak memory	284660 kb
Host	smart-962dc8d8-eb7e-4242-96b3-1112839b870e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=770942039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.770942039
Directory	/workspace/3.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rd_buff_evict.3168081631
Short name	T60
Test name
Test status
Simulation time	831283200 ps
CPU time	157.32 seconds
Started	Jul 16 05:30:14 PM PDT 24
Finished	Jul 16 05:32:52 PM PDT 24
Peak memory	262904 kb
Host	smart-0e05ac3c-eaaa-4523-8ca2-8fa53a0a28f9
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3168081631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.3168081631
Directory	/workspace/3.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_re_evict.3006845398
Short name	T349
Test name
Test status
Simulation time	79816400 ps
CPU time	32.11 seconds
Started	Jul 16 05:34:24 PM PDT 24
Finished	Jul 16 05:34:57 PM PDT 24
Peak memory	270336 kb
Host	smart-b7b0c878-9be3-4911-88b6-8e5749d9ff1c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006845398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_re_evict.3006845398
Directory	/workspace/3.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.58739307
Short name	T815
Test name
Test status
Simulation time	238562700 ps
CPU time	23.28 seconds
Started	Jul 16 05:32:34 PM PDT 24
Finished	Jul 16 05:32:58 PM PDT 24
Peak memory	264944 kb
Host	smart-192e3de9-e3db-4c9d-bc72-2b6bc0ee0278
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58739307 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.58739307
Directory	/workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.2588731708
Short name	T1047
Test name
Test status
Simulation time	26808000 ps
CPU time	23.34 seconds
Started	Jul 16 05:36:53 PM PDT 24
Finished	Jul 16 05:37:17 PM PDT 24
Peak memory	265336 kb
Host	smart-c8236ab1-64c6-45f3-bd40-c3b930e080a2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588731708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl ash_ctrl_read_word_sweep_serr.2588731708
Directory	/workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro.2301201809
Short name	T708
Test name
Test status
Simulation time	1802681200 ps
CPU time	112.38 seconds
Started	Jul 16 05:30:28 PM PDT 24
Finished	Jul 16 05:32:21 PM PDT 24
Peak memory	280936 kb
Host	smart-ba7bc3e7-45d9-43a2-8258-06482eb87965
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301201809 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_ro.2301201809
Directory	/workspace/3.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_derr.3140845051
Short name	T203
Test name
Test status
Simulation time	641474800 ps
CPU time	137.6 seconds
Started	Jul 16 05:30:27 PM PDT 24
Finished	Jul 16 05:32:46 PM PDT 24
Peak memory	281724 kb
Host	smart-512e593b-6a03-41ea-bdfc-5c784199cd1b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3140845051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.3140845051
Directory	/workspace/3.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_serr.3936099757
Short name	T692
Test name
Test status
Simulation time	680949800 ps
CPU time	127.81 seconds
Started	Jul 16 05:30:27 PM PDT 24
Finished	Jul 16 05:32:36 PM PDT 24
Peak memory	290220 kb
Host	smart-30978e6b-3c5d-4a89-b339-96ac9df321a4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936099757 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.3936099757
Directory	/workspace/3.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw.3467103658
Short name	T679
Test name
Test status
Simulation time	14611581600 ps
CPU time	505.45 seconds
Started	Jul 16 05:30:25 PM PDT 24
Finished	Jul 16 05:38:52 PM PDT 24
Peak memory	314432 kb
Host	smart-455063b1-fcc0-43f8-a865-9eb8fa5a5a98
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467103658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.flash_ctrl_rw.3467103658
Directory	/workspace/3.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.957443476
Short name	T1059
Test name
Test status
Simulation time	43219400 ps
CPU time	31.17 seconds
Started	Jul 16 05:30:43 PM PDT 24
Finished	Jul 16 05:31:15 PM PDT 24
Peak memory	275608 kb
Host	smart-c396d4c9-12f9-4b02-b726-4e616b8f641f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957443476 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.957443476
Directory	/workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_serr.1336578335
Short name	T616
Test name
Test status
Simulation time	21686341600 ps
CPU time	485.92 seconds
Started	Jul 16 05:30:28 PM PDT 24
Finished	Jul 16 05:38:35 PM PDT 24
Peak memory	320896 kb
Host	smart-0f67d7c9-189f-4566-b7f0-9eed52c5cad6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336578335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s err.1336578335
Directory	/workspace/3.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_cm.2418506457
Short name	T15
Test name
Test status
Simulation time	6775138800 ps
CPU time	4811.7 seconds
Started	Jul 16 05:30:46 PM PDT 24
Finished	Jul 16 06:50:59 PM PDT 24
Peak memory	290484 kb
Host	smart-e8e022c7-e4ab-4e49-8f18-ccc2e9afaa74
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418506457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.2418506457
Directory	/workspace/3.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_address.2101296133
Short name	T931
Test name
Test status
Simulation time	1402283100 ps
CPU time	77.54 seconds
Started	Jul 16 05:30:30 PM PDT 24
Finished	Jul 16 05:31:49 PM PDT 24
Peak memory	265080 kb
Host	smart-d683e0a8-9776-4407-b56e-313d54a09d58
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101296133 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_serr_address.2101296133
Directory	/workspace/3.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_counter.261815069
Short name	T469
Test name
Test status
Simulation time	491831500 ps
CPU time	55.38 seconds
Started	Jul 16 05:34:24 PM PDT 24
Finished	Jul 16 05:35:21 PM PDT 24
Peak memory	274948 kb
Host	smart-ba152454-f192-46bc-9215-3e7170929f15
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261815069 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_serr_counter.261815069
Directory	/workspace/3.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke.3997579880
Short name	T813
Test name
Test status
Simulation time	37027500 ps
CPU time	119.11 seconds
Started	Jul 16 05:30:30 PM PDT 24
Finished	Jul 16 05:32:30 PM PDT 24
Peak memory	277524 kb
Host	smart-c799ac68-e279-4bbc-91dc-53c9035e0b1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997579880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3997579880
Directory	/workspace/3.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke_hw.3789073557
Short name	T1111
Test name
Test status
Simulation time	16203600 ps
CPU time	23.91 seconds
Started	Jul 16 05:30:17 PM PDT 24
Finished	Jul 16 05:30:42 PM PDT 24
Peak memory	259696 kb
Host	smart-99920bec-ce5a-45d9-b2ac-f6b5d796a636
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3789073557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3789073557
Directory	/workspace/3.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_stress_all.3882115609
Short name	T773
Test name
Test status
Simulation time	209824700 ps
CPU time	808.17 seconds
Started	Jul 16 05:30:42 PM PDT 24
Finished	Jul 16 05:44:10 PM PDT 24
Peak memory	289692 kb
Host	smart-b0a8763d-0963-4310-8cd5-878bc00082ea
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882115609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres s_all.3882115609
Directory	/workspace/3.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sw_op.2615896528
Short name	T518
Test name
Test status
Simulation time	82974100 ps
CPU time	26 seconds
Started	Jul 16 05:30:29 PM PDT 24
Finished	Jul 16 05:30:56 PM PDT 24
Peak memory	259232 kb
Host	smart-2196391d-5c21-423f-8224-1079673a4203
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2615896528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.2615896528
Directory	/workspace/3.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_wo.1032971258
Short name	T385
Test name
Test status
Simulation time	2853608000 ps
CPU time	176.72 seconds
Started	Jul 16 05:36:09 PM PDT 24
Finished	Jul 16 05:39:06 PM PDT 24
Peak memory	265328 kb
Host	smart-3042dee1-d0d6-4794-9f4e-20ddfafbb0be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032971258 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.flash_ctrl_wo.1032971258
Directory	/workspace/3.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/30.flash_ctrl_alert_test.345987972
Short name	T847
Test name
Test status
Simulation time	59335000 ps
CPU time	13.84 seconds
Started	Jul 16 05:35:42 PM PDT 24
Finished	Jul 16 05:35:56 PM PDT 24
Peak memory	265064 kb
Host	smart-9626df75-4120-4a40-9606-9525141677b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345987972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.345987972
Directory	/workspace/30.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.flash_ctrl_connect.3095279730
Short name	T782
Test name
Test status
Simulation time	16317400 ps
CPU time	13.29 seconds
Started	Jul 16 05:35:35 PM PDT 24
Finished	Jul 16 05:35:48 PM PDT 24
Peak memory	275000 kb
Host	smart-46018ed7-28e0-42ed-9b41-deaafb1493f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3095279730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3095279730
Directory	/workspace/30.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/30.flash_ctrl_disable.19475241
Short name	T40
Test name
Test status
Simulation time	16267700 ps
CPU time	21.89 seconds
Started	Jul 16 05:35:42 PM PDT 24
Finished	Jul 16 05:36:04 PM PDT 24
Peak memory	273460 kb
Host	smart-72595869-542f-4015-b59d-bb389053f3db
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19475241 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 30.flash_ctrl_disable.19475241
Directory	/workspace/30.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/30.flash_ctrl_hw_sec_otp.376101106
Short name	T535
Test name
Test status
Simulation time	1595065800 ps
CPU time	73.53 seconds
Started	Jul 16 05:35:34 PM PDT 24
Finished	Jul 16 05:36:47 PM PDT 24
Peak memory	262756 kb
Host	smart-7e317d0d-3a29-42a3-9e76-bdda835f88b0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376101106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_h w_sec_otp.376101106
Directory	/workspace/30.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd.415521704
Short name	T336
Test name
Test status
Simulation time	14652423500 ps
CPU time	216.95 seconds
Started	Jul 16 05:35:34 PM PDT 24
Finished	Jul 16 05:39:11 PM PDT 24
Peak memory	284972 kb
Host	smart-24089789-86fc-48cd-956c-ac5754b558f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415521704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flas h_ctrl_intr_rd.415521704
Directory	/workspace/30.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.69198075
Short name	T1062
Test name
Test status
Simulation time	202443930100 ps
CPU time	315.19 seconds
Started	Jul 16 05:35:37 PM PDT 24
Finished	Jul 16 05:40:52 PM PDT 24
Peak memory	289804 kb
Host	smart-4be3d6d4-6760-437f-a87c-49d098f51ad1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69198075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.69198075
Directory	/workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/30.flash_ctrl_otp_reset.865066879
Short name	T542
Test name
Test status
Simulation time	76220100 ps
CPU time	130.4 seconds
Started	Jul 16 05:35:33 PM PDT 24
Finished	Jul 16 05:37:44 PM PDT 24
Peak memory	265076 kb
Host	smart-a4a44ac4-fb2b-41ea-8f78-9bc82a7725f6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865066879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_ot p_reset.865066879
Directory	/workspace/30.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict.2422265962
Short name	T48
Test name
Test status
Simulation time	53840200 ps
CPU time	30.97 seconds
Started	Jul 16 05:35:36 PM PDT 24
Finished	Jul 16 05:36:08 PM PDT 24
Peak memory	268464 kb
Host	smart-9bc0f123-b628-4f20-ab11-63a46e376f1c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422265962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl ash_ctrl_rw_evict.2422265962
Directory	/workspace/30.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3719384009
Short name	T643
Test name
Test status
Simulation time	45025400 ps
CPU time	30.56 seconds
Started	Jul 16 05:35:33 PM PDT 24
Finished	Jul 16 05:36:04 PM PDT 24
Peak memory	275568 kb
Host	smart-55479307-57e4-4f89-bd5e-dd8a601d142a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719384009 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.3719384009
Directory	/workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/30.flash_ctrl_sec_info_access.3673717139
Short name	T395
Test name
Test status
Simulation time	10553095500 ps
CPU time	67.07 seconds
Started	Jul 16 05:35:34 PM PDT 24
Finished	Jul 16 05:36:41 PM PDT 24
Peak memory	263616 kb
Host	smart-4b2ab098-c0c4-443b-b6ec-eccbb9997679
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673717139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.3673717139
Directory	/workspace/30.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/30.flash_ctrl_smoke.2802332656
Short name	T759
Test name
Test status
Simulation time	25777700 ps
CPU time	96.84 seconds
Started	Jul 16 05:35:33 PM PDT 24
Finished	Jul 16 05:37:10 PM PDT 24
Peak memory	276240 kb
Host	smart-d6a41e11-1c97-475d-b099-09d8a4741237
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2802332656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.2802332656
Directory	/workspace/30.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.flash_ctrl_alert_test.2781567782
Short name	T919
Test name
Test status
Simulation time	161481100 ps
CPU time	13.53 seconds
Started	Jul 16 05:35:54 PM PDT 24
Finished	Jul 16 05:36:08 PM PDT 24
Peak memory	258140 kb
Host	smart-f802ae4f-3726-4def-9404-4c1cdd7b3998
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781567782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test. 2781567782
Directory	/workspace/31.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.flash_ctrl_connect.2207220212
Short name	T772
Test name
Test status
Simulation time	98980500 ps
CPU time	16.05 seconds
Started	Jul 16 05:35:42 PM PDT 24
Finished	Jul 16 05:35:58 PM PDT 24
Peak memory	274972 kb
Host	smart-89759f7b-c0f7-4541-8d30-0bf7a0270268
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2207220212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.2207220212
Directory	/workspace/31.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/31.flash_ctrl_disable.1464169502
Short name	T12
Test name
Test status
Simulation time	13291100 ps
CPU time	21.46 seconds
Started	Jul 16 05:36:45 PM PDT 24
Finished	Jul 16 05:37:07 PM PDT 24
Peak memory	273552 kb
Host	smart-f7bf6929-b589-498a-a8fb-c2f7a79f88f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464169502 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_disable.1464169502
Directory	/workspace/31.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/31.flash_ctrl_hw_sec_otp.1288579112
Short name	T317
Test name
Test status
Simulation time	7984605000 ps
CPU time	132.96 seconds
Started	Jul 16 05:35:34 PM PDT 24
Finished	Jul 16 05:37:47 PM PDT 24
Peak memory	260896 kb
Host	smart-b1947f95-e5fe-456c-9fa5-18e59272bed3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288579112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_ hw_sec_otp.1288579112
Directory	/workspace/31.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd.3892911691
Short name	T1101
Test name
Test status
Simulation time	1501261500 ps
CPU time	139.79 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:39:10 PM PDT 24
Peak memory	291536 kb
Host	smart-6372906e-3065-4e04-8c00-96525fc47937
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892911691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla sh_ctrl_intr_rd.3892911691
Directory	/workspace/31.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.427424830
Short name	T107
Test name
Test status
Simulation time	12477462700 ps
CPU time	122.22 seconds
Started	Jul 16 05:35:42 PM PDT 24
Finished	Jul 16 05:37:45 PM PDT 24
Peak memory	292976 kb
Host	smart-40fea4d5-c222-491f-aa3f-907f927cbaea
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427424830 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.427424830
Directory	/workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/31.flash_ctrl_otp_reset.1690691667
Short name	T549
Test name
Test status
Simulation time	142924300 ps
CPU time	131.74 seconds
Started	Jul 16 05:37:21 PM PDT 24
Finished	Jul 16 05:39:34 PM PDT 24
Peak memory	260060 kb
Host	smart-cdc420c1-8524-44dd-a26e-58690f23c2eb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690691667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o tp_reset.1690691667
Directory	/workspace/31.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict.3960251745
Short name	T479
Test name
Test status
Simulation time	74751900 ps
CPU time	31.59 seconds
Started	Jul 16 05:35:43 PM PDT 24
Finished	Jul 16 05:36:15 PM PDT 24
Peak memory	268300 kb
Host	smart-ac7ace8c-8a5f-4d29-b7bf-ef3cfe209a1d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960251745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl ash_ctrl_rw_evict.3960251745
Directory	/workspace/31.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.146228180
Short name	T143
Test name
Test status
Simulation time	81867700 ps
CPU time	30.67 seconds
Started	Jul 16 05:35:43 PM PDT 24
Finished	Jul 16 05:36:14 PM PDT 24
Peak memory	268432 kb
Host	smart-be54b25f-0bd0-415e-a7fa-8fe2386d53c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146228180 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.146228180
Directory	/workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/31.flash_ctrl_sec_info_access.2272200426
Short name	T403
Test name
Test status
Simulation time	1527319300 ps
CPU time	56.25 seconds
Started	Jul 16 05:36:18 PM PDT 24
Finished	Jul 16 05:37:14 PM PDT 24
Peak memory	263624 kb
Host	smart-1ca881b8-e460-4a74-b86e-6eb20a0af1d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2272200426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2272200426
Directory	/workspace/31.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/31.flash_ctrl_smoke.1063793173
Short name	T594
Test name
Test status
Simulation time	41841300 ps
CPU time	168.7 seconds
Started	Jul 16 05:35:31 PM PDT 24
Finished	Jul 16 05:38:20 PM PDT 24
Peak memory	279492 kb
Host	smart-9ea85c88-1772-4567-9032-8641f2862ed3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063793173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1063793173
Directory	/workspace/31.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.flash_ctrl_alert_test.4229113732
Short name	T802
Test name
Test status
Simulation time	36584100 ps
CPU time	13.83 seconds
Started	Jul 16 05:35:41 PM PDT 24
Finished	Jul 16 05:35:56 PM PDT 24
Peak memory	258296 kb
Host	smart-5205b4e4-cb2f-4812-9ff3-939fd21156b4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229113732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test. 4229113732
Directory	/workspace/32.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.flash_ctrl_connect.2857152018
Short name	T621
Test name
Test status
Simulation time	50261900 ps
CPU time	16.3 seconds
Started	Jul 16 05:35:40 PM PDT 24
Finished	Jul 16 05:35:57 PM PDT 24
Peak memory	275108 kb
Host	smart-1dc44789-19a5-4b92-921a-c76f815e7635
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857152018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2857152018
Directory	/workspace/32.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/32.flash_ctrl_hw_sec_otp.2253349991
Short name	T855
Test name
Test status
Simulation time	1520702400 ps
CPU time	59.99 seconds
Started	Jul 16 05:36:48 PM PDT 24
Finished	Jul 16 05:37:49 PM PDT 24
Peak memory	260976 kb
Host	smart-5e8253c3-f369-45e5-953c-90bd2da10b19
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253349991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ hw_sec_otp.2253349991
Directory	/workspace/32.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd.2801477224
Short name	T506
Test name
Test status
Simulation time	3782950100 ps
CPU time	215.42 seconds
Started	Jul 16 05:38:11 PM PDT 24
Finished	Jul 16 05:41:47 PM PDT 24
Peak memory	291304 kb
Host	smart-34855ee3-59bf-46e0-a7b5-4542fb0d8e77
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801477224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla sh_ctrl_intr_rd.2801477224
Directory	/workspace/32.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.601831311
Short name	T1116
Test name
Test status
Simulation time	12093369100 ps
CPU time	251.45 seconds
Started	Jul 16 05:35:54 PM PDT 24
Finished	Jul 16 05:40:06 PM PDT 24
Peak memory	291924 kb
Host	smart-893f7ed0-e038-4d44-a8b3-b73b08814343
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601831311 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.601831311
Directory	/workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict.1549746993
Short name	T789
Test name
Test status
Simulation time	76917700 ps
CPU time	30.27 seconds
Started	Jul 16 05:35:41 PM PDT 24
Finished	Jul 16 05:36:12 PM PDT 24
Peak memory	275608 kb
Host	smart-86dc999d-7988-454e-b4ea-e21cc0305603
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549746993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl ash_ctrl_rw_evict.1549746993
Directory	/workspace/32.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.1671921355
Short name	T271
Test name
Test status
Simulation time	40738700 ps
CPU time	28.1 seconds
Started	Jul 16 05:35:41 PM PDT 24
Finished	Jul 16 05:36:10 PM PDT 24
Peak memory	275756 kb
Host	smart-2a08b43c-f3ca-40f2-8f6c-b40a3c71a4f5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671921355 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.1671921355
Directory	/workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/32.flash_ctrl_sec_info_access.3797440572
Short name	T872
Test name
Test status
Simulation time	2306741900 ps
CPU time	67.15 seconds
Started	Jul 16 05:35:41 PM PDT 24
Finished	Jul 16 05:36:49 PM PDT 24
Peak memory	263276 kb
Host	smart-db578c92-09c9-45f7-816c-fcf445995252
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797440572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3797440572
Directory	/workspace/32.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/32.flash_ctrl_smoke.3064874553
Short name	T459
Test name
Test status
Simulation time	79194700 ps
CPU time	95.31 seconds
Started	Jul 16 05:35:40 PM PDT 24
Finished	Jul 16 05:37:15 PM PDT 24
Peak memory	277464 kb
Host	smart-ef780673-66e5-45be-aaea-ea6bd12ef061
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064874553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.3064874553
Directory	/workspace/32.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.flash_ctrl_alert_test.3081763925
Short name	T499
Test name
Test status
Simulation time	45981400 ps
CPU time	13.46 seconds
Started	Jul 16 05:35:50 PM PDT 24
Finished	Jul 16 05:36:04 PM PDT 24
Peak memory	258320 kb
Host	smart-60f7cf7a-0f6d-4033-ab95-c01b9e9e8111
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081763925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test. 3081763925
Directory	/workspace/33.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.flash_ctrl_connect.477852520
Short name	T629
Test name
Test status
Simulation time	16775600 ps
CPU time	13.62 seconds
Started	Jul 16 05:36:09 PM PDT 24
Finished	Jul 16 05:36:23 PM PDT 24
Peak memory	284340 kb
Host	smart-73a8d149-7bea-422c-8e57-d8be5a8497f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=477852520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.477852520
Directory	/workspace/33.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/33.flash_ctrl_disable.1831633158
Short name	T394
Test name
Test status
Simulation time	29472500 ps
CPU time	21.4 seconds
Started	Jul 16 05:35:56 PM PDT 24
Finished	Jul 16 05:36:18 PM PDT 24
Peak memory	273488 kb
Host	smart-2a36cc6d-a8e0-4b4d-a579-243c5424a327
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831633158 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_disable.1831633158
Directory	/workspace/33.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.2937420097
Short name	T645
Test name
Test status
Simulation time	1255713900 ps
CPU time	46.64 seconds
Started	Jul 16 05:35:54 PM PDT 24
Finished	Jul 16 05:36:41 PM PDT 24
Peak memory	260880 kb
Host	smart-05e75b6b-a0b3-4791-b10c-8271eea6f689
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937420097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ hw_sec_otp.2937420097
Directory	/workspace/33.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd.2040503189
Short name	T361
Test name
Test status
Simulation time	538035900 ps
CPU time	126.96 seconds
Started	Jul 16 05:36:22 PM PDT 24
Finished	Jul 16 05:38:30 PM PDT 24
Peak memory	290908 kb
Host	smart-e6299f17-ca7c-4693-a0a5-35105ddebabf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040503189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla sh_ctrl_intr_rd.2040503189
Directory	/workspace/33.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1310420732
Short name	T781
Test name
Test status
Simulation time	24427463100 ps
CPU time	309.61 seconds
Started	Jul 16 05:35:43 PM PDT 24
Finished	Jul 16 05:40:53 PM PDT 24
Peak memory	291580 kb
Host	smart-431d0630-68b7-490b-9c54-70fcc1389cc0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310420732 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.1310420732
Directory	/workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/33.flash_ctrl_otp_reset.2980708210
Short name	T170
Test name
Test status
Simulation time	39855500 ps
CPU time	132.74 seconds
Started	Jul 16 05:35:40 PM PDT 24
Finished	Jul 16 05:37:53 PM PDT 24
Peak memory	259940 kb
Host	smart-d051fb37-562f-414e-a050-23afc8eac327
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980708210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o tp_reset.2980708210
Directory	/workspace/33.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict.3206019730
Short name	T966
Test name
Test status
Simulation time	51560600 ps
CPU time	30.26 seconds
Started	Jul 16 05:35:54 PM PDT 24
Finished	Jul 16 05:36:24 PM PDT 24
Peak memory	275544 kb
Host	smart-7a48ddee-f96f-4398-8e29-8d3396d414a2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206019730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl ash_ctrl_rw_evict.3206019730
Directory	/workspace/33.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.2375598702
Short name	T946
Test name
Test status
Simulation time	31210900 ps
CPU time	28.38 seconds
Started	Jul 16 05:35:51 PM PDT 24
Finished	Jul 16 05:36:20 PM PDT 24
Peak memory	273516 kb
Host	smart-9c8030a8-9a42-49e0-8188-a2ff8db41ff4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375598702 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.2375598702
Directory	/workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/33.flash_ctrl_sec_info_access.755676019
Short name	T1076
Test name
Test status
Simulation time	1353951600 ps
CPU time	67.19 seconds
Started	Jul 16 05:36:48 PM PDT 24
Finished	Jul 16 05:37:56 PM PDT 24
Peak memory	263668 kb
Host	smart-e147a1b2-2548-4f37-954a-b49f1fbf3dc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755676019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.755676019
Directory	/workspace/33.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/33.flash_ctrl_smoke.2830597912
Short name	T322
Test name
Test status
Simulation time	180480600 ps
CPU time	122.1 seconds
Started	Jul 16 05:35:42 PM PDT 24
Finished	Jul 16 05:37:45 PM PDT 24
Peak memory	276352 kb
Host	smart-b0ec2081-17c3-4caf-a342-406069a9f3e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830597912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.2830597912
Directory	/workspace/33.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.flash_ctrl_alert_test.1404257752
Short name	T88
Test name
Test status
Simulation time	26209000 ps
CPU time	13.56 seconds
Started	Jul 16 05:35:50 PM PDT 24
Finished	Jul 16 05:36:04 PM PDT 24
Peak memory	265336 kb
Host	smart-8139d114-1290-4072-8519-e2c742fc9c97
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404257752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test. 1404257752
Directory	/workspace/34.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.flash_ctrl_connect.2734536042
Short name	T103
Test name
Test status
Simulation time	14216400 ps
CPU time	15.79 seconds
Started	Jul 16 05:35:52 PM PDT 24
Finished	Jul 16 05:36:08 PM PDT 24
Peak memory	274784 kb
Host	smart-0e150938-6991-45d2-938b-efb1afd45a69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734536042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.2734536042
Directory	/workspace/34.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/34.flash_ctrl_disable.3312158137
Short name	T768
Test name
Test status
Simulation time	41575800 ps
CPU time	20.47 seconds
Started	Jul 16 05:35:53 PM PDT 24
Finished	Jul 16 05:36:14 PM PDT 24
Peak memory	265648 kb
Host	smart-47f8d195-7a21-4695-9e47-4fdd35d9c779
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312158137 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_disable.3312158137
Directory	/workspace/34.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.569056539
Short name	T318
Test name
Test status
Simulation time	3999924100 ps
CPU time	55.57 seconds
Started	Jul 16 05:35:56 PM PDT 24
Finished	Jul 16 05:36:52 PM PDT 24
Peak memory	260808 kb
Host	smart-010a483b-c0ae-4784-99df-bb9804d94299
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569056539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_h w_sec_otp.569056539
Directory	/workspace/34.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd.289177902
Short name	T567
Test name
Test status
Simulation time	3679683200 ps
CPU time	235.53 seconds
Started	Jul 16 05:35:48 PM PDT 24
Finished	Jul 16 05:39:44 PM PDT 24
Peak memory	291528 kb
Host	smart-32761f3b-50cd-4f12-9f11-be65b55e16e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289177902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flas h_ctrl_intr_rd.289177902
Directory	/workspace/34.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3852841806
Short name	T969
Test name
Test status
Simulation time	23389551700 ps
CPU time	305.17 seconds
Started	Jul 16 05:35:53 PM PDT 24
Finished	Jul 16 05:40:59 PM PDT 24
Peak memory	292076 kb
Host	smart-07db3d05-4cef-439a-ae25-e140f32e5c06
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852841806 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.3852841806
Directory	/workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/34.flash_ctrl_otp_reset.2874619864
Short name	T537
Test name
Test status
Simulation time	444314000 ps
CPU time	132.8 seconds
Started	Jul 16 05:35:49 PM PDT 24
Finished	Jul 16 05:38:02 PM PDT 24
Peak memory	260216 kb
Host	smart-743b882c-330a-4644-b96d-53b082c8a33a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874619864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o tp_reset.2874619864
Directory	/workspace/34.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict.1719335810
Short name	T452
Test name
Test status
Simulation time	46219200 ps
CPU time	30.71 seconds
Started	Jul 16 05:35:49 PM PDT 24
Finished	Jul 16 05:36:20 PM PDT 24
Peak memory	275492 kb
Host	smart-b9b37530-ba7b-4baf-9a87-7b49408029b1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719335810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl ash_ctrl_rw_evict.1719335810
Directory	/workspace/34.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2217106042
Short name	T1095
Test name
Test status
Simulation time	33024500 ps
CPU time	31.03 seconds
Started	Jul 16 05:37:00 PM PDT 24
Finished	Jul 16 05:37:33 PM PDT 24
Peak memory	268388 kb
Host	smart-56c89424-cc68-4137-87f9-c9e960ba2391
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217106042 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2217106042
Directory	/workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/34.flash_ctrl_sec_info_access.3092575291
Short name	T404
Test name
Test status
Simulation time	715061900 ps
CPU time	70.17 seconds
Started	Jul 16 05:36:32 PM PDT 24
Finished	Jul 16 05:37:42 PM PDT 24
Peak memory	263624 kb
Host	smart-2dc7e1ce-15f7-4583-acf4-9f5c05e947b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3092575291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3092575291
Directory	/workspace/34.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/34.flash_ctrl_smoke.3408245321
Short name	T386
Test name
Test status
Simulation time	79761100 ps
CPU time	75.33 seconds
Started	Jul 16 05:35:50 PM PDT 24
Finished	Jul 16 05:37:06 PM PDT 24
Peak memory	275684 kb
Host	smart-6a80b12b-bc3b-4a8f-ad1d-af3dd61cf79a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408245321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.3408245321
Directory	/workspace/34.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.flash_ctrl_alert_test.4159830349
Short name	T889
Test name
Test status
Simulation time	139038000 ps
CPU time	13.86 seconds
Started	Jul 16 05:36:00 PM PDT 24
Finished	Jul 16 05:36:14 PM PDT 24
Peak memory	258332 kb
Host	smart-b330f2c1-b5f5-4075-b552-bbac600ae7e4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159830349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test. 4159830349
Directory	/workspace/35.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.flash_ctrl_connect.854456735
Short name	T718
Test name
Test status
Simulation time	14861500 ps
CPU time	16.2 seconds
Started	Jul 16 05:35:59 PM PDT 24
Finished	Jul 16 05:36:16 PM PDT 24
Peak memory	274752 kb
Host	smart-fe6d2691-2195-496d-82d7-1e63b9372a99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854456735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.854456735
Directory	/workspace/35.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/35.flash_ctrl_disable.2239091590
Short name	T702
Test name
Test status
Simulation time	117765300 ps
CPU time	21.47 seconds
Started	Jul 16 05:36:05 PM PDT 24
Finished	Jul 16 05:36:26 PM PDT 24
Peak memory	265540 kb
Host	smart-2d3bb972-eb91-491a-b07e-d32e4ef626ec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239091590 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_disable.2239091590
Directory	/workspace/35.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3030755920
Short name	T531
Test name
Test status
Simulation time	10686597700 ps
CPU time	208.49 seconds
Started	Jul 16 05:35:52 PM PDT 24
Finished	Jul 16 05:39:21 PM PDT 24
Peak memory	263328 kb
Host	smart-4b39565f-54c6-470a-8c7f-e425f0257f00
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030755920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ hw_sec_otp.3030755920
Directory	/workspace/35.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd.2847147188
Short name	T914
Test name
Test status
Simulation time	687586800 ps
CPU time	172.6 seconds
Started	Jul 16 05:35:59 PM PDT 24
Finished	Jul 16 05:38:52 PM PDT 24
Peak memory	291532 kb
Host	smart-63cf4893-7ea9-4465-b604-a228ad50abf3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847147188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla sh_ctrl_intr_rd.2847147188
Directory	/workspace/35.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.2082172434
Short name	T577
Test name
Test status
Simulation time	8714877400 ps
CPU time	195.72 seconds
Started	Jul 16 05:35:58 PM PDT 24
Finished	Jul 16 05:39:14 PM PDT 24
Peak memory	285064 kb
Host	smart-f5fd3d7b-6717-4a1c-90fc-1466939d8826
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082172434 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.2082172434
Directory	/workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/35.flash_ctrl_otp_reset.2843359376
Short name	T311
Test name
Test status
Simulation time	160286200 ps
CPU time	113.37 seconds
Started	Jul 16 05:35:59 PM PDT 24
Finished	Jul 16 05:37:53 PM PDT 24
Peak memory	260156 kb
Host	smart-e02dd7a4-705c-4c78-83c7-7be0e576b9d2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843359376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o tp_reset.2843359376
Directory	/workspace/35.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict.443817014
Short name	T144
Test name
Test status
Simulation time	54934200 ps
CPU time	28.99 seconds
Started	Jul 16 05:36:00 PM PDT 24
Finished	Jul 16 05:36:30 PM PDT 24
Peak memory	275632 kb
Host	smart-a7c9592b-0816-45fa-b83f-6a54f59edaa3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443817014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla sh_ctrl_rw_evict.443817014
Directory	/workspace/35.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.492975266
Short name	T205
Test name
Test status
Simulation time	41308000 ps
CPU time	30.13 seconds
Started	Jul 16 05:36:03 PM PDT 24
Finished	Jul 16 05:36:33 PM PDT 24
Peak memory	275708 kb
Host	smart-a8d9a5cc-dc7a-4b9a-a62b-44d34b59474e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492975266 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.492975266
Directory	/workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/35.flash_ctrl_sec_info_access.3129994733
Short name	T402
Test name
Test status
Simulation time	2011940600 ps
CPU time	62.79 seconds
Started	Jul 16 05:36:00 PM PDT 24
Finished	Jul 16 05:37:03 PM PDT 24
Peak memory	264780 kb
Host	smart-c70fa524-9ba2-459c-a037-89ab8089e071
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3129994733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.3129994733
Directory	/workspace/35.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/35.flash_ctrl_smoke.3836667171
Short name	T694
Test name
Test status
Simulation time	22460900 ps
CPU time	119.34 seconds
Started	Jul 16 05:35:56 PM PDT 24
Finished	Jul 16 05:37:56 PM PDT 24
Peak memory	277476 kb
Host	smart-371d2b6c-2aa5-4fc5-8d40-c0499928178d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3836667171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.3836667171
Directory	/workspace/35.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.flash_ctrl_alert_test.151530805
Short name	T125
Test name
Test status
Simulation time	104022800 ps
CPU time	13.57 seconds
Started	Jul 16 05:36:17 PM PDT 24
Finished	Jul 16 05:36:31 PM PDT 24
Peak memory	258224 kb
Host	smart-099c3df2-bb06-48e8-af96-44871d2458e8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151530805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.151530805
Directory	/workspace/36.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.flash_ctrl_connect.3214163911
Short name	T587
Test name
Test status
Simulation time	27582800 ps
CPU time	13.5 seconds
Started	Jul 16 05:36:11 PM PDT 24
Finished	Jul 16 05:36:25 PM PDT 24
Peak memory	274904 kb
Host	smart-30cd6600-353d-4ac5-8b56-fe8f81e59553
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3214163911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3214163911
Directory	/workspace/36.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/36.flash_ctrl_disable.3512675404
Short name	T947
Test name
Test status
Simulation time	14623600 ps
CPU time	22.31 seconds
Started	Jul 16 05:36:00 PM PDT 24
Finished	Jul 16 05:36:23 PM PDT 24
Peak memory	273652 kb
Host	smart-e335b55f-66c9-4f67-bf77-9ab8e1393404
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512675404 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_disable.3512675404
Directory	/workspace/36.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd.3075615801
Short name	T202
Test name
Test status
Simulation time	1820382500 ps
CPU time	114.85 seconds
Started	Jul 16 05:36:16 PM PDT 24
Finished	Jul 16 05:38:11 PM PDT 24
Peak memory	293784 kb
Host	smart-3c94e173-ca0c-45d8-9023-1efe7337b640
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075615801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla sh_ctrl_intr_rd.3075615801
Directory	/workspace/36.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.475409424
Short name	T335
Test name
Test status
Simulation time	51496818700 ps
CPU time	314.94 seconds
Started	Jul 16 05:35:58 PM PDT 24
Finished	Jul 16 05:41:14 PM PDT 24
Peak memory	284876 kb
Host	smart-0d121808-538e-4c75-ba28-2ad48096745d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475409424 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.475409424
Directory	/workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/36.flash_ctrl_otp_reset.1648997655
Short name	T962
Test name
Test status
Simulation time	40518200 ps
CPU time	133.08 seconds
Started	Jul 16 05:36:00 PM PDT 24
Finished	Jul 16 05:38:13 PM PDT 24
Peak memory	264608 kb
Host	smart-ed695416-bae4-414d-bff4-790e0572eda5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648997655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o tp_reset.1648997655
Directory	/workspace/36.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict.2351954030
Short name	T348
Test name
Test status
Simulation time	38576500 ps
CPU time	31.26 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:37:26 PM PDT 24
Peak memory	268460 kb
Host	smart-b7f772fe-9d18-42f6-ae2e-3751c6c2f168
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351954030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl ash_ctrl_rw_evict.2351954030
Directory	/workspace/36.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.2763302692
Short name	T356
Test name
Test status
Simulation time	40522300 ps
CPU time	30.43 seconds
Started	Jul 16 05:36:05 PM PDT 24
Finished	Jul 16 05:36:35 PM PDT 24
Peak memory	275668 kb
Host	smart-4d852791-fea9-42db-be1e-e8c08892148b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763302692 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.2763302692
Directory	/workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/36.flash_ctrl_sec_info_access.2625899811
Short name	T411
Test name
Test status
Simulation time	11660415200 ps
CPU time	79.41 seconds
Started	Jul 16 05:36:11 PM PDT 24
Finished	Jul 16 05:37:31 PM PDT 24
Peak memory	263076 kb
Host	smart-b59ad056-1509-4aa1-93be-f9cf427f96c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625899811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2625899811
Directory	/workspace/36.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/36.flash_ctrl_smoke.2534444400
Short name	T429
Test name
Test status
Simulation time	22740300 ps
CPU time	76.31 seconds
Started	Jul 16 05:35:59 PM PDT 24
Finished	Jul 16 05:37:16 PM PDT 24
Peak memory	275516 kb
Host	smart-1b4d8e67-14ad-46d6-8588-2005bff0b69a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534444400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2534444400
Directory	/workspace/36.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.flash_ctrl_alert_test.1932303516
Short name	T933
Test name
Test status
Simulation time	75305100 ps
CPU time	13.74 seconds
Started	Jul 16 05:36:12 PM PDT 24
Finished	Jul 16 05:36:26 PM PDT 24
Peak memory	265132 kb
Host	smart-bbcbe778-6ee3-4347-ad99-1e32cedc90cf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932303516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test. 1932303516
Directory	/workspace/37.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.flash_ctrl_connect.1143635441
Short name	T941
Test name
Test status
Simulation time	18216500 ps
CPU time	15.99 seconds
Started	Jul 16 05:36:10 PM PDT 24
Finished	Jul 16 05:36:27 PM PDT 24
Peak memory	274892 kb
Host	smart-27ed2abf-2e7c-4ccd-bd6d-1d21168c6cfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143635441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1143635441
Directory	/workspace/37.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/37.flash_ctrl_disable.2841239980
Short name	T607
Test name
Test status
Simulation time	17240700 ps
CPU time	22.14 seconds
Started	Jul 16 05:36:13 PM PDT 24
Finished	Jul 16 05:36:36 PM PDT 24
Peak memory	273488 kb
Host	smart-78d239bd-4881-4ae5-b020-ce0b2447b6d8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841239980 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_disable.2841239980
Directory	/workspace/37.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/37.flash_ctrl_hw_sec_otp.297393977
Short name	T604
Test name
Test status
Simulation time	7690481500 ps
CPU time	108.47 seconds
Started	Jul 16 05:36:11 PM PDT 24
Finished	Jul 16 05:38:00 PM PDT 24
Peak memory	262696 kb
Host	smart-c32a8467-10f9-466b-8894-2970df5f029b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297393977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_h w_sec_otp.297393977
Directory	/workspace/37.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd.3277252175
Short name	T807
Test name
Test status
Simulation time	1449771900 ps
CPU time	139.74 seconds
Started	Jul 16 05:36:09 PM PDT 24
Finished	Jul 16 05:38:29 PM PDT 24
Peak memory	294716 kb
Host	smart-b6dbb79d-2b71-4758-a94a-9d44f76a1126
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277252175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla sh_ctrl_intr_rd.3277252175
Directory	/workspace/37.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.969946395
Short name	T337
Test name
Test status
Simulation time	61504781000 ps
CPU time	287.69 seconds
Started	Jul 16 05:36:16 PM PDT 24
Finished	Jul 16 05:41:05 PM PDT 24
Peak memory	284760 kb
Host	smart-93a42dba-f797-4ee7-a1e5-c31e328e45cd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969946395 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.969946395
Directory	/workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/37.flash_ctrl_otp_reset.3637499204
Short name	T725
Test name
Test status
Simulation time	154563700 ps
CPU time	109.95 seconds
Started	Jul 16 05:36:13 PM PDT 24
Finished	Jul 16 05:38:03 PM PDT 24
Peak memory	260384 kb
Host	smart-8d992d91-375e-4a5c-b70a-3742ee47a2de
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637499204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o tp_reset.3637499204
Directory	/workspace/37.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict.3210380457
Short name	T36
Test name
Test status
Simulation time	86433300 ps
CPU time	28.16 seconds
Started	Jul 16 05:36:17 PM PDT 24
Finished	Jul 16 05:36:45 PM PDT 24
Peak memory	275620 kb
Host	smart-6bff8206-29c3-48c4-92d3-e445ee59a1b2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210380457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl ash_ctrl_rw_evict.3210380457
Directory	/workspace/37.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3402022219
Short name	T281
Test name
Test status
Simulation time	63350100 ps
CPU time	31.27 seconds
Started	Jul 16 05:36:13 PM PDT 24
Finished	Jul 16 05:36:45 PM PDT 24
Peak memory	268548 kb
Host	smart-247025b6-9bd4-4c21-8078-8a0102ae7d0d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402022219 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3402022219
Directory	/workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/37.flash_ctrl_sec_info_access.1197707209
Short name	T595
Test name
Test status
Simulation time	1539973800 ps
CPU time	67.27 seconds
Started	Jul 16 05:36:17 PM PDT 24
Finished	Jul 16 05:37:25 PM PDT 24
Peak memory	264072 kb
Host	smart-a8d5ee01-c933-4e18-8e8a-6b69b5899a44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1197707209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.1197707209
Directory	/workspace/37.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/37.flash_ctrl_smoke.904709836
Short name	T596
Test name
Test status
Simulation time	71416000 ps
CPU time	146.23 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:39:21 PM PDT 24
Peak memory	277120 kb
Host	smart-b2bd9ca7-5d09-4094-adcc-4599cb79b1b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=904709836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.904709836
Directory	/workspace/37.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.flash_ctrl_alert_test.3035715643
Short name	T1044
Test name
Test status
Simulation time	31085900 ps
CPU time	13.45 seconds
Started	Jul 16 05:36:24 PM PDT 24
Finished	Jul 16 05:36:38 PM PDT 24
Peak memory	258192 kb
Host	smart-c1d17264-fbb4-4f8a-b5ee-a5e002f70d42
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035715643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test. 3035715643
Directory	/workspace/38.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.flash_ctrl_connect.3257201033
Short name	T753
Test name
Test status
Simulation time	24265900 ps
CPU time	13.86 seconds
Started	Jul 16 05:36:21 PM PDT 24
Finished	Jul 16 05:36:36 PM PDT 24
Peak memory	284172 kb
Host	smart-c2db7423-f5bb-4e69-ab7d-26ff62bb8aa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257201033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3257201033
Directory	/workspace/38.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/38.flash_ctrl_disable.863845547
Short name	T380
Test name
Test status
Simulation time	17109000 ps
CPU time	21.56 seconds
Started	Jul 16 05:36:25 PM PDT 24
Finished	Jul 16 05:36:47 PM PDT 24
Peak memory	273488 kb
Host	smart-c0dc5e07-7f60-4a5c-883a-19b9a3e3d3c8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863845547 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_disable.863845547
Directory	/workspace/38.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.4279778127
Short name	T1098
Test name
Test status
Simulation time	4518146200 ps
CPU time	130.7 seconds
Started	Jul 16 05:36:12 PM PDT 24
Finished	Jul 16 05:38:23 PM PDT 24
Peak memory	260712 kb
Host	smart-c150525d-fc06-4abc-bdb9-59ef8473987a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279778127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ hw_sec_otp.4279778127
Directory	/workspace/38.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.3954342728
Short name	T717
Test name
Test status
Simulation time	25320843000 ps
CPU time	282.08 seconds
Started	Jul 16 05:36:22 PM PDT 24
Finished	Jul 16 05:41:05 PM PDT 24
Peak memory	289832 kb
Host	smart-d5e218df-f447-4121-879c-06b392ead404
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954342728 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.3954342728
Directory	/workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/38.flash_ctrl_otp_reset.4055479035
Short name	T970
Test name
Test status
Simulation time	88864000 ps
CPU time	134.12 seconds
Started	Jul 16 05:36:17 PM PDT 24
Finished	Jul 16 05:38:32 PM PDT 24
Peak memory	265096 kb
Host	smart-2f407388-01ca-4af5-88b9-da4e9e568c6a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055479035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o tp_reset.4055479035
Directory	/workspace/38.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict.580957896
Short name	T276
Test name
Test status
Simulation time	138900600 ps
CPU time	31.12 seconds
Started	Jul 16 05:36:23 PM PDT 24
Finished	Jul 16 05:36:55 PM PDT 24
Peak memory	275636 kb
Host	smart-a3760e01-e344-480f-b64a-9071fce1b864
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580957896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla sh_ctrl_rw_evict.580957896
Directory	/workspace/38.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.1595403634
Short name	T358
Test name
Test status
Simulation time	41449600 ps
CPU time	30.92 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:37:34 PM PDT 24
Peak memory	275608 kb
Host	smart-bc6df52e-f6c8-4e0d-9ad5-22e460f3fa4b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595403634 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.1595403634
Directory	/workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/38.flash_ctrl_sec_info_access.2613491188
Short name	T907
Test name
Test status
Simulation time	951241200 ps
CPU time	69.07 seconds
Started	Jul 16 05:36:49 PM PDT 24
Finished	Jul 16 05:37:59 PM PDT 24
Peak memory	263628 kb
Host	smart-9031556f-e3af-4f24-aa36-d0ac86f58d1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2613491188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2613491188
Directory	/workspace/38.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/38.flash_ctrl_smoke.1616292582
Short name	T683
Test name
Test status
Simulation time	34640700 ps
CPU time	220.1 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:40:30 PM PDT 24
Peak memory	281492 kb
Host	smart-3eae4a2b-3b0a-4348-93ee-59aad83e4eb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616292582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.1616292582
Directory	/workspace/38.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.flash_ctrl_alert_test.3073749766
Short name	T626
Test name
Test status
Simulation time	112070000 ps
CPU time	13.61 seconds
Started	Jul 16 05:36:24 PM PDT 24
Finished	Jul 16 05:36:38 PM PDT 24
Peak memory	258188 kb
Host	smart-75818c8e-1a72-4e2f-8a79-8563a04e6230
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073749766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test. 3073749766
Directory	/workspace/39.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.flash_ctrl_connect.2889387813
Short name	T566
Test name
Test status
Simulation time	146659400 ps
CPU time	16.23 seconds
Started	Jul 16 05:36:21 PM PDT 24
Finished	Jul 16 05:36:38 PM PDT 24
Peak memory	284312 kb
Host	smart-0e7a8aa8-3796-4b87-933c-91f8eb9acd9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889387813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2889387813
Directory	/workspace/39.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/39.flash_ctrl_disable.369365341
Short name	T173
Test name
Test status
Simulation time	26301600 ps
CPU time	22.55 seconds
Started	Jul 16 05:36:44 PM PDT 24
Finished	Jul 16 05:37:07 PM PDT 24
Peak memory	273548 kb
Host	smart-56311361-089b-49df-a659-73c1461d086a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369365341 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_disable.369365341
Directory	/workspace/39.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.2230366735
Short name	T109
Test name
Test status
Simulation time	42097781700 ps
CPU time	113.11 seconds
Started	Jul 16 05:36:25 PM PDT 24
Finished	Jul 16 05:38:18 PM PDT 24
Peak memory	263240 kb
Host	smart-24d98765-04ba-45f9-9664-99153f598f30
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230366735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_ hw_sec_otp.2230366735
Directory	/workspace/39.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd.1606076431
Short name	T454
Test name
Test status
Simulation time	2517642600 ps
CPU time	133.34 seconds
Started	Jul 16 05:36:23 PM PDT 24
Finished	Jul 16 05:38:37 PM PDT 24
Peak memory	294020 kb
Host	smart-aee0ee6a-016b-4da1-b0f8-0956f9e9f4a4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606076431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla sh_ctrl_intr_rd.1606076431
Directory	/workspace/39.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1150259937
Short name	T509
Test name
Test status
Simulation time	11862212200 ps
CPU time	138.74 seconds
Started	Jul 16 05:36:20 PM PDT 24
Finished	Jul 16 05:38:39 PM PDT 24
Peak memory	292988 kb
Host	smart-4fec30fe-7b2c-4591-84a2-1492e8c2a6ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150259937 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.1150259937
Directory	/workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/39.flash_ctrl_otp_reset.536240394
Short name	T579
Test name
Test status
Simulation time	360255000 ps
CPU time	131.16 seconds
Started	Jul 16 05:46:07 PM PDT 24
Finished	Jul 16 05:48:19 PM PDT 24
Peak memory	260996 kb
Host	smart-c89b3469-68c2-4985-a450-27dc6af4e183
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536240394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_ot p_reset.536240394
Directory	/workspace/39.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict.2025277051
Short name	T474
Test name
Test status
Simulation time	27982800 ps
CPU time	29.07 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:37:19 PM PDT 24
Peak memory	268448 kb
Host	smart-abbdd663-a28d-4d08-be2d-08b731bd80e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025277051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl ash_ctrl_rw_evict.2025277051
Directory	/workspace/39.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.1815418502
Short name	T1091
Test name
Test status
Simulation time	43586300 ps
CPU time	30.97 seconds
Started	Jul 16 05:36:23 PM PDT 24
Finished	Jul 16 05:36:55 PM PDT 24
Peak memory	275664 kb
Host	smart-b1eee967-8188-4674-be3a-fec506be7eeb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815418502 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.1815418502
Directory	/workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/39.flash_ctrl_sec_info_access.1136818569
Short name	T408
Test name
Test status
Simulation time	2390679300 ps
CPU time	54.72 seconds
Started	Jul 16 05:36:22 PM PDT 24
Finished	Jul 16 05:37:18 PM PDT 24
Peak memory	263724 kb
Host	smart-7328205e-342c-496d-aeaa-8907247832b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136818569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1136818569
Directory	/workspace/39.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/39.flash_ctrl_smoke.2536707603
Short name	T436
Test name
Test status
Simulation time	44986400 ps
CPU time	147.2 seconds
Started	Jul 16 05:36:23 PM PDT 24
Finished	Jul 16 05:38:51 PM PDT 24
Peak memory	278132 kb
Host	smart-e38cc10d-099c-4c57-858c-3d25b2f37b20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2536707603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.2536707603
Directory	/workspace/39.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_alert_test.66049752
Short name	T466
Test name
Test status
Simulation time	54444500 ps
CPU time	13.32 seconds
Started	Jul 16 05:31:25 PM PDT 24
Finished	Jul 16 05:31:40 PM PDT 24
Peak memory	264432 kb
Host	smart-fc014cf0-924f-48ae-85dc-365c0b4529b6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66049752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.66049752
Directory	/workspace/4.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.flash_ctrl_config_regwen.2638580996
Short name	T249
Test name
Test status
Simulation time	19573800 ps
CPU time	13.74 seconds
Started	Jul 16 05:31:25 PM PDT 24
Finished	Jul 16 05:31:40 PM PDT 24
Peak memory	261044 kb
Host	smart-6c95ee95-122c-4972-92a1-34b3c8aad4a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638580996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .flash_ctrl_config_regwen.2638580996
Directory	/workspace/4.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/4.flash_ctrl_connect.905436706
Short name	T652
Test name
Test status
Simulation time	52745900 ps
CPU time	15.82 seconds
Started	Jul 16 05:35:30 PM PDT 24
Finished	Jul 16 05:35:46 PM PDT 24
Peak memory	284416 kb
Host	smart-dfd5d849-9a62-4c2e-acd6-f16e3203ed46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=905436706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.905436706
Directory	/workspace/4.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/4.flash_ctrl_disable.2732772399
Short name	T1061
Test name
Test status
Simulation time	34706300 ps
CPU time	20.45 seconds
Started	Jul 16 05:31:18 PM PDT 24
Finished	Jul 16 05:31:40 PM PDT 24
Peak memory	273560 kb
Host	smart-ba304ffa-467c-4d5d-85d7-5302da529b5f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732772399 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_disable.2732772399
Directory	/workspace/4.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/4.flash_ctrl_erase_suspend.2106192733
Short name	T185
Test name
Test status
Simulation time	5795860800 ps
CPU time	351.22 seconds
Started	Jul 16 05:35:52 PM PDT 24
Finished	Jul 16 05:41:44 PM PDT 24
Peak memory	263512 kb
Host	smart-f181d85c-2b6b-4b7c-a1e6-bf0751aff997
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2106192733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2106192733
Directory	/workspace/4.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_mp.3654648996
Short name	T728
Test name
Test status
Simulation time	3996158800 ps
CPU time	2154.38 seconds
Started	Jul 16 05:30:58 PM PDT 24
Finished	Jul 16 06:06:53 PM PDT 24
Peak memory	262876 kb
Host	smart-bbff974f-3850-44ef-8a97-73de9aa8cfd5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3654648996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.3654648996
Directory	/workspace/4.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_type.2710065109
Short name	T80
Test name
Test status
Simulation time	698271800 ps
CPU time	2413.39 seconds
Started	Jul 16 05:30:58 PM PDT 24
Finished	Jul 16 06:11:12 PM PDT 24
Peak memory	264264 kb
Host	smart-58015b2c-3cc9-47d9-9306-476744a4e9f2
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710065109 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.2710065109
Directory	/workspace/4.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_win.707203178
Short name	T1081
Test name
Test status
Simulation time	1643583400 ps
CPU time	922.19 seconds
Started	Jul 16 05:30:54 PM PDT 24
Finished	Jul 16 05:46:17 PM PDT 24
Peak memory	273504 kb
Host	smart-d688ad7b-34d1-4e51-95c6-cd88121e1142
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707203178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.707203178
Directory	/workspace/4.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fetch_code.2520838752
Short name	T47
Test name
Test status
Simulation time	645337600 ps
CPU time	26.24 seconds
Started	Jul 16 05:30:53 PM PDT 24
Finished	Jul 16 05:31:20 PM PDT 24
Peak memory	263740 kb
Host	smart-a377a860-d41b-45e7-878b-9ce65ae5702a
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520838752 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.2520838752
Directory	/workspace/4.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fs_sup.3089494895
Short name	T843
Test name
Test status
Simulation time	1312681300 ps
CPU time	43.27 seconds
Started	Jul 16 05:31:26 PM PDT 24
Finished	Jul 16 05:32:10 PM PDT 24
Peak memory	264992 kb
Host	smart-ab132ce0-0ccd-493b-a169-881066f6bb17
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089494895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 4.flash_ctrl_fs_sup.3089494895
Directory	/workspace/4.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/4.flash_ctrl_full_mem_access.3581760896
Short name	T120
Test name
Test status
Simulation time	382197184400 ps
CPU time	2652.81 seconds
Started	Jul 16 05:31:02 PM PDT 24
Finished	Jul 16 06:15:15 PM PDT 24
Peak memory	265024 kb
Host	smart-439aa99b-1d3f-4ec1-af79-d9b1e7b1932c
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581760896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c trl_full_mem_access.3581760896
Directory	/workspace/4.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.751545498
Short name	T1108
Test name
Test status
Simulation time	344857620500 ps
CPU time	2053.69 seconds
Started	Jul 16 05:35:52 PM PDT 24
Finished	Jul 16 06:10:06 PM PDT 24
Peak memory	264092 kb
Host	smart-fea34976-2656-4376-b154-a0d998ab2c34
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751545498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.flash_ctrl_host_ctrl_arb.751545498
Directory	/workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_dir_rd.118988107
Short name	T1085
Test name
Test status
Simulation time	114900700 ps
CPU time	37.14 seconds
Started	Jul 16 05:30:57 PM PDT 24
Finished	Jul 16 05:31:34 PM PDT 24
Peak memory	265188 kb
Host	smart-ee66d258-222b-43a9-9aae-c74d8681ea73
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=118988107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.118988107
Directory	/workspace/4.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3380062205
Short name	T284
Test name
Test status
Simulation time	10018964300 ps
CPU time	83.49 seconds
Started	Jul 16 05:36:17 PM PDT 24
Finished	Jul 16 05:37:41 PM PDT 24
Peak memory	293172 kb
Host	smart-2223dd89-c8de-4e62-af3c-2e4b0390f486
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380062205 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.3380062205
Directory	/workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3470811224
Short name	T979
Test name
Test status
Simulation time	26249000 ps
CPU time	13.13 seconds
Started	Jul 16 05:36:18 PM PDT 24
Finished	Jul 16 05:36:31 PM PDT 24
Peak memory	264996 kb
Host	smart-3323bea0-c176-45f4-a5b0-af8ff86aa9e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470811224 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3470811224
Directory	/workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_rma_reset.3660228660
Short name	T672
Test name
Test status
Simulation time	40121277300 ps
CPU time	754.26 seconds
Started	Jul 16 05:32:01 PM PDT 24
Finished	Jul 16 05:44:36 PM PDT 24
Peak memory	264340 kb
Host	smart-8430e4e1-583c-4ed6-bd4d-ea9c28d4bb72
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660228660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.flash_ctrl_hw_rma_reset.3660228660
Directory	/workspace/4.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.3779494155
Short name	T312
Test name
Test status
Simulation time	10661836100 ps
CPU time	88.25 seconds
Started	Jul 16 05:30:59 PM PDT 24
Finished	Jul 16 05:32:28 PM PDT 24
Peak memory	263288 kb
Host	smart-d7a07fba-fdca-4c1c-b02a-4984d0783dff
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779494155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h w_sec_otp.3779494155
Directory	/workspace/4.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_integrity.2234975988
Short name	T240
Test name
Test status
Simulation time	7260103800 ps
CPU time	613.9 seconds
Started	Jul 16 05:36:00 PM PDT 24
Finished	Jul 16 05:46:15 PM PDT 24
Peak memory	334608 kb
Host	smart-d8498f93-d50e-49e2-94b7-911b4c628f48
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234975988 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_integrity.2234975988
Directory	/workspace/4.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd.831328139
Short name	T609
Test name
Test status
Simulation time	1670557800 ps
CPU time	179.88 seconds
Started	Jul 16 05:35:29 PM PDT 24
Finished	Jul 16 05:38:29 PM PDT 24
Peak memory	291004 kb
Host	smart-5f605191-b6d9-48a6-a3ff-c7c3c73d46c2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831328139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash _ctrl_intr_rd.831328139
Directory	/workspace/4.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.209721713
Short name	T444
Test name
Test status
Simulation time	48814773200 ps
CPU time	321.26 seconds
Started	Jul 16 05:36:00 PM PDT 24
Finished	Jul 16 05:41:22 PM PDT 24
Peak memory	284756 kb
Host	smart-9bea5945-3904-420b-ba84-235e61b035ae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209721713 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.209721713
Directory	/workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr.1107324315
Short name	T677
Test name
Test status
Simulation time	2170499400 ps
CPU time	63.27 seconds
Started	Jul 16 05:31:05 PM PDT 24
Finished	Jul 16 05:32:10 PM PDT 24
Peak memory	265208 kb
Host	smart-6cec5143-386b-4cdc-992e-619a163c6b7f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107324315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_intr_wr.1107324315
Directory	/workspace/4.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.420640160
Short name	T701
Test name
Test status
Simulation time	23780735800 ps
CPU time	181.48 seconds
Started	Jul 16 05:31:07 PM PDT 24
Finished	Jul 16 05:34:09 PM PDT 24
Peak memory	265264 kb
Host	smart-0104149e-a46b-4773-9f15-7c64277b9a72
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420 640160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.420640160
Directory	/workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_invalid_op.2708683047
Short name	T972
Test name
Test status
Simulation time	1645886300 ps
CPU time	62.29 seconds
Started	Jul 16 05:35:17 PM PDT 24
Finished	Jul 16 05:36:19 PM PDT 24
Peak memory	262732 kb
Host	smart-dcef244e-87a2-4fd9-9eea-3a00d1f52c6c
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708683047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.2708683047
Directory	/workspace/4.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mid_op_rst.1752963428
Short name	T181
Test name
Test status
Simulation time	2452194100 ps
CPU time	71.4 seconds
Started	Jul 16 05:31:00 PM PDT 24
Finished	Jul 16 05:32:12 PM PDT 24
Peak memory	260592 kb
Host	smart-7bcf8806-4087-4285-a28f-79af441f26af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752963428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.1752963428
Directory	/workspace/4.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mp_regions.588737818
Short name	T121
Test name
Test status
Simulation time	29514775000 ps
CPU time	439.98 seconds
Started	Jul 16 05:30:58 PM PDT 24
Finished	Jul 16 05:38:19 PM PDT 24
Peak memory	274784 kb
Host	smart-27adce11-9f22-423a-bf94-b27009e71960
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588737818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.588737818
Directory	/workspace/4.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/4.flash_ctrl_otp_reset.2154357173
Short name	T757
Test name
Test status
Simulation time	71190300 ps
CPU time	110.13 seconds
Started	Jul 16 05:31:04 PM PDT 24
Finished	Jul 16 05:32:55 PM PDT 24
Peak memory	259868 kb
Host	smart-ee3f799e-ad6a-40b7-9902-50e0a779481d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154357173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot p_reset.2154357173
Directory	/workspace/4.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_oversize_error.3869452633
Short name	T291
Test name
Test status
Simulation time	1829256000 ps
CPU time	187.54 seconds
Started	Jul 16 05:35:16 PM PDT 24
Finished	Jul 16 05:38:24 PM PDT 24
Peak memory	281748 kb
Host	smart-cceae4c5-e281-4a03-915a-c1397b13c56d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869452633 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.3869452633
Directory	/workspace/4.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb.1957878236
Short name	T804
Test name
Test status
Simulation time	754047200 ps
CPU time	456.83 seconds
Started	Jul 16 05:30:57 PM PDT 24
Finished	Jul 16 05:38:34 PM PDT 24
Peak memory	263160 kb
Host	smart-b2f299f3-026d-458b-8b73-427c8bea5c17
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1957878236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1957878236
Directory	/workspace/4.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.3685632127
Short name	T211
Test name
Test status
Simulation time	746054800 ps
CPU time	15.36 seconds
Started	Jul 16 05:31:25 PM PDT 24
Finished	Jul 16 05:31:42 PM PDT 24
Peak memory	261716 kb
Host	smart-ab1da2bb-a286-4bfc-adec-7dd5349855a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685632127 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.3685632127
Directory	/workspace/4.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/4.flash_ctrl_prog_reset.941794805
Short name	T441
Test name
Test status
Simulation time	87916700 ps
CPU time	13.47 seconds
Started	Jul 16 05:31:05 PM PDT 24
Finished	Jul 16 05:31:20 PM PDT 24
Peak memory	259096 kb
Host	smart-6b113b40-003d-425b-a65c-dd72f9429178
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941794805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.flash_ctrl_prog_reset.941794805
Directory	/workspace/4.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rand_ops.373599360
Short name	T148
Test name
Test status
Simulation time	407741900 ps
CPU time	1087.15 seconds
Started	Jul 16 05:31:03 PM PDT 24
Finished	Jul 16 05:49:11 PM PDT 24
Peak memory	287540 kb
Host	smart-036051c6-1d19-4bd4-99a6-d651490c9d51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373599360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.373599360
Directory	/workspace/4.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2827840297
Short name	T128
Test name
Test status
Simulation time	101418900 ps
CPU time	99.23 seconds
Started	Jul 16 05:36:09 PM PDT 24
Finished	Jul 16 05:37:49 PM PDT 24
Peak memory	262968 kb
Host	smart-18be4076-48c0-4175-b5e4-3aaa112ae7d3
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2827840297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2827840297
Directory	/workspace/4.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_re_evict.2875580145
Short name	T131
Test name
Test status
Simulation time	125503800 ps
CPU time	35.46 seconds
Started	Jul 16 05:32:27 PM PDT 24
Finished	Jul 16 05:33:03 PM PDT 24
Peak memory	275668 kb
Host	smart-0184da88-9e3d-4f79-a63f-e61d35b6bb94
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875580145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_re_evict.2875580145
Directory	/workspace/4.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.3497450511
Short name	T977
Test name
Test status
Simulation time	19268700 ps
CPU time	22.48 seconds
Started	Jul 16 05:31:04 PM PDT 24
Finished	Jul 16 05:31:27 PM PDT 24
Peak memory	265504 kb
Host	smart-85ad18e2-95a9-4429-a36e-3a1e64d8ddd3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497450511 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.3497450511
Directory	/workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.1608956232
Short name	T424
Test name
Test status
Simulation time	88562700 ps
CPU time	22.39 seconds
Started	Jul 16 05:30:58 PM PDT 24
Finished	Jul 16 05:31:21 PM PDT 24
Peak memory	265348 kb
Host	smart-5fdda64f-7866-4ff9-b567-72cd64f9e606
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608956232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_read_word_sweep_serr.1608956232
Directory	/workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro.942386884
Short name	T51
Test name
Test status
Simulation time	513658700 ps
CPU time	109.68 seconds
Started	Jul 16 05:30:57 PM PDT 24
Finished	Jul 16 05:32:48 PM PDT 24
Peak memory	291536 kb
Host	smart-2bc815c2-488a-4bdd-94e3-100333984c24
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942386884 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.flash_ctrl_ro.942386884
Directory	/workspace/4.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_derr.56086231
Short name	T519
Test name
Test status
Simulation time	1263568300 ps
CPU time	125 seconds
Started	Jul 16 05:35:58 PM PDT 24
Finished	Jul 16 05:38:03 PM PDT 24
Peak memory	281868 kb
Host	smart-7b0933eb-2cfe-4425-8ea3-83c8283f0d5a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 56086231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.56086231
Directory	/workspace/4.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_serr.804887644
Short name	T1010
Test name
Test status
Simulation time	1201608900 ps
CPU time	123.14 seconds
Started	Jul 16 05:30:57 PM PDT 24
Finished	Jul 16 05:33:01 PM PDT 24
Peak memory	281808 kb
Host	smart-65f61c1b-8323-4598-8e31-ed8b4e34e0a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804887644 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.804887644
Directory	/workspace/4.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw.4272077438
Short name	T199
Test name
Test status
Simulation time	12463252800 ps
CPU time	547.85 seconds
Started	Jul 16 05:30:58 PM PDT 24
Finished	Jul 16 05:40:06 PM PDT 24
Peak memory	309588 kb
Host	smart-1a20d27c-11ee-44b0-9617-632307122192
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272077438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.flash_ctrl_rw.4272077438
Directory	/workspace/4.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict.3588170979
Short name	T504
Test name
Test status
Simulation time	40326100 ps
CPU time	31.01 seconds
Started	Jul 16 05:31:18 PM PDT 24
Finished	Jul 16 05:31:49 PM PDT 24
Peak memory	275752 kb
Host	smart-a7243b43-034e-48b4-b13f-bc47e86f0e20
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588170979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_rw_evict.3588170979
Directory	/workspace/4.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.2538225278
Short name	T765
Test name
Test status
Simulation time	129972600 ps
CPU time	28.7 seconds
Started	Jul 16 05:34:24 PM PDT 24
Finished	Jul 16 05:34:54 PM PDT 24
Peak memory	273568 kb
Host	smart-4c961caf-1a9f-472a-80e4-83f5dc3f264e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538225278 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.2538225278
Directory	/workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_address.2532150108
Short name	T35
Test name
Test status
Simulation time	739900200 ps
CPU time	80.6 seconds
Started	Jul 16 05:36:24 PM PDT 24
Finished	Jul 16 05:37:45 PM PDT 24
Peak memory	265120 kb
Host	smart-ce16d5d8-eaea-4a83-8d07-fe63d63efaeb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532150108 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 4.flash_ctrl_serr_address.2532150108
Directory	/workspace/4.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_counter.1957972627
Short name	T867
Test name
Test status
Simulation time	922764500 ps
CPU time	60.28 seconds
Started	Jul 16 05:31:06 PM PDT 24
Finished	Jul 16 05:32:07 PM PDT 24
Peak memory	273748 kb
Host	smart-32d5bf79-4367-4731-804f-17329086dfdf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957972627 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_serr_counter.1957972627
Directory	/workspace/4.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke.1258558971
Short name	T1
Test name
Test status
Simulation time	115001000 ps
CPU time	123.81 seconds
Started	Jul 16 05:35:16 PM PDT 24
Finished	Jul 16 05:37:20 PM PDT 24
Peak memory	276380 kb
Host	smart-c1f4676e-0e7e-4157-bb4e-95f601021cc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258558971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.1258558971
Directory	/workspace/4.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke_hw.3359839207
Short name	T321
Test name
Test status
Simulation time	13186500 ps
CPU time	25.87 seconds
Started	Jul 16 05:30:58 PM PDT 24
Finished	Jul 16 05:31:24 PM PDT 24
Peak memory	259760 kb
Host	smart-d6af10ee-fff0-4193-8ba9-f6734de2a714
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3359839207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3359839207
Directory	/workspace/4.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_stress_all.2944470490
Short name	T960
Test name
Test status
Simulation time	2201102200 ps
CPU time	1232.85 seconds
Started	Jul 16 05:37:03 PM PDT 24
Finished	Jul 16 05:57:37 PM PDT 24
Peak memory	288564 kb
Host	smart-e9c35611-4e12-4aef-a18e-8e6f3c1ab6d4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944470490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres s_all.2944470490
Directory	/workspace/4.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sw_op.1162633061
Short name	T585
Test name
Test status
Simulation time	85053500 ps
CPU time	26.71 seconds
Started	Jul 16 05:31:44 PM PDT 24
Finished	Jul 16 05:32:11 PM PDT 24
Peak memory	262244 kb
Host	smart-0857724d-da3e-4046-9f75-e30c2008eaa4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1162633061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.1162633061
Directory	/workspace/4.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_wo.2822586529
Short name	T270
Test name
Test status
Simulation time	10242452200 ps
CPU time	181.65 seconds
Started	Jul 16 05:31:00 PM PDT 24
Finished	Jul 16 05:34:02 PM PDT 24
Peak memory	265360 kb
Host	smart-606b42c7-dfa0-44fb-953e-b1351d677ed2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822586529 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.flash_ctrl_wo.2822586529
Directory	/workspace/4.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/40.flash_ctrl_alert_test.3482223249
Short name	T487
Test name
Test status
Simulation time	45001900 ps
CPU time	13.68 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:37:17 PM PDT 24
Peak memory	258232 kb
Host	smart-af7106be-90a2-442a-8d5e-648c08ae6aba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482223249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test. 3482223249
Directory	/workspace/40.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.flash_ctrl_connect.1691598452
Short name	T576
Test name
Test status
Simulation time	24271400 ps
CPU time	16.11 seconds
Started	Jul 16 05:36:31 PM PDT 24
Finished	Jul 16 05:36:47 PM PDT 24
Peak memory	284284 kb
Host	smart-8611da10-6b5f-4e5f-8f79-85b51182e007
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1691598452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.1691598452
Directory	/workspace/40.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/40.flash_ctrl_disable.2433864921
Short name	T390
Test name
Test status
Simulation time	16827000 ps
CPU time	20.2 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:37:24 PM PDT 24
Peak memory	265376 kb
Host	smart-12036456-17e1-489a-8d18-16138e2f062c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433864921 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_disable.2433864921
Directory	/workspace/40.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.2974284898
Short name	T1027
Test name
Test status
Simulation time	4287622300 ps
CPU time	152.78 seconds
Started	Jul 16 05:36:32 PM PDT 24
Finished	Jul 16 05:39:05 PM PDT 24
Peak memory	263252 kb
Host	smart-e1737e28-f2d0-4a56-80e1-91b5f6cb470b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974284898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ hw_sec_otp.2974284898
Directory	/workspace/40.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/40.flash_ctrl_otp_reset.103009841
Short name	T1068
Test name
Test status
Simulation time	109474200 ps
CPU time	133.67 seconds
Started	Jul 16 05:36:35 PM PDT 24
Finished	Jul 16 05:38:51 PM PDT 24
Peak memory	260776 kb
Host	smart-ad2c802b-2f44-431f-b94d-cbe41563bdd9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103009841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ot p_reset.103009841
Directory	/workspace/40.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/40.flash_ctrl_sec_info_access.294643980
Short name	T829
Test name
Test status
Simulation time	9615030200 ps
CPU time	73.9 seconds
Started	Jul 16 05:36:35 PM PDT 24
Finished	Jul 16 05:37:51 PM PDT 24
Peak memory	263800 kb
Host	smart-7bd68c50-417f-472b-b2f6-d6d42c90434b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294643980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.294643980
Directory	/workspace/40.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/40.flash_ctrl_smoke.876667625
Short name	T758
Test name
Test status
Simulation time	19396700 ps
CPU time	52.22 seconds
Started	Jul 16 05:36:32 PM PDT 24
Finished	Jul 16 05:37:25 PM PDT 24
Peak memory	271248 kb
Host	smart-01393200-4b76-43d2-936a-159d18c517aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=876667625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.876667625
Directory	/workspace/40.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.flash_ctrl_alert_test.1878534768
Short name	T906
Test name
Test status
Simulation time	47386700 ps
CPU time	13.54 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:37:17 PM PDT 24
Peak memory	258152 kb
Host	smart-33312382-85d9-4ab9-95eb-0246dd54601a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878534768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test. 1878534768
Directory	/workspace/41.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.flash_ctrl_connect.599452344
Short name	T96
Test name
Test status
Simulation time	16795500 ps
CPU time	15.66 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:37:19 PM PDT 24
Peak memory	274676 kb
Host	smart-23971d74-380b-41fa-b05f-a7f43cc7cb7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=599452344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.599452344
Directory	/workspace/41.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/41.flash_ctrl_disable.789097793
Short name	T976
Test name
Test status
Simulation time	57472900 ps
CPU time	21.87 seconds
Started	Jul 16 05:36:46 PM PDT 24
Finished	Jul 16 05:37:08 PM PDT 24
Peak memory	273528 kb
Host	smart-35e36d7e-4d3f-40bf-8800-20c8b8d077b4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789097793 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_disable.789097793
Directory	/workspace/41.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.2076559572
Short name	T514
Test name
Test status
Simulation time	1759673600 ps
CPU time	36.22 seconds
Started	Jul 16 05:36:34 PM PDT 24
Finished	Jul 16 05:37:12 PM PDT 24
Peak memory	260988 kb
Host	smart-aa0461fb-4931-4861-b629-80877a1bffbe
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076559572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ hw_sec_otp.2076559572
Directory	/workspace/41.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/41.flash_ctrl_smoke.450453988
Short name	T99
Test name
Test status
Simulation time	96604400 ps
CPU time	124.76 seconds
Started	Jul 16 05:36:31 PM PDT 24
Finished	Jul 16 05:38:37 PM PDT 24
Peak memory	278284 kb
Host	smart-f6a2984e-60ae-4f21-a7d8-cec03ad577c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450453988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.450453988
Directory	/workspace/41.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.flash_ctrl_alert_test.3099732128
Short name	T998
Test name
Test status
Simulation time	35788800 ps
CPU time	13.17 seconds
Started	Jul 16 05:36:30 PM PDT 24
Finished	Jul 16 05:36:44 PM PDT 24
Peak memory	265108 kb
Host	smart-0655c304-c1f9-4bca-9d13-0074fb8c3bd3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099732128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test. 3099732128
Directory	/workspace/42.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.flash_ctrl_connect.1468083016
Short name	T680
Test name
Test status
Simulation time	16366500 ps
CPU time	16.01 seconds
Started	Jul 16 05:36:52 PM PDT 24
Finished	Jul 16 05:37:09 PM PDT 24
Peak memory	274780 kb
Host	smart-63eadfa6-6529-4279-87ee-64c0bdf2ba0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1468083016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1468083016
Directory	/workspace/42.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/42.flash_ctrl_disable.1535090536
Short name	T784
Test name
Test status
Simulation time	10862400 ps
CPU time	21.63 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:37:25 PM PDT 24
Peak memory	273396 kb
Host	smart-a52460a4-70b0-49a9-a4fe-c78c5d73fec5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535090536 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_disable.1535090536
Directory	/workspace/42.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.62296106
Short name	T508
Test name
Test status
Simulation time	7256013800 ps
CPU time	67.55 seconds
Started	Jul 16 05:36:34 PM PDT 24
Finished	Jul 16 05:37:43 PM PDT 24
Peak memory	262856 kb
Host	smart-3a7cd743-63df-4890-ad85-998ef29b0546
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62296106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw _sec_otp.62296106
Directory	/workspace/42.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/42.flash_ctrl_otp_reset.1628343455
Short name	T168
Test name
Test status
Simulation time	123627400 ps
CPU time	113.24 seconds
Started	Jul 16 05:36:32 PM PDT 24
Finished	Jul 16 05:38:26 PM PDT 24
Peak memory	260108 kb
Host	smart-9fad96c7-d0dd-47dc-83eb-4731c45fc705
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628343455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o tp_reset.1628343455
Directory	/workspace/42.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/42.flash_ctrl_sec_info_access.1975206112
Short name	T778
Test name
Test status
Simulation time	4661907400 ps
CPU time	61.2 seconds
Started	Jul 16 05:36:35 PM PDT 24
Finished	Jul 16 05:37:38 PM PDT 24
Peak memory	262812 kb
Host	smart-6879a03f-d78e-4edf-a194-1a0b6f9d1342
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1975206112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.1975206112
Directory	/workspace/42.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/42.flash_ctrl_smoke.3315226018
Short name	T232
Test name
Test status
Simulation time	117950600 ps
CPU time	146.83 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:39:30 PM PDT 24
Peak memory	279384 kb
Host	smart-0740658e-17c5-4fcb-acda-3f028c5eef71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315226018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3315226018
Directory	/workspace/42.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.flash_ctrl_alert_test.493058907
Short name	T430
Test name
Test status
Simulation time	43182200 ps
CPU time	13.61 seconds
Started	Jul 16 05:36:49 PM PDT 24
Finished	Jul 16 05:37:03 PM PDT 24
Peak memory	265080 kb
Host	smart-b11abe11-a6f4-44c2-b51a-81635043cf8a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493058907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.493058907
Directory	/workspace/43.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.flash_ctrl_connect.3173564398
Short name	T557
Test name
Test status
Simulation time	48578400 ps
CPU time	16.27 seconds
Started	Jul 16 05:36:40 PM PDT 24
Finished	Jul 16 05:36:58 PM PDT 24
Peak memory	274968 kb
Host	smart-57bec49e-8eec-4ad3-a9d2-cceee35cf2d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173564398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3173564398
Directory	/workspace/43.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/43.flash_ctrl_disable.1970824641
Short name	T376
Test name
Test status
Simulation time	10280100 ps
CPU time	22.11 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:37:13 PM PDT 24
Peak memory	273472 kb
Host	smart-5d680d5c-6c69-4a24-a266-481f92c55feb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970824641 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_disable.1970824641
Directory	/workspace/43.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/43.flash_ctrl_hw_sec_otp.3027357793
Short name	T498
Test name
Test status
Simulation time	5834981200 ps
CPU time	80.08 seconds
Started	Jul 16 05:37:02 PM PDT 24
Finished	Jul 16 05:38:23 PM PDT 24
Peak memory	260764 kb
Host	smart-43e0b2ef-6559-4dc1-adca-c7d833af8648
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027357793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_ hw_sec_otp.3027357793
Directory	/workspace/43.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/43.flash_ctrl_otp_reset.2150579986
Short name	T388
Test name
Test status
Simulation time	48551400 ps
CPU time	133.58 seconds
Started	Jul 16 05:36:43 PM PDT 24
Finished	Jul 16 05:38:58 PM PDT 24
Peak memory	265072 kb
Host	smart-8577e85f-ff9f-40d6-8a68-79c0d56ba73e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150579986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o tp_reset.2150579986
Directory	/workspace/43.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/43.flash_ctrl_sec_info_access.216206625
Short name	T1060
Test name
Test status
Simulation time	7709189300 ps
CPU time	72.03 seconds
Started	Jul 16 05:36:40 PM PDT 24
Finished	Jul 16 05:37:53 PM PDT 24
Peak memory	262092 kb
Host	smart-146ed996-2646-41ed-b8c7-aa2e72252633
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216206625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.216206625
Directory	/workspace/43.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/43.flash_ctrl_smoke.2465292041
Short name	T657
Test name
Test status
Simulation time	61667800 ps
CPU time	99.28 seconds
Started	Jul 16 05:36:47 PM PDT 24
Finished	Jul 16 05:38:27 PM PDT 24
Peak memory	275924 kb
Host	smart-46a35014-79b1-40f3-90c2-1628d16576de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2465292041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2465292041
Directory	/workspace/43.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.flash_ctrl_alert_test.1201868052
Short name	T589
Test name
Test status
Simulation time	125456700 ps
CPU time	13.96 seconds
Started	Jul 16 05:36:41 PM PDT 24
Finished	Jul 16 05:36:57 PM PDT 24
Peak memory	258136 kb
Host	smart-4421ccb2-d037-469e-a19e-8ca54b48882c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201868052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test. 1201868052
Directory	/workspace/44.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.flash_ctrl_connect.187512299
Short name	T1045
Test name
Test status
Simulation time	23424700 ps
CPU time	16 seconds
Started	Jul 16 05:36:41 PM PDT 24
Finished	Jul 16 05:36:58 PM PDT 24
Peak memory	274772 kb
Host	smart-18d4044f-fca9-4aaa-8df3-59df83676d0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=187512299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.187512299
Directory	/workspace/44.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/44.flash_ctrl_disable.2837102763
Short name	T381
Test name
Test status
Simulation time	29033000 ps
CPU time	22.21 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:37:14 PM PDT 24
Peak memory	273460 kb
Host	smart-2b57b765-62bc-4c14-84c2-43e22cff7784
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837102763 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_disable.2837102763
Directory	/workspace/44.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1251010244
Short name	T515
Test name
Test status
Simulation time	4515815900 ps
CPU time	171.96 seconds
Started	Jul 16 05:36:40 PM PDT 24
Finished	Jul 16 05:39:34 PM PDT 24
Peak memory	263140 kb
Host	smart-de4c117c-9ae8-443d-a4db-b3d782577ddf
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251010244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ hw_sec_otp.1251010244
Directory	/workspace/44.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/44.flash_ctrl_otp_reset.691167410
Short name	T602
Test name
Test status
Simulation time	149721700 ps
CPU time	112.64 seconds
Started	Jul 16 05:36:43 PM PDT 24
Finished	Jul 16 05:38:37 PM PDT 24
Peak memory	265108 kb
Host	smart-cf0fa29f-4146-4d0d-8424-f528c32e68d3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691167410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ot p_reset.691167410
Directory	/workspace/44.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/44.flash_ctrl_sec_info_access.75522178
Short name	T413
Test name
Test status
Simulation time	2308911400 ps
CPU time	75.2 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:38:06 PM PDT 24
Peak memory	264616 kb
Host	smart-cde3332b-c0f5-4e28-bd4e-32c682370aa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75522178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.75522178
Directory	/workspace/44.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/44.flash_ctrl_smoke.2383120508
Short name	T247
Test name
Test status
Simulation time	296429200 ps
CPU time	52.4 seconds
Started	Jul 16 05:36:41 PM PDT 24
Finished	Jul 16 05:37:35 PM PDT 24
Peak memory	271284 kb
Host	smart-70426fd7-dea8-461c-b9f2-89537ed21ad3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2383120508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.2383120508
Directory	/workspace/44.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.flash_ctrl_alert_test.2143766180
Short name	T667
Test name
Test status
Simulation time	134182700 ps
CPU time	13.52 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:37:11 PM PDT 24
Peak memory	258220 kb
Host	smart-67519708-bb0a-44f9-854f-e8d56e724a54
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143766180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test. 2143766180
Directory	/workspace/45.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.flash_ctrl_connect.62172404
Short name	T384
Test name
Test status
Simulation time	14967400 ps
CPU time	16.4 seconds
Started	Jul 16 05:37:00 PM PDT 24
Finished	Jul 16 05:37:18 PM PDT 24
Peak memory	274800 kb
Host	smart-ccd97f89-fef8-4713-8e86-74bcd8f1fe9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62172404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.62172404
Directory	/workspace/45.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/45.flash_ctrl_disable.3816052677
Short name	T387
Test name
Test status
Simulation time	29554000 ps
CPU time	21.7 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:37:19 PM PDT 24
Peak memory	273408 kb
Host	smart-ea312c48-3b4f-4cf2-8b07-6a230ff2aecd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816052677 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_disable.3816052677
Directory	/workspace/45.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.4198594633
Short name	T1056
Test name
Test status
Simulation time	4961839600 ps
CPU time	144.52 seconds
Started	Jul 16 05:36:50 PM PDT 24
Finished	Jul 16 05:39:15 PM PDT 24
Peak memory	260916 kb
Host	smart-b0378ef7-9193-473a-a200-d9e3e881ac77
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198594633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_ hw_sec_otp.4198594633
Directory	/workspace/45.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/45.flash_ctrl_otp_reset.603056847
Short name	T790
Test name
Test status
Simulation time	67851600 ps
CPU time	133.35 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:39:09 PM PDT 24
Peak memory	261032 kb
Host	smart-0d7a1dae-a9a7-488f-96c3-d81c83ce4f1e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603056847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_ot p_reset.603056847
Directory	/workspace/45.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/45.flash_ctrl_sec_info_access.2740275351
Short name	T989
Test name
Test status
Simulation time	3813937000 ps
CPU time	64.3 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:38:01 PM PDT 24
Peak memory	263680 kb
Host	smart-b134198c-695e-4370-828f-3e045ae6ca3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2740275351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.2740275351
Directory	/workspace/45.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/45.flash_ctrl_smoke.1525740824
Short name	T617
Test name
Test status
Simulation time	67912500 ps
CPU time	123.63 seconds
Started	Jul 16 05:36:41 PM PDT 24
Finished	Jul 16 05:38:46 PM PDT 24
Peak memory	276900 kb
Host	smart-6a86a467-e334-4fd3-ad36-5d44d982a3fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525740824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1525740824
Directory	/workspace/45.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.flash_ctrl_alert_test.271310066
Short name	T928
Test name
Test status
Simulation time	31599000 ps
CPU time	13.33 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:37:10 PM PDT 24
Peak memory	265120 kb
Host	smart-c468cbfe-5b59-45a1-967d-0a072f20e0a0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271310066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.271310066
Directory	/workspace/46.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.flash_ctrl_connect.3340053170
Short name	T812
Test name
Test status
Simulation time	45925700 ps
CPU time	15.77 seconds
Started	Jul 16 05:36:52 PM PDT 24
Finished	Jul 16 05:37:09 PM PDT 24
Peak memory	274832 kb
Host	smart-c6e52983-5bb9-4d5a-bedc-2a0aef8b2158
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340053170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.3340053170
Directory	/workspace/46.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/46.flash_ctrl_disable.1884645000
Short name	T481
Test name
Test status
Simulation time	10379000 ps
CPU time	22.12 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:37:20 PM PDT 24
Peak memory	273596 kb
Host	smart-add9d2dd-bf66-41cf-af10-3f81e2ee28e8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884645000 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_disable.1884645000
Directory	/workspace/46.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/46.flash_ctrl_hw_sec_otp.1561981524
Short name	T953
Test name
Test status
Simulation time	3113135500 ps
CPU time	91.75 seconds
Started	Jul 16 05:36:52 PM PDT 24
Finished	Jul 16 05:38:25 PM PDT 24
Peak memory	260980 kb
Host	smart-ed20be56-dd76-4660-9722-cb4c560dec66
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561981524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ hw_sec_otp.1561981524
Directory	/workspace/46.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/46.flash_ctrl_otp_reset.2799051834
Short name	T571
Test name
Test status
Simulation time	72323000 ps
CPU time	131.9 seconds
Started	Jul 16 05:37:00 PM PDT 24
Finished	Jul 16 05:39:13 PM PDT 24
Peak memory	261024 kb
Host	smart-a9cf357e-5129-4dde-ade0-516f7f36545f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799051834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o tp_reset.2799051834
Directory	/workspace/46.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/46.flash_ctrl_sec_info_access.1170534863
Short name	T695
Test name
Test status
Simulation time	506060500 ps
CPU time	56.97 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:37:52 PM PDT 24
Peak memory	265064 kb
Host	smart-9d3b0b70-b624-4179-8e6c-0349db3ef4bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170534863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.1170534863
Directory	/workspace/46.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/46.flash_ctrl_smoke.456044729
Short name	T462
Test name
Test status
Simulation time	46528900 ps
CPU time	122.53 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:39:00 PM PDT 24
Peak memory	276300 kb
Host	smart-cceb1c7f-21fa-4941-9d96-18799835ab46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456044729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.456044729
Directory	/workspace/46.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.flash_ctrl_alert_test.3886896701
Short name	T599
Test name
Test status
Simulation time	62429100 ps
CPU time	13.87 seconds
Started	Jul 16 05:37:12 PM PDT 24
Finished	Jul 16 05:37:27 PM PDT 24
Peak memory	265172 kb
Host	smart-01826154-7367-444d-a127-835607484010
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886896701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test. 3886896701
Directory	/workspace/47.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.flash_ctrl_connect.2693798371
Short name	T503
Test name
Test status
Simulation time	13560900 ps
CPU time	16.22 seconds
Started	Jul 16 05:37:08 PM PDT 24
Finished	Jul 16 05:37:25 PM PDT 24
Peak memory	274924 kb
Host	smart-b42c4d67-9ef0-48db-9d97-e24efdc1adfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693798371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.2693798371
Directory	/workspace/47.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/47.flash_ctrl_disable.2089194402
Short name	T1067
Test name
Test status
Simulation time	11693700 ps
CPU time	22.09 seconds
Started	Jul 16 05:36:52 PM PDT 24
Finished	Jul 16 05:37:15 PM PDT 24
Peak memory	273552 kb
Host	smart-dc952ab3-1855-4e2f-8427-ba29ff35703f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089194402 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_disable.2089194402
Directory	/workspace/47.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/47.flash_ctrl_hw_sec_otp.3666738899
Short name	T767
Test name
Test status
Simulation time	3853588600 ps
CPU time	76.66 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:38:12 PM PDT 24
Peak memory	263288 kb
Host	smart-132d2e14-975b-4233-b258-f7aa87268e02
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666738899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ hw_sec_otp.3666738899
Directory	/workspace/47.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/47.flash_ctrl_otp_reset.99208731
Short name	T1100
Test name
Test status
Simulation time	269825800 ps
CPU time	129.32 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:39:07 PM PDT 24
Peak memory	261044 kb
Host	smart-137bf50b-245e-49cd-9fff-f4ca2da82f44
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99208731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp _reset.99208731
Directory	/workspace/47.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/47.flash_ctrl_sec_info_access.2415722683
Short name	T581
Test name
Test status
Simulation time	2832928000 ps
CPU time	77.7 seconds
Started	Jul 16 05:37:15 PM PDT 24
Finished	Jul 16 05:38:33 PM PDT 24
Peak memory	263752 kb
Host	smart-2560c970-836e-4f2b-8e3d-945f1a751764
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415722683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2415722683
Directory	/workspace/47.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/47.flash_ctrl_smoke.3491851280
Short name	T990
Test name
Test status
Simulation time	85504800 ps
CPU time	196.55 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:40:13 PM PDT 24
Peak memory	280468 kb
Host	smart-bcb09993-150c-4504-804a-79500cc9078a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3491851280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3491851280
Directory	/workspace/47.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.flash_ctrl_alert_test.362852769
Short name	T628
Test name
Test status
Simulation time	26437300 ps
CPU time	13.39 seconds
Started	Jul 16 05:37:11 PM PDT 24
Finished	Jul 16 05:37:26 PM PDT 24
Peak memory	265276 kb
Host	smart-216013e3-13c8-48d8-b506-669c74877b59
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362852769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.362852769
Directory	/workspace/48.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.flash_ctrl_connect.285121769
Short name	T825
Test name
Test status
Simulation time	14163200 ps
CPU time	15.94 seconds
Started	Jul 16 05:37:08 PM PDT 24
Finished	Jul 16 05:37:24 PM PDT 24
Peak memory	284408 kb
Host	smart-bfbec16e-077b-4d62-bacf-731e28ed7d3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=285121769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.285121769
Directory	/workspace/48.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/48.flash_ctrl_disable.3996565451
Short name	T798
Test name
Test status
Simulation time	21206600 ps
CPU time	21.54 seconds
Started	Jul 16 05:37:10 PM PDT 24
Finished	Jul 16 05:37:32 PM PDT 24
Peak memory	273580 kb
Host	smart-40082fec-b675-4f28-bbdb-13dedf5d931d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996565451 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_disable.3996565451
Directory	/workspace/48.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/48.flash_ctrl_hw_sec_otp.4099290309
Short name	T943
Test name
Test status
Simulation time	12517490200 ps
CPU time	160.28 seconds
Started	Jul 16 05:37:12 PM PDT 24
Finished	Jul 16 05:39:53 PM PDT 24
Peak memory	260940 kb
Host	smart-d02ee09e-e0f6-41f4-88ae-25d9cec7db39
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099290309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ hw_sec_otp.4099290309
Directory	/workspace/48.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/48.flash_ctrl_sec_info_access.2349022380
Short name	T398
Test name
Test status
Simulation time	2267767400 ps
CPU time	69.57 seconds
Started	Jul 16 05:37:11 PM PDT 24
Finished	Jul 16 05:38:22 PM PDT 24
Peak memory	263692 kb
Host	smart-4053072b-0469-44e8-96f6-4bcc363aa738
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349022380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2349022380
Directory	/workspace/48.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/48.flash_ctrl_smoke.3853235684
Short name	T655
Test name
Test status
Simulation time	267156000 ps
CPU time	102.8 seconds
Started	Jul 16 05:37:10 PM PDT 24
Finished	Jul 16 05:38:54 PM PDT 24
Peak memory	276024 kb
Host	smart-c5897ea3-d42d-4109-aac7-6f5abf720d40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3853235684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3853235684
Directory	/workspace/48.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.flash_ctrl_alert_test.1224376447
Short name	T792
Test name
Test status
Simulation time	148295000 ps
CPU time	13.69 seconds
Started	Jul 16 05:37:13 PM PDT 24
Finished	Jul 16 05:37:27 PM PDT 24
Peak memory	258288 kb
Host	smart-560dd90e-ec4f-4e0b-a7c2-ea9008f3f8f3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224376447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test. 1224376447
Directory	/workspace/49.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.flash_ctrl_connect.642188526
Short name	T1001
Test name
Test status
Simulation time	13794600 ps
CPU time	15.96 seconds
Started	Jul 16 05:37:15 PM PDT 24
Finished	Jul 16 05:37:31 PM PDT 24
Peak memory	274844 kb
Host	smart-98d44e44-0d6e-4012-8782-fdf69a35e804
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=642188526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.642188526
Directory	/workspace/49.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/49.flash_ctrl_disable.2885910527
Short name	T92
Test name
Test status
Simulation time	31600800 ps
CPU time	22.02 seconds
Started	Jul 16 05:37:14 PM PDT 24
Finished	Jul 16 05:37:36 PM PDT 24
Peak memory	273508 kb
Host	smart-ec489ae7-60fc-4511-a62f-252b1ae57f06
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885910527 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_disable.2885910527
Directory	/workspace/49.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.4010825269
Short name	T1008
Test name
Test status
Simulation time	38081527600 ps
CPU time	132.42 seconds
Started	Jul 16 05:37:23 PM PDT 24
Finished	Jul 16 05:39:36 PM PDT 24
Peak memory	260948 kb
Host	smart-be05f31e-e855-48d1-822b-f2df5a4b695e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010825269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ hw_sec_otp.4010825269
Directory	/workspace/49.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/49.flash_ctrl_otp_reset.2414150190
Short name	T741
Test name
Test status
Simulation time	36893600 ps
CPU time	109.75 seconds
Started	Jul 16 05:37:11 PM PDT 24
Finished	Jul 16 05:39:02 PM PDT 24
Peak memory	260160 kb
Host	smart-aa59e494-d60b-4527-9b82-82da1a8bf19c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414150190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o tp_reset.2414150190
Directory	/workspace/49.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/49.flash_ctrl_sec_info_access.2795384835
Short name	T42
Test name
Test status
Simulation time	10534119400 ps
CPU time	81.44 seconds
Started	Jul 16 05:37:10 PM PDT 24
Finished	Jul 16 05:38:33 PM PDT 24
Peak memory	264936 kb
Host	smart-3c4cd323-ee8b-433a-8638-c83319cb8835
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2795384835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.2795384835
Directory	/workspace/49.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/49.flash_ctrl_smoke.3516299152
Short name	T434
Test name
Test status
Simulation time	66808600 ps
CPU time	74.45 seconds
Started	Jul 16 05:37:07 PM PDT 24
Finished	Jul 16 05:38:22 PM PDT 24
Peak memory	275384 kb
Host	smart-5845a6dd-e1eb-48cc-a8e9-19001c67bbc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516299152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.3516299152
Directory	/workspace/49.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_alert_test.1870110590
Short name	T142
Test name
Test status
Simulation time	116607500 ps
CPU time	13.78 seconds
Started	Jul 16 05:31:40 PM PDT 24
Finished	Jul 16 05:31:54 PM PDT 24
Peak memory	265176 kb
Host	smart-09258aa4-137d-4067-9448-a5a5b7e6db63
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870110590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.1 870110590
Directory	/workspace/5.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.flash_ctrl_connect.3868753969
Short name	T761
Test name
Test status
Simulation time	19773500 ps
CPU time	13.12 seconds
Started	Jul 16 05:36:13 PM PDT 24
Finished	Jul 16 05:36:27 PM PDT 24
Peak memory	284340 kb
Host	smart-375f04e1-d647-42df-8a29-a77e4b75e889
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3868753969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.3868753969
Directory	/workspace/5.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/5.flash_ctrl_disable.3634667203
Short name	T752
Test name
Test status
Simulation time	13672600 ps
CPU time	19.93 seconds
Started	Jul 16 05:31:38 PM PDT 24
Finished	Jul 16 05:31:59 PM PDT 24
Peak memory	273508 kb
Host	smart-41a59c95-0470-46ed-8282-e2d15ac05d83
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634667203 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_disable.3634667203
Directory	/workspace/5.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_mp.1956177234
Short name	T539
Test name
Test status
Simulation time	19564399800 ps
CPU time	2200.65 seconds
Started	Jul 16 05:31:27 PM PDT 24
Finished	Jul 16 06:08:09 PM PDT 24
Peak memory	264436 kb
Host	smart-908c4d31-ba7b-4135-bf7f-380185870ab9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1956177234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.1956177234
Directory	/workspace/5.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_prog_win.266804482
Short name	T939
Test name
Test status
Simulation time	2398293600 ps
CPU time	823.52 seconds
Started	Jul 16 05:31:29 PM PDT 24
Finished	Jul 16 05:45:13 PM PDT 24
Peak memory	273968 kb
Host	smart-caf993c2-bdbd-4bc0-a0b3-acae73cf2f8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266804482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.266804482
Directory	/workspace/5.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/5.flash_ctrl_fetch_code.1381320234
Short name	T764
Test name
Test status
Simulation time	248726100 ps
CPU time	23.99 seconds
Started	Jul 16 05:31:35 PM PDT 24
Finished	Jul 16 05:32:00 PM PDT 24
Peak memory	262520 kb
Host	smart-03e6b5e7-1089-44e0-b946-cf333da175fb
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381320234 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1381320234
Directory	/workspace/5.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.4157993672
Short name	T191
Test name
Test status
Simulation time	10060214800 ps
CPU time	45.83 seconds
Started	Jul 16 05:31:44 PM PDT 24
Finished	Jul 16 05:32:30 PM PDT 24
Peak memory	265392 kb
Host	smart-e382d673-7a07-4cdc-b472-1c8c72c17936
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157993672 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.4157993672
Directory	/workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.3658868512
Short name	T186
Test name
Test status
Simulation time	15601100 ps
CPU time	13.3 seconds
Started	Jul 16 05:31:39 PM PDT 24
Finished	Jul 16 05:31:54 PM PDT 24
Peak memory	264912 kb
Host	smart-0c920cfe-5a27-4c16-a769-1e26697bb19d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658868512 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.3658868512
Directory	/workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_rma_reset.190212589
Short name	T171
Test name
Test status
Simulation time	80152769000 ps
CPU time	873.95 seconds
Started	Jul 16 05:31:30 PM PDT 24
Finished	Jul 16 05:46:05 PM PDT 24
Peak memory	265000 kb
Host	smart-90ec1be0-f708-409e-be56-2be05080d3bf
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190212589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.flash_ctrl_hw_rma_reset.190212589
Directory	/workspace/5.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.524467279
Short name	T1071
Test name
Test status
Simulation time	21492384200 ps
CPU time	251.39 seconds
Started	Jul 16 05:31:25 PM PDT 24
Finished	Jul 16 05:35:38 PM PDT 24
Peak memory	260716 kb
Host	smart-7ce893be-935a-4022-8343-ae28803afab4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524467279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw _sec_otp.524467279
Directory	/workspace/5.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd.1020185218
Short name	T826
Test name
Test status
Simulation time	8604634600 ps
CPU time	194.19 seconds
Started	Jul 16 05:31:30 PM PDT 24
Finished	Jul 16 05:34:45 PM PDT 24
Peak memory	291468 kb
Host	smart-a7c9b4c7-7bc6-474f-902b-c8f2813575e5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020185218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_intr_rd.1020185218
Directory	/workspace/5.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.55078148
Short name	T954
Test name
Test status
Simulation time	202392000500 ps
CPU time	430 seconds
Started	Jul 16 05:31:27 PM PDT 24
Finished	Jul 16 05:38:38 PM PDT 24
Peak memory	291068 kb
Host	smart-a78ff7d8-888f-468d-b7a4-bc29a6c53b67
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55078148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.55078148
Directory	/workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr.446241417
Short name	T632
Test name
Test status
Simulation time	2910506900 ps
CPU time	82.31 seconds
Started	Jul 16 05:31:28 PM PDT 24
Finished	Jul 16 05:32:51 PM PDT 24
Peak memory	265144 kb
Host	smart-e54dc25f-7c3c-4dfd-b283-c6c40f17f7aa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446241417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 5.flash_ctrl_intr_wr.446241417
Directory	/workspace/5.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.37713901
Short name	T955
Test name
Test status
Simulation time	44363421500 ps
CPU time	176.6 seconds
Started	Jul 16 05:31:28 PM PDT 24
Finished	Jul 16 05:34:25 PM PDT 24
Peak memory	260388 kb
Host	smart-5b53e429-b0c1-4e6b-a83b-fb7f53a354f2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377 13901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.37713901
Directory	/workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_invalid_op.1885792229
Short name	T1022
Test name
Test status
Simulation time	4214945400 ps
CPU time	67.02 seconds
Started	Jul 16 05:31:35 PM PDT 24
Finished	Jul 16 05:32:43 PM PDT 24
Peak memory	262632 kb
Host	smart-f4b5045d-fa12-4643-9acf-bc2fad41d786
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885792229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1885792229
Directory	/workspace/5.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/5.flash_ctrl_lcmgr_intg.261081664
Short name	T153
Test name
Test status
Simulation time	30947200 ps
CPU time	13.34 seconds
Started	Jul 16 05:31:36 PM PDT 24
Finished	Jul 16 05:31:50 PM PDT 24
Peak memory	260100 kb
Host	smart-7a6025c5-ac7c-4fe6-a891-495944abf2dd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261081664 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.261081664
Directory	/workspace/5.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/5.flash_ctrl_otp_reset.3391869869
Short name	T801
Test name
Test status
Simulation time	62121500 ps
CPU time	135.03 seconds
Started	Jul 16 05:31:29 PM PDT 24
Finished	Jul 16 05:33:44 PM PDT 24
Peak memory	259928 kb
Host	smart-8a6ea6be-5105-4b53-b969-06156bec875e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391869869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot p_reset.3391869869
Directory	/workspace/5.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_phy_arb.2455130117
Short name	T840
Test name
Test status
Simulation time	40434579300 ps
CPU time	548.11 seconds
Started	Jul 16 05:31:25 PM PDT 24
Finished	Jul 16 05:40:34 PM PDT 24
Peak memory	263096 kb
Host	smart-e538ce93-c9a5-46e8-aa2e-31e945bc21e1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2455130117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.2455130117
Directory	/workspace/5.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/5.flash_ctrl_prog_reset.3570061489
Short name	T97
Test name
Test status
Simulation time	50977400 ps
CPU time	14.51 seconds
Started	Jul 16 05:31:44 PM PDT 24
Finished	Jul 16 05:31:59 PM PDT 24
Peak memory	259828 kb
Host	smart-e73894c5-b36f-4117-8f25-3ddf19bbbb4d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570061489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.flash_ctrl_prog_reset.3570061489
Directory	/workspace/5.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rand_ops.2681489702
Short name	T135
Test name
Test status
Simulation time	35752200 ps
CPU time	144.13 seconds
Started	Jul 16 05:31:22 PM PDT 24
Finished	Jul 16 05:33:46 PM PDT 24
Peak memory	277200 kb
Host	smart-1eed6bd3-d83e-42dc-bd28-45742db6202c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681489702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.2681489702
Directory	/workspace/5.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/5.flash_ctrl_re_evict.2088515793
Short name	T280
Test name
Test status
Simulation time	72079600 ps
CPU time	35.7 seconds
Started	Jul 16 05:31:44 PM PDT 24
Finished	Jul 16 05:32:20 PM PDT 24
Peak memory	277384 kb
Host	smart-fcfe894e-ffa7-4cf0-913f-632720d08841
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088515793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_re_evict.2088515793
Directory	/workspace/5.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_derr.1753510237
Short name	T239
Test name
Test status
Simulation time	2429688100 ps
CPU time	165.44 seconds
Started	Jul 16 05:31:35 PM PDT 24
Finished	Jul 16 05:34:21 PM PDT 24
Peak memory	281780 kb
Host	smart-e04bff14-f222-4aab-80fa-3f4ea52f57da
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1753510237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1753510237
Directory	/workspace/5.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_serr.211407897
Short name	T715
Test name
Test status
Simulation time	1512152900 ps
CPU time	146.44 seconds
Started	Jul 16 05:31:35 PM PDT 24
Finished	Jul 16 05:34:02 PM PDT 24
Peak memory	281704 kb
Host	smart-c0308c18-b288-450b-864b-08d4e097acfe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211407897 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.211407897
Directory	/workspace/5.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw.433981496
Short name	T575
Test name
Test status
Simulation time	6861228300 ps
CPU time	485.41 seconds
Started	Jul 16 05:31:27 PM PDT 24
Finished	Jul 16 05:39:33 PM PDT 24
Peak memory	309408 kb
Host	smart-0dcc6b88-688c-454b-bb22-483acd029d9a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433981496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.433981496
Directory	/workspace/5.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_derr.3985451473
Short name	T925
Test name
Test status
Simulation time	3654333600 ps
CPU time	531.39 seconds
Started	Jul 16 05:31:33 PM PDT 24
Finished	Jul 16 05:40:25 PM PDT 24
Peak memory	328440 kb
Host	smart-563ee282-8888-49b5-ba1f-30813293ff8d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985451473 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_rw_derr.3985451473
Directory	/workspace/5.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict.2541000391
Short name	T16
Test name
Test status
Simulation time	79750200 ps
CPU time	30.91 seconds
Started	Jul 16 05:31:37 PM PDT 24
Finished	Jul 16 05:32:09 PM PDT 24
Peak memory	273808 kb
Host	smart-9c0a143c-bbbd-49ac-bf00-c875302d3603
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541000391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_rw_evict.2541000391
Directory	/workspace/5.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.1570125324
Short name	T653
Test name
Test status
Simulation time	65725400 ps
CPU time	30.93 seconds
Started	Jul 16 05:31:44 PM PDT 24
Finished	Jul 16 05:32:15 PM PDT 24
Peak memory	268416 kb
Host	smart-1c15e7cd-70f3-4a17-b194-22d4f324253b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570125324 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.1570125324
Directory	/workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_serr.4284113381
Short name	T935
Test name
Test status
Simulation time	6926987500 ps
CPU time	582.86 seconds
Started	Jul 16 05:31:29 PM PDT 24
Finished	Jul 16 05:41:13 PM PDT 24
Peak memory	312652 kb
Host	smart-e75ce352-db44-4a22-b285-b76c2c8834c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284113381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s err.4284113381
Directory	/workspace/5.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_sec_info_access.3652561437
Short name	T505
Test name
Test status
Simulation time	27055414400 ps
CPU time	79.76 seconds
Started	Jul 16 05:32:19 PM PDT 24
Finished	Jul 16 05:33:39 PM PDT 24
Peak memory	263728 kb
Host	smart-3fa2de4d-5109-4852-aea0-a6e1beed8ce0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652561437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3652561437
Directory	/workspace/5.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/5.flash_ctrl_smoke.2554853968
Short name	T835
Test name
Test status
Simulation time	59493000 ps
CPU time	121.11 seconds
Started	Jul 16 05:31:21 PM PDT 24
Finished	Jul 16 05:33:22 PM PDT 24
Peak memory	268868 kb
Host	smart-edc40e46-470e-470a-b89f-1890c9b79297
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554853968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2554853968
Directory	/workspace/5.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_wo.878277978
Short name	T704
Test name
Test status
Simulation time	29770224600 ps
CPU time	136.55 seconds
Started	Jul 16 05:31:35 PM PDT 24
Finished	Jul 16 05:33:52 PM PDT 24
Peak memory	259892 kb
Host	smart-4145d253-5e57-4107-90eb-5bfd32f47134
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878277978 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 5.flash_ctrl_wo.878277978
Directory	/workspace/5.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/50.flash_ctrl_connect.3519563727
Short name	T482
Test name
Test status
Simulation time	41320600 ps
CPU time	15.45 seconds
Started	Jul 16 05:37:11 PM PDT 24
Finished	Jul 16 05:37:27 PM PDT 24
Peak memory	274748 kb
Host	smart-c3939248-ab5e-4a68-a8cf-b54475ba9714
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3519563727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3519563727
Directory	/workspace/50.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/50.flash_ctrl_otp_reset.230203709
Short name	T61
Test name
Test status
Simulation time	40545700 ps
CPU time	109.67 seconds
Started	Jul 16 05:37:10 PM PDT 24
Finished	Jul 16 05:39:01 PM PDT 24
Peak memory	260048 kb
Host	smart-1b520484-2857-413b-a672-f53abc42aa87
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230203709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_ot p_reset.230203709
Directory	/workspace/50.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/51.flash_ctrl_connect.626122237
Short name	T723
Test name
Test status
Simulation time	29522300 ps
CPU time	15.83 seconds
Started	Jul 16 05:37:12 PM PDT 24
Finished	Jul 16 05:37:28 PM PDT 24
Peak memory	274916 kb
Host	smart-994f8760-dba8-40bb-80b2-832ffae0dec1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=626122237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.626122237
Directory	/workspace/51.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/51.flash_ctrl_otp_reset.1657529867
Short name	T864
Test name
Test status
Simulation time	148402900 ps
CPU time	135.58 seconds
Started	Jul 16 05:37:11 PM PDT 24
Finished	Jul 16 05:39:27 PM PDT 24
Peak memory	264824 kb
Host	smart-1f8daf69-6114-42b9-b4d2-d0bfe3372e56
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657529867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o tp_reset.1657529867
Directory	/workspace/51.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/52.flash_ctrl_connect.1957283726
Short name	T862
Test name
Test status
Simulation time	15446700 ps
CPU time	13.86 seconds
Started	Jul 16 05:37:09 PM PDT 24
Finished	Jul 16 05:37:23 PM PDT 24
Peak memory	274820 kb
Host	smart-3bde5f66-af86-4a06-b9ff-9f14a6232471
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957283726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1957283726
Directory	/workspace/52.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/52.flash_ctrl_otp_reset.1133756184
Short name	T905
Test name
Test status
Simulation time	98355300 ps
CPU time	131.59 seconds
Started	Jul 16 05:37:15 PM PDT 24
Finished	Jul 16 05:39:27 PM PDT 24
Peak memory	261060 kb
Host	smart-84b1db11-b2af-439f-9390-961447dd233d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133756184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o tp_reset.1133756184
Directory	/workspace/52.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/53.flash_ctrl_connect.1360443701
Short name	T560
Test name
Test status
Simulation time	48971100 ps
CPU time	14.1 seconds
Started	Jul 16 05:37:10 PM PDT 24
Finished	Jul 16 05:37:25 PM PDT 24
Peak memory	274888 kb
Host	smart-2d3f64ad-4952-4272-82b4-5e1b32dd32a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1360443701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1360443701
Directory	/workspace/53.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/53.flash_ctrl_otp_reset.3108324840
Short name	T660
Test name
Test status
Simulation time	78908900 ps
CPU time	131.65 seconds
Started	Jul 16 05:37:09 PM PDT 24
Finished	Jul 16 05:39:21 PM PDT 24
Peak memory	260116 kb
Host	smart-ae144faf-734b-4842-90c2-adf44e7bd496
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108324840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o tp_reset.3108324840
Directory	/workspace/53.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/54.flash_ctrl_connect.3615645693
Short name	T637
Test name
Test status
Simulation time	51575800 ps
CPU time	15.96 seconds
Started	Jul 16 05:37:15 PM PDT 24
Finished	Jul 16 05:37:31 PM PDT 24
Peak memory	284220 kb
Host	smart-15bd9785-81a4-449b-9eaa-bc889cc6946e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615645693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.3615645693
Directory	/workspace/54.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/54.flash_ctrl_otp_reset.1357473763
Short name	T887
Test name
Test status
Simulation time	42705300 ps
CPU time	132.72 seconds
Started	Jul 16 05:37:21 PM PDT 24
Finished	Jul 16 05:39:34 PM PDT 24
Peak memory	261028 kb
Host	smart-85e96b60-56ab-4de5-b6cb-4d7564446232
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357473763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o tp_reset.1357473763
Directory	/workspace/54.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/55.flash_ctrl_connect.2000669137
Short name	T899
Test name
Test status
Simulation time	100969800 ps
CPU time	13.3 seconds
Started	Jul 16 05:37:16 PM PDT 24
Finished	Jul 16 05:37:30 PM PDT 24
Peak memory	274820 kb
Host	smart-d9910ed2-adf5-4d5c-b5ef-54b45917754b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000669137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2000669137
Directory	/workspace/55.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/55.flash_ctrl_otp_reset.3272909411
Short name	T831
Test name
Test status
Simulation time	470558900 ps
CPU time	109.52 seconds
Started	Jul 16 05:37:11 PM PDT 24
Finished	Jul 16 05:39:02 PM PDT 24
Peak memory	261016 kb
Host	smart-65e8b43c-df82-4701-8ef4-ea467c057feb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272909411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o tp_reset.3272909411
Directory	/workspace/55.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/56.flash_ctrl_connect.203966049
Short name	T915
Test name
Test status
Simulation time	22949500 ps
CPU time	13.42 seconds
Started	Jul 16 05:37:11 PM PDT 24
Finished	Jul 16 05:37:26 PM PDT 24
Peak memory	284304 kb
Host	smart-72aa48c2-0b6a-4d46-bc4d-369cbf80ff9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203966049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.203966049
Directory	/workspace/56.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/56.flash_ctrl_otp_reset.1090118425
Short name	T901
Test name
Test status
Simulation time	77935600 ps
CPU time	134.36 seconds
Started	Jul 16 05:37:08 PM PDT 24
Finished	Jul 16 05:39:22 PM PDT 24
Peak memory	265156 kb
Host	smart-c9410775-3783-4b89-b476-4d2751a75e79
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090118425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o tp_reset.1090118425
Directory	/workspace/56.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/57.flash_ctrl_connect.1158647287
Short name	T1017
Test name
Test status
Simulation time	28701200 ps
CPU time	15.72 seconds
Started	Jul 16 05:37:15 PM PDT 24
Finished	Jul 16 05:37:31 PM PDT 24
Peak memory	274868 kb
Host	smart-72dc91d9-4f67-495e-9d60-a3d92bcaf696
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1158647287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.1158647287
Directory	/workspace/57.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/57.flash_ctrl_otp_reset.597298273
Short name	T893
Test name
Test status
Simulation time	489056500 ps
CPU time	131.5 seconds
Started	Jul 16 05:37:09 PM PDT 24
Finished	Jul 16 05:39:21 PM PDT 24
Peak memory	260204 kb
Host	smart-6c327b36-c8d1-47d8-9305-7e08cfe63280
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597298273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_ot p_reset.597298273
Directory	/workspace/57.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/58.flash_ctrl_connect.4292659464
Short name	T305
Test name
Test status
Simulation time	15151700 ps
CPU time	13.73 seconds
Started	Jul 16 05:37:16 PM PDT 24
Finished	Jul 16 05:37:31 PM PDT 24
Peak memory	284376 kb
Host	smart-a5868e8f-98f2-443d-b1e1-062a60e20511
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292659464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.4292659464
Directory	/workspace/58.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/59.flash_ctrl_connect.3703299097
Short name	T664
Test name
Test status
Simulation time	14080900 ps
CPU time	16.51 seconds
Started	Jul 16 05:37:17 PM PDT 24
Finished	Jul 16 05:37:34 PM PDT 24
Peak memory	274732 kb
Host	smart-90c678e0-40ea-48e2-99c3-0c7dfb278d4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703299097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.3703299097
Directory	/workspace/59.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/59.flash_ctrl_otp_reset.3330648601
Short name	T391
Test name
Test status
Simulation time	129489900 ps
CPU time	109.04 seconds
Started	Jul 16 05:37:12 PM PDT 24
Finished	Jul 16 05:39:02 PM PDT 24
Peak memory	259892 kb
Host	smart-84cdd774-2569-405e-96b9-6083a7b05afd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330648601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o tp_reset.3330648601
Directory	/workspace/59.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_alert_test.1329445437
Short name	T1110
Test name
Test status
Simulation time	95323100 ps
CPU time	13.88 seconds
Started	Jul 16 05:31:57 PM PDT 24
Finished	Jul 16 05:32:11 PM PDT 24
Peak memory	258228 kb
Host	smart-9a8d215d-da9a-42ff-99c7-9046442a686a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329445437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.1 329445437
Directory	/workspace/6.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.flash_ctrl_connect.4198172391
Short name	T936
Test name
Test status
Simulation time	26068100 ps
CPU time	15.74 seconds
Started	Jul 16 05:32:00 PM PDT 24
Finished	Jul 16 05:32:16 PM PDT 24
Peak memory	274952 kb
Host	smart-11c4d3d5-0d7a-4b0b-85e8-172467d2d3df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4198172391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.4198172391
Directory	/workspace/6.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/6.flash_ctrl_disable.2595277952
Short name	T940
Test name
Test status
Simulation time	12555100 ps
CPU time	21.87 seconds
Started	Jul 16 05:32:09 PM PDT 24
Finished	Jul 16 05:32:31 PM PDT 24
Peak memory	265336 kb
Host	smart-90cb41de-8130-4fdb-99b5-34746e9149a3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595277952 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_disable.2595277952
Directory	/workspace/6.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_mp.3031308690
Short name	T837
Test name
Test status
Simulation time	5817584600 ps
CPU time	2193.71 seconds
Started	Jul 16 05:31:50 PM PDT 24
Finished	Jul 16 06:08:24 PM PDT 24
Peak memory	264560 kb
Host	smart-0f4b5dd5-ad9e-4f62-800c-2afd076de0a3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3031308690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.3031308690
Directory	/workspace/6.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_prog_win.1083120159
Short name	T293
Test name
Test status
Simulation time	3225958500 ps
CPU time	875.03 seconds
Started	Jul 16 05:34:18 PM PDT 24
Finished	Jul 16 05:48:53 PM PDT 24
Peak memory	273336 kb
Host	smart-ae351197-4a9b-4292-852a-e454048e296c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083120159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.1083120159
Directory	/workspace/6.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.3567501585
Short name	T1070
Test name
Test status
Simulation time	89607800 ps
CPU time	13.29 seconds
Started	Jul 16 05:32:00 PM PDT 24
Finished	Jul 16 05:32:14 PM PDT 24
Peak memory	264960 kb
Host	smart-2ca09cc8-ff8a-4c92-b251-d024f997a4b3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567501585 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.3567501585
Directory	/workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_rma_reset.2507231342
Short name	T158
Test name
Test status
Simulation time	320251122000 ps
CPU time	1067.89 seconds
Started	Jul 16 05:31:36 PM PDT 24
Finished	Jul 16 05:49:25 PM PDT 24
Peak memory	262304 kb
Host	smart-570cb75d-05a4-40fb-a40c-3577b33dfc95
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507231342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.flash_ctrl_hw_rma_reset.2507231342
Directory	/workspace/6.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_sec_otp.1499516847
Short name	T1013
Test name
Test status
Simulation time	2304397700 ps
CPU time	89.86 seconds
Started	Jul 16 05:31:44 PM PDT 24
Finished	Jul 16 05:33:15 PM PDT 24
Peak memory	262652 kb
Host	smart-d3247546-bc11-4ed3-a9f3-9a8b599f202c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499516847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h w_sec_otp.1499516847
Directory	/workspace/6.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd.441367589
Short name	T544
Test name
Test status
Simulation time	1449850100 ps
CPU time	167.64 seconds
Started	Jul 16 05:31:56 PM PDT 24
Finished	Jul 16 05:34:44 PM PDT 24
Peak memory	291360 kb
Host	smart-8f02bb84-07d8-43d9-ab01-a43fcd62274c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441367589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash _ctrl_intr_rd.441367589
Directory	/workspace/6.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.4018154575
Short name	T331
Test name
Test status
Simulation time	25519289500 ps
CPU time	484.96 seconds
Started	Jul 16 05:31:59 PM PDT 24
Finished	Jul 16 05:40:05 PM PDT 24
Peak memory	291072 kb
Host	smart-1505a50e-2f99-44b1-8cf3-e11927047d69
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018154575 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.4018154575
Directory	/workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr.550213449
Short name	T821
Test name
Test status
Simulation time	4091664200 ps
CPU time	60.59 seconds
Started	Jul 16 05:32:30 PM PDT 24
Finished	Jul 16 05:33:32 PM PDT 24
Peak memory	260056 kb
Host	smart-a3130253-a160-47d9-a002-4e0338ae4bf5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550213449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 6.flash_ctrl_intr_wr.550213449
Directory	/workspace/6.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1307801912
Short name	T763
Test name
Test status
Simulation time	265364443100 ps
CPU time	432.46 seconds
Started	Jul 16 05:31:59 PM PDT 24
Finished	Jul 16 05:39:13 PM PDT 24
Peak memory	260348 kb
Host	smart-4a8ed9f1-5059-4351-a0b3-ff91be700c1c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130 7801912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.1307801912
Directory	/workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_invalid_op.2951242043
Short name	T415
Test name
Test status
Simulation time	19390909400 ps
CPU time	103.1 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:38:41 PM PDT 24
Peak memory	260468 kb
Host	smart-60f9c214-f879-443a-bb62-1d9fe91ec6f6
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951242043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.2951242043
Directory	/workspace/6.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/6.flash_ctrl_lcmgr_intg.2333018384
Short name	T154
Test name
Test status
Simulation time	15742300 ps
CPU time	13.38 seconds
Started	Jul 16 05:32:00 PM PDT 24
Finished	Jul 16 05:32:14 PM PDT 24
Peak memory	259896 kb
Host	smart-5ddbcdcd-c251-49e8-adfc-8c086f9f01bf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333018384 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.2333018384
Directory	/workspace/6.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/6.flash_ctrl_mp_regions.362684683
Short name	T122
Test name
Test status
Simulation time	19323161000 ps
CPU time	419.15 seconds
Started	Jul 16 05:31:48 PM PDT 24
Finished	Jul 16 05:38:47 PM PDT 24
Peak memory	274796 kb
Host	smart-f310c70a-e9f1-4ef4-ad19-d7ae4e5ae5b8
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362684683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.362684683
Directory	/workspace/6.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/6.flash_ctrl_otp_reset.4046897857
Short name	T605
Test name
Test status
Simulation time	74953900 ps
CPU time	133.17 seconds
Started	Jul 16 05:31:39 PM PDT 24
Finished	Jul 16 05:33:53 PM PDT 24
Peak memory	265068 kb
Host	smart-2ad9c83d-087d-4c52-afe4-711e81fed41a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046897857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot p_reset.4046897857
Directory	/workspace/6.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_phy_arb.2414878786
Short name	T439
Test name
Test status
Simulation time	188855300 ps
CPU time	226.45 seconds
Started	Jul 16 05:31:38 PM PDT 24
Finished	Jul 16 05:35:25 PM PDT 24
Peak memory	263008 kb
Host	smart-4617ff0a-3578-4629-9733-9167fdb8b287
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2414878786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.2414878786
Directory	/workspace/6.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/6.flash_ctrl_prog_reset.2269123244
Short name	T871
Test name
Test status
Simulation time	15198546700 ps
CPU time	185.25 seconds
Started	Jul 16 05:36:35 PM PDT 24
Finished	Jul 16 05:39:42 PM PDT 24
Peak memory	260584 kb
Host	smart-bcee93cc-3d04-40de-9a36-6385afb95abd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269123244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.flash_ctrl_prog_reset.2269123244
Directory	/workspace/6.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_re_evict.346181255
Short name	T343
Test name
Test status
Simulation time	134400600 ps
CPU time	31.68 seconds
Started	Jul 16 05:32:01 PM PDT 24
Finished	Jul 16 05:32:33 PM PDT 24
Peak memory	269996 kb
Host	smart-14f0853e-431f-478a-bb5e-db96a56a4246
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346181255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_re_evict.346181255
Directory	/workspace/6.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro.3750708335
Short name	T1115
Test name
Test status
Simulation time	579635500 ps
CPU time	141.24 seconds
Started	Jul 16 05:31:49 PM PDT 24
Finished	Jul 16 05:34:10 PM PDT 24
Peak memory	281772 kb
Host	smart-99896041-4f72-41c5-87d9-651679bac911
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750708335 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_ro.3750708335
Directory	/workspace/6.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_derr.1916368850
Short name	T241
Test name
Test status
Simulation time	1257561300 ps
CPU time	129.03 seconds
Started	Jul 16 05:31:49 PM PDT 24
Finished	Jul 16 05:33:59 PM PDT 24
Peak memory	281816 kb
Host	smart-fe490f0f-974e-4b12-bd5c-64a7cba18c6c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1916368850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.1916368850
Directory	/workspace/6.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_serr.627262937
Short name	T858
Test name
Test status
Simulation time	2977832800 ps
CPU time	140.2 seconds
Started	Jul 16 05:31:50 PM PDT 24
Finished	Jul 16 05:34:11 PM PDT 24
Peak memory	281648 kb
Host	smart-f2ac863a-5ed6-42a4-9f48-a2f1a7e7fbfc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627262937 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.627262937
Directory	/workspace/6.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw.2953418205
Short name	T533
Test name
Test status
Simulation time	15289417500 ps
CPU time	572.95 seconds
Started	Jul 16 05:31:49 PM PDT 24
Finished	Jul 16 05:41:23 PM PDT 24
Peak memory	319368 kb
Host	smart-98f05832-a7b2-4254-9ce5-2cd5eae55b63
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953418205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.flash_ctrl_rw.2953418205
Directory	/workspace/6.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict.3665382278
Short name	T844
Test name
Test status
Simulation time	46488300 ps
CPU time	31.2 seconds
Started	Jul 16 05:32:01 PM PDT 24
Finished	Jul 16 05:32:33 PM PDT 24
Peak memory	268456 kb
Host	smart-388f0aa8-9801-47ad-b1a6-05c5543fb6a3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665382278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla sh_ctrl_rw_evict.3665382278
Directory	/workspace/6.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.4176819566
Short name	T50
Test name
Test status
Simulation time	27855200 ps
CPU time	31.39 seconds
Started	Jul 16 05:31:58 PM PDT 24
Finished	Jul 16 05:32:31 PM PDT 24
Peak memory	268484 kb
Host	smart-1edbbee9-de1c-462d-ab87-ffffcc2bae2a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176819566 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.4176819566
Directory	/workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_serr.2342711447
Short name	T775
Test name
Test status
Simulation time	6323674600 ps
CPU time	739.85 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:49:17 PM PDT 24
Peak memory	312632 kb
Host	smart-aebd1eaa-8627-434e-9158-7f365336c68c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342711447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s err.2342711447
Directory	/workspace/6.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_sec_info_access.4243729623
Short name	T912
Test name
Test status
Simulation time	20078371400 ps
CPU time	80.42 seconds
Started	Jul 16 05:32:00 PM PDT 24
Finished	Jul 16 05:33:21 PM PDT 24
Peak memory	259836 kb
Host	smart-cca52ebd-7a00-44de-9a8d-d22be4b2c9d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243729623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.4243729623
Directory	/workspace/6.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/6.flash_ctrl_smoke.1638245456
Short name	T458
Test name
Test status
Simulation time	22770100 ps
CPU time	76.02 seconds
Started	Jul 16 05:31:37 PM PDT 24
Finished	Jul 16 05:32:53 PM PDT 24
Peak memory	269924 kb
Host	smart-ea71424d-2131-4de6-b0d4-fd09718ef034
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638245456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.1638245456
Directory	/workspace/6.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.flash_ctrl_wo.3356454399
Short name	T1066
Test name
Test status
Simulation time	4080248700 ps
CPU time	193.16 seconds
Started	Jul 16 05:31:46 PM PDT 24
Finished	Jul 16 05:34:59 PM PDT 24
Peak memory	260720 kb
Host	smart-8caca413-a729-4b05-991c-4a4b25da0ef7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356454399 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.flash_ctrl_wo.3356454399
Directory	/workspace/6.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/60.flash_ctrl_connect.1619363946
Short name	T975
Test name
Test status
Simulation time	101474100 ps
CPU time	16.09 seconds
Started	Jul 16 05:37:18 PM PDT 24
Finished	Jul 16 05:37:34 PM PDT 24
Peak memory	284168 kb
Host	smart-aec5ecbc-44df-46ff-bc0f-9393337f0074
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619363946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.1619363946
Directory	/workspace/60.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/60.flash_ctrl_otp_reset.1275199661
Short name	T174
Test name
Test status
Simulation time	40486900 ps
CPU time	131.45 seconds
Started	Jul 16 05:37:17 PM PDT 24
Finished	Jul 16 05:39:29 PM PDT 24
Peak memory	264672 kb
Host	smart-e1b27ba4-2591-4d57-979f-ee7cc09955fe
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275199661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o tp_reset.1275199661
Directory	/workspace/60.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/61.flash_ctrl_connect.620291771
Short name	T967
Test name
Test status
Simulation time	47909800 ps
CPU time	15.86 seconds
Started	Jul 16 05:37:12 PM PDT 24
Finished	Jul 16 05:37:29 PM PDT 24
Peak memory	284268 kb
Host	smart-9de9f544-1b97-44a8-b0d7-d3d277a9d8b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620291771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.620291771
Directory	/workspace/61.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/61.flash_ctrl_otp_reset.3701167336
Short name	T163
Test name
Test status
Simulation time	79686700 ps
CPU time	109.6 seconds
Started	Jul 16 05:37:20 PM PDT 24
Finished	Jul 16 05:39:10 PM PDT 24
Peak memory	260276 kb
Host	smart-740c4061-ff47-43d5-9221-f48875ad277b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701167336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o tp_reset.3701167336
Directory	/workspace/61.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/62.flash_ctrl_connect.3706991471
Short name	T816
Test name
Test status
Simulation time	25442800 ps
CPU time	16.34 seconds
Started	Jul 16 05:37:16 PM PDT 24
Finished	Jul 16 05:37:33 PM PDT 24
Peak memory	284356 kb
Host	smart-b483f4b0-301a-48ed-9e56-2a02006aca8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3706991471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3706991471
Directory	/workspace/62.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/62.flash_ctrl_otp_reset.1729460393
Short name	T817
Test name
Test status
Simulation time	87822700 ps
CPU time	132.19 seconds
Started	Jul 16 05:37:27 PM PDT 24
Finished	Jul 16 05:39:40 PM PDT 24
Peak memory	260916 kb
Host	smart-a3fb718e-1164-46f1-9a20-f93c74bfadda
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729460393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o tp_reset.1729460393
Directory	/workspace/62.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/63.flash_ctrl_connect.2099532783
Short name	T641
Test name
Test status
Simulation time	16195200 ps
CPU time	13.28 seconds
Started	Jul 16 05:37:16 PM PDT 24
Finished	Jul 16 05:37:30 PM PDT 24
Peak memory	274788 kb
Host	smart-1cb8b6c1-18ae-47a9-b0d2-0796b349ae82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099532783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.2099532783
Directory	/workspace/63.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/63.flash_ctrl_otp_reset.1772584197
Short name	T874
Test name
Test status
Simulation time	231208100 ps
CPU time	131.09 seconds
Started	Jul 16 05:37:16 PM PDT 24
Finished	Jul 16 05:39:28 PM PDT 24
Peak memory	260100 kb
Host	smart-c3052652-6c8e-4bc7-878e-6adfb1a152b5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772584197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o tp_reset.1772584197
Directory	/workspace/63.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/64.flash_ctrl_connect.1721234812
Short name	T1002
Test name
Test status
Simulation time	52334800 ps
CPU time	15.47 seconds
Started	Jul 16 05:37:13 PM PDT 24
Finished	Jul 16 05:37:30 PM PDT 24
Peak memory	274924 kb
Host	smart-f3c35947-a4fa-4ed6-8400-1b82415a06d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1721234812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1721234812
Directory	/workspace/64.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/64.flash_ctrl_otp_reset.579754097
Short name	T1093
Test name
Test status
Simulation time	58541400 ps
CPU time	135.3 seconds
Started	Jul 16 05:37:16 PM PDT 24
Finished	Jul 16 05:39:33 PM PDT 24
Peak memory	265076 kb
Host	smart-163e5a9b-c87a-48db-a053-8b8e48b06dfe
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579754097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_ot p_reset.579754097
Directory	/workspace/64.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/65.flash_ctrl_connect.2677999981
Short name	T724
Test name
Test status
Simulation time	16387200 ps
CPU time	13.31 seconds
Started	Jul 16 05:37:27 PM PDT 24
Finished	Jul 16 05:37:41 PM PDT 24
Peak memory	284348 kb
Host	smart-f9444d81-0391-4a23-9294-254ec518a34a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677999981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2677999981
Directory	/workspace/65.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/65.flash_ctrl_otp_reset.2114474267
Short name	T631
Test name
Test status
Simulation time	78664800 ps
CPU time	107.88 seconds
Started	Jul 16 05:37:17 PM PDT 24
Finished	Jul 16 05:39:06 PM PDT 24
Peak memory	260968 kb
Host	smart-41e0c7bb-5806-4b4c-a140-0ed0e0976503
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114474267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o tp_reset.2114474267
Directory	/workspace/65.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/66.flash_ctrl_connect.2620706142
Short name	T592
Test name
Test status
Simulation time	46700000 ps
CPU time	13.43 seconds
Started	Jul 16 05:37:16 PM PDT 24
Finished	Jul 16 05:37:30 PM PDT 24
Peak memory	274848 kb
Host	smart-5ed29d64-63ea-4ae9-9f47-dbfbfc7d8f7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620706142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2620706142
Directory	/workspace/66.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/66.flash_ctrl_otp_reset.707396569
Short name	T965
Test name
Test status
Simulation time	141511100 ps
CPU time	109.57 seconds
Started	Jul 16 05:37:17 PM PDT 24
Finished	Jul 16 05:39:07 PM PDT 24
Peak memory	264400 kb
Host	smart-78110fe2-f4c5-4ed9-8d9b-ac2d485df1f0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707396569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_ot p_reset.707396569
Directory	/workspace/66.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/67.flash_ctrl_connect.4031521365
Short name	T810
Test name
Test status
Simulation time	73970900 ps
CPU time	15.69 seconds
Started	Jul 16 05:37:15 PM PDT 24
Finished	Jul 16 05:37:31 PM PDT 24
Peak memory	274708 kb
Host	smart-60bcc924-96b3-4052-b465-071c72577bac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031521365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.4031521365
Directory	/workspace/67.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/67.flash_ctrl_otp_reset.3930482864
Short name	T310
Test name
Test status
Simulation time	40307000 ps
CPU time	112.06 seconds
Started	Jul 16 05:37:19 PM PDT 24
Finished	Jul 16 05:39:12 PM PDT 24
Peak memory	260128 kb
Host	smart-04fa8080-973d-4de6-b066-2b27bb0dbe90
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930482864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o tp_reset.3930482864
Directory	/workspace/67.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/68.flash_ctrl_connect.3846429899
Short name	T500
Test name
Test status
Simulation time	16451000 ps
CPU time	13.43 seconds
Started	Jul 16 05:37:26 PM PDT 24
Finished	Jul 16 05:37:40 PM PDT 24
Peak memory	284292 kb
Host	smart-b2b39cae-57df-4fe5-a5dd-9082b34f1ab7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846429899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3846429899
Directory	/workspace/68.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/68.flash_ctrl_otp_reset.2797699399
Short name	T155
Test name
Test status
Simulation time	40491500 ps
CPU time	109.33 seconds
Started	Jul 16 05:37:16 PM PDT 24
Finished	Jul 16 05:39:06 PM PDT 24
Peak memory	260152 kb
Host	smart-d51e5684-6cc8-416a-9674-dde4ebac141a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797699399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o tp_reset.2797699399
Directory	/workspace/68.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/69.flash_ctrl_connect.3891928238
Short name	T417
Test name
Test status
Simulation time	37532100 ps
CPU time	15.58 seconds
Started	Jul 16 05:37:27 PM PDT 24
Finished	Jul 16 05:37:43 PM PDT 24
Peak memory	275064 kb
Host	smart-d5a6d972-b1fc-4ed6-a8f7-4eaa8e6ab433
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891928238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3891928238
Directory	/workspace/69.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/69.flash_ctrl_otp_reset.4063305319
Short name	T614
Test name
Test status
Simulation time	75352400 ps
CPU time	109.66 seconds
Started	Jul 16 05:37:22 PM PDT 24
Finished	Jul 16 05:39:12 PM PDT 24
Peak memory	260044 kb
Host	smart-b7e345b0-9f48-44ca-9514-1ad44dfaf982
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063305319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o tp_reset.4063305319
Directory	/workspace/69.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_alert_test.1778755950
Short name	T115
Test name
Test status
Simulation time	102181600 ps
CPU time	13.8 seconds
Started	Jul 16 05:36:35 PM PDT 24
Finished	Jul 16 05:36:51 PM PDT 24
Peak memory	265224 kb
Host	smart-091a00ba-c23c-4a8d-b65c-8dedb9c8847e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778755950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1 778755950
Directory	/workspace/7.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.flash_ctrl_connect.1597714394
Short name	T890
Test name
Test status
Simulation time	185495800 ps
CPU time	15.99 seconds
Started	Jul 16 05:35:30 PM PDT 24
Finished	Jul 16 05:35:46 PM PDT 24
Peak memory	284368 kb
Host	smart-ff4f61ed-9a2f-43bf-ba9c-c28b00c708e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1597714394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.1597714394
Directory	/workspace/7.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/7.flash_ctrl_disable.1473876873
Short name	T1049
Test name
Test status
Simulation time	26292300 ps
CPU time	21.81 seconds
Started	Jul 16 05:36:34 PM PDT 24
Finished	Jul 16 05:36:57 PM PDT 24
Peak memory	273592 kb
Host	smart-cee52b46-f46d-48a3-adf1-db6070bf9894
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473876873 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_disable.1473876873
Directory	/workspace/7.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_mp.315630076
Short name	T136
Test name
Test status
Simulation time	14049986700 ps
CPU time	2093.71 seconds
Started	Jul 16 05:36:51 PM PDT 24
Finished	Jul 16 06:11:46 PM PDT 24
Peak memory	264772 kb
Host	smart-3e4d860e-a7fc-48e9-82ce-c8cf91abc202
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=315630076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.315630076
Directory	/workspace/7.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_prog_win.1383233111
Short name	T1087
Test name
Test status
Simulation time	432041900 ps
CPU time	862.5 seconds
Started	Jul 16 05:36:39 PM PDT 24
Finished	Jul 16 05:51:03 PM PDT 24
Peak memory	273460 kb
Host	smart-f3882d91-d287-4227-b473-4900227e4f76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1383233111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.1383233111
Directory	/workspace/7.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/7.flash_ctrl_fetch_code.1140354100
Short name	T929
Test name
Test status
Simulation time	213801900 ps
CPU time	20.08 seconds
Started	Jul 16 05:36:25 PM PDT 24
Finished	Jul 16 05:36:46 PM PDT 24
Peak memory	263536 kb
Host	smart-a7bd41b8-b5dc-4408-bb3d-24342fc2d52a
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140354100 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.1140354100
Directory	/workspace/7.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.1038766931
Short name	T164
Test name
Test status
Simulation time	10026839700 ps
CPU time	69.84 seconds
Started	Jul 16 05:32:08 PM PDT 24
Finished	Jul 16 05:33:18 PM PDT 24
Peak memory	300168 kb
Host	smart-21d31945-9da5-4807-af08-465072dfe4a2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038766931 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.1038766931
Directory	/workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.1575973257
Short name	T908
Test name
Test status
Simulation time	15200600 ps
CPU time	13.63 seconds
Started	Jul 16 05:36:33 PM PDT 24
Finished	Jul 16 05:36:47 PM PDT 24
Peak memory	265348 kb
Host	smart-98eceba9-f4cd-463d-ae75-6606584b3c7f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575973257 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.1575973257
Directory	/workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_rma_reset.313584045
Short name	T845
Test name
Test status
Simulation time	40123129200 ps
CPU time	854.03 seconds
Started	Jul 16 05:32:08 PM PDT 24
Finished	Jul 16 05:46:24 PM PDT 24
Peak memory	260844 kb
Host	smart-98f538a5-6da9-4ce8-a9e0-8f67c18f5124
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313584045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.flash_ctrl_hw_rma_reset.313584045
Directory	/workspace/7.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1735114561
Short name	T981
Test name
Test status
Simulation time	2935847000 ps
CPU time	51.49 seconds
Started	Jul 16 05:32:08 PM PDT 24
Finished	Jul 16 05:33:01 PM PDT 24
Peak memory	260856 kb
Host	smart-c83ad1c6-3996-4f9c-b57d-1fa6253d288c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735114561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h w_sec_otp.1735114561
Directory	/workspace/7.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd.200041951
Short name	T546
Test name
Test status
Simulation time	4299247900 ps
CPU time	149.55 seconds
Started	Jul 16 05:36:51 PM PDT 24
Finished	Jul 16 05:39:22 PM PDT 24
Peak memory	291500 kb
Host	smart-df3a7b5f-cf38-44e9-9d4e-89bfca5096eb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200041951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash _ctrl_intr_rd.200041951
Directory	/workspace/7.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1005484493
Short name	T553
Test name
Test status
Simulation time	199126736500 ps
CPU time	330.73 seconds
Started	Jul 16 05:32:08 PM PDT 24
Finished	Jul 16 05:37:39 PM PDT 24
Peak memory	293396 kb
Host	smart-c30fd4b1-e63d-4c8d-9c48-aee8b9df7541
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005484493 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.1005484493
Directory	/workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr.3085515969
Short name	T550
Test name
Test status
Simulation time	1871788800 ps
CPU time	60.03 seconds
Started	Jul 16 05:36:38 PM PDT 24
Finished	Jul 16 05:37:39 PM PDT 24
Peak memory	265312 kb
Host	smart-461adebf-72a0-4c1f-a416-06fff8e7a6e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085515969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.flash_ctrl_intr_wr.3085515969
Directory	/workspace/7.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1696141757
Short name	T497
Test name
Test status
Simulation time	98187063700 ps
CPU time	241.41 seconds
Started	Jul 16 05:32:14 PM PDT 24
Finished	Jul 16 05:36:17 PM PDT 24
Peak memory	265012 kb
Host	smart-99391a4b-7c1c-4a9f-baf3-0e9e7ebcb150
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169 6141757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1696141757
Directory	/workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_invalid_op.530097183
Short name	T74
Test name
Test status
Simulation time	1644053200 ps
CPU time	63.87 seconds
Started	Jul 16 05:32:19 PM PDT 24
Finished	Jul 16 05:33:23 PM PDT 24
Peak memory	262616 kb
Host	smart-e76efdbc-1d7b-41fb-b694-72d0a8042955
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530097183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.530097183
Directory	/workspace/7.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/7.flash_ctrl_lcmgr_intg.3775210355
Short name	T287
Test name
Test status
Simulation time	46774600 ps
CPU time	13.5 seconds
Started	Jul 16 05:32:14 PM PDT 24
Finished	Jul 16 05:32:29 PM PDT 24
Peak memory	259968 kb
Host	smart-7ee31bc4-abdc-49cd-83c1-a7b9d42760df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775210355 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.3775210355
Directory	/workspace/7.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/7.flash_ctrl_mp_regions.1832302659
Short name	T711
Test name
Test status
Simulation time	7983050300 ps
CPU time	139.29 seconds
Started	Jul 16 05:32:08 PM PDT 24
Finished	Jul 16 05:34:29 PM PDT 24
Peak memory	262332 kb
Host	smart-d2414f9e-431f-4a97-b1e7-ce7ae3a87a1e
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832302659 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.1832302659
Directory	/workspace/7.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/7.flash_ctrl_phy_arb.31825165
Short name	T219
Test name
Test status
Simulation time	720780000 ps
CPU time	202.03 seconds
Started	Jul 16 05:31:59 PM PDT 24
Finished	Jul 16 05:35:22 PM PDT 24
Peak memory	263036 kb
Host	smart-64777d00-40ca-4d23-9832-753d19840edd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=31825165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.31825165
Directory	/workspace/7.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/7.flash_ctrl_prog_reset.3733224764
Short name	T917
Test name
Test status
Simulation time	9426708700 ps
CPU time	191 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:40:08 PM PDT 24
Peak memory	260568 kb
Host	smart-0f5fca6d-57f0-45ee-858b-2ecdf431c62f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733224764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.flash_ctrl_prog_reset.3733224764
Directory	/workspace/7.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rand_ops.4132657747
Short name	T700
Test name
Test status
Simulation time	220294800 ps
CPU time	308.72 seconds
Started	Jul 16 05:32:01 PM PDT 24
Finished	Jul 16 05:37:10 PM PDT 24
Peak memory	281596 kb
Host	smart-17b7aa01-995f-41ef-a978-df6236e2e3c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4132657747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.4132657747
Directory	/workspace/7.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/7.flash_ctrl_re_evict.3411619471
Short name	T346
Test name
Test status
Simulation time	122456300 ps
CPU time	33.68 seconds
Started	Jul 16 05:36:36 PM PDT 24
Finished	Jul 16 05:37:11 PM PDT 24
Peak memory	270040 kb
Host	smart-9f52ec9e-4986-437e-830c-a5ee48463149
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411619471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_re_evict.3411619471
Directory	/workspace/7.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro.85087328
Short name	T737
Test name
Test status
Simulation time	4276182600 ps
CPU time	122.87 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:38:59 PM PDT 24
Peak memory	281808 kb
Host	smart-dc227482-8bd8-4dad-8985-ed4120037926
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85087328 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.flash_ctrl_ro.85087328
Directory	/workspace/7.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_derr.2991299367
Short name	T942
Test name
Test status
Simulation time	1057447400 ps
CPU time	139.06 seconds
Started	Jul 16 05:36:51 PM PDT 24
Finished	Jul 16 05:39:11 PM PDT 24
Peak memory	281920 kb
Host	smart-6002cb46-d03b-4d68-87c4-6d55ca604de4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2991299367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.2991299367
Directory	/workspace/7.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_serr.582229549
Short name	T274
Test name
Test status
Simulation time	600256100 ps
CPU time	150.06 seconds
Started	Jul 16 05:32:14 PM PDT 24
Finished	Jul 16 05:34:45 PM PDT 24
Peak memory	281752 kb
Host	smart-1b527026-0b0a-42f4-9de9-24936071bb35
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582229549 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.582229549
Directory	/workspace/7.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw.450272800
Short name	T930
Test name
Test status
Simulation time	12528526700 ps
CPU time	554.65 seconds
Started	Jul 16 05:32:19 PM PDT 24
Finished	Jul 16 05:41:34 PM PDT 24
Peak memory	318620 kb
Host	smart-55a5efa9-d2c9-4837-a5ca-a1e94f255ef8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450272800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.450272800
Directory	/workspace/7.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_derr.3013731484
Short name	T705
Test name
Test status
Simulation time	15469321700 ps
CPU time	633.25 seconds
Started	Jul 16 05:32:07 PM PDT 24
Finished	Jul 16 05:42:41 PM PDT 24
Peak memory	336692 kb
Host	smart-fbf7126c-d164-4c95-bc45-44ba67d1630c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013731484 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_rw_derr.3013731484
Directory	/workspace/7.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict.3946062917
Short name	T634
Test name
Test status
Simulation time	35109600 ps
CPU time	31.65 seconds
Started	Jul 16 05:32:14 PM PDT 24
Finished	Jul 16 05:32:46 PM PDT 24
Peak memory	275584 kb
Host	smart-de280660-0277-4a73-8f9f-98e6f1a564a5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946062917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_rw_evict.3946062917
Directory	/workspace/7.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.2354091905
Short name	T859
Test name
Test status
Simulation time	41070400 ps
CPU time	30.94 seconds
Started	Jul 16 05:32:14 PM PDT 24
Finished	Jul 16 05:32:46 PM PDT 24
Peak memory	275584 kb
Host	smart-3537ed19-c9e1-41f9-95e9-74e8675a0582
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354091905 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.2354091905
Directory	/workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_serr.3703765550
Short name	T89
Test name
Test status
Simulation time	4063080800 ps
CPU time	592.04 seconds
Started	Jul 16 05:36:33 PM PDT 24
Finished	Jul 16 05:46:26 PM PDT 24
Peak memory	313028 kb
Host	smart-3afd1b16-083f-4263-b68d-e1c0ae8cc084
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703765550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s err.3703765550
Directory	/workspace/7.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_sec_info_access.3890136289
Short name	T399
Test name
Test status
Simulation time	2440891600 ps
CPU time	65.11 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:38:02 PM PDT 24
Peak memory	263672 kb
Host	smart-b4e1cb33-acd8-4f7e-bd1d-6394b9a4d264
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3890136289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3890136289
Directory	/workspace/7.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/7.flash_ctrl_smoke.30032715
Short name	T562
Test name
Test status
Simulation time	60413300 ps
CPU time	94.9 seconds
Started	Jul 16 05:35:30 PM PDT 24
Finished	Jul 16 05:37:05 PM PDT 24
Peak memory	276312 kb
Host	smart-3e40f913-430a-499e-9698-4b8ba3bee756
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30032715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.30032715
Directory	/workspace/7.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.flash_ctrl_wo.1575164280
Short name	T624
Test name
Test status
Simulation time	18268000800 ps
CPU time	173.12 seconds
Started	Jul 16 05:36:39 PM PDT 24
Finished	Jul 16 05:39:33 PM PDT 24
Peak memory	265224 kb
Host	smart-f5f4f55e-22b1-4816-a2f5-ee8ad105bba3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575164280 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.flash_ctrl_wo.1575164280
Directory	/workspace/7.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/70.flash_ctrl_connect.809336219
Short name	T851
Test name
Test status
Simulation time	203937400 ps
CPU time	13.41 seconds
Started	Jul 16 05:37:24 PM PDT 24
Finished	Jul 16 05:37:39 PM PDT 24
Peak memory	274732 kb
Host	smart-1dc57647-74c4-495a-9520-746d898e45d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809336219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.809336219
Directory	/workspace/70.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/70.flash_ctrl_otp_reset.1620508246
Short name	T467
Test name
Test status
Simulation time	106238200 ps
CPU time	134.17 seconds
Started	Jul 16 05:37:25 PM PDT 24
Finished	Jul 16 05:39:40 PM PDT 24
Peak memory	264980 kb
Host	smart-02346774-bb0b-433c-8589-c9696527caf3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620508246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o tp_reset.1620508246
Directory	/workspace/70.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/71.flash_ctrl_connect.432979105
Short name	T464
Test name
Test status
Simulation time	31259300 ps
CPU time	16.25 seconds
Started	Jul 16 05:37:24 PM PDT 24
Finished	Jul 16 05:37:41 PM PDT 24
Peak memory	274884 kb
Host	smart-84043ebd-32de-446f-a34d-44b279323570
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=432979105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.432979105
Directory	/workspace/71.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/71.flash_ctrl_otp_reset.4276204608
Short name	T316
Test name
Test status
Simulation time	53777900 ps
CPU time	131.16 seconds
Started	Jul 16 05:37:25 PM PDT 24
Finished	Jul 16 05:39:37 PM PDT 24
Peak memory	260276 kb
Host	smart-26637e8e-cc53-40cb-a20a-4e84ba96031a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276204608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o tp_reset.4276204608
Directory	/workspace/71.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/72.flash_ctrl_connect.1066944192
Short name	T834
Test name
Test status
Simulation time	17090700 ps
CPU time	16.28 seconds
Started	Jul 16 05:37:26 PM PDT 24
Finished	Jul 16 05:37:43 PM PDT 24
Peak memory	274812 kb
Host	smart-c4d94ef9-02f7-478c-bd4d-a1c3514b2bbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066944192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1066944192
Directory	/workspace/72.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/72.flash_ctrl_otp_reset.2919529218
Short name	T110
Test name
Test status
Simulation time	150212100 ps
CPU time	135.43 seconds
Started	Jul 16 05:37:30 PM PDT 24
Finished	Jul 16 05:39:46 PM PDT 24
Peak memory	260096 kb
Host	smart-3e6ccc7f-99bc-4015-bde4-31584d8592c3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919529218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o tp_reset.2919529218
Directory	/workspace/72.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/73.flash_ctrl_connect.2906873589
Short name	T886
Test name
Test status
Simulation time	15907900 ps
CPU time	16.25 seconds
Started	Jul 16 05:37:30 PM PDT 24
Finished	Jul 16 05:37:47 PM PDT 24
Peak memory	284232 kb
Host	smart-67e8831f-d838-401f-9d7a-d20a3f1fd62a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2906873589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.2906873589
Directory	/workspace/73.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/73.flash_ctrl_otp_reset.4278029784
Short name	T760
Test name
Test status
Simulation time	39627100 ps
CPU time	110.07 seconds
Started	Jul 16 05:37:27 PM PDT 24
Finished	Jul 16 05:39:18 PM PDT 24
Peak memory	264296 kb
Host	smart-cd80a817-aa77-4679-bb64-9304e0cc1f5e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278029784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o tp_reset.4278029784
Directory	/workspace/73.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/74.flash_ctrl_connect.3634201079
Short name	T722
Test name
Test status
Simulation time	30289200 ps
CPU time	16.13 seconds
Started	Jul 16 05:37:25 PM PDT 24
Finished	Jul 16 05:37:42 PM PDT 24
Peak memory	274828 kb
Host	smart-ff7bace6-2038-44e1-8600-8154ed2bc33b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3634201079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.3634201079
Directory	/workspace/74.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/74.flash_ctrl_otp_reset.284524336
Short name	T494
Test name
Test status
Simulation time	144115400 ps
CPU time	132.02 seconds
Started	Jul 16 05:37:25 PM PDT 24
Finished	Jul 16 05:39:38 PM PDT 24
Peak memory	264264 kb
Host	smart-29d12f8f-95dd-4fc5-ad66-9c84085bd37e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284524336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_ot p_reset.284524336
Directory	/workspace/74.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/75.flash_ctrl_connect.3812013105
Short name	T428
Test name
Test status
Simulation time	21831900 ps
CPU time	15.79 seconds
Started	Jul 16 05:37:34 PM PDT 24
Finished	Jul 16 05:37:51 PM PDT 24
Peak memory	274844 kb
Host	smart-1ad33f8f-3b72-4c0a-be55-f6a04757586d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3812013105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.3812013105
Directory	/workspace/75.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/75.flash_ctrl_otp_reset.1327419842
Short name	T665
Test name
Test status
Simulation time	44305300 ps
CPU time	132.78 seconds
Started	Jul 16 05:37:27 PM PDT 24
Finished	Jul 16 05:39:41 PM PDT 24
Peak memory	260984 kb
Host	smart-7dcb0d91-28f4-4075-9203-954b7e84ffdd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327419842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o tp_reset.1327419842
Directory	/workspace/75.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/76.flash_ctrl_connect.53638268
Short name	T1042
Test name
Test status
Simulation time	56579800 ps
CPU time	15.82 seconds
Started	Jul 16 05:37:27 PM PDT 24
Finished	Jul 16 05:37:44 PM PDT 24
Peak memory	284392 kb
Host	smart-41c03b36-b81b-46e8-a803-ca16a7a01482
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=53638268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.53638268
Directory	/workspace/76.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/76.flash_ctrl_otp_reset.2735569398
Short name	T63
Test name
Test status
Simulation time	42544600 ps
CPU time	133.14 seconds
Started	Jul 16 05:37:23 PM PDT 24
Finished	Jul 16 05:39:37 PM PDT 24
Peak memory	261048 kb
Host	smart-54f7d702-285c-404f-b4b0-a65603b9aeb4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735569398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o tp_reset.2735569398
Directory	/workspace/76.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/77.flash_ctrl_connect.825483579
Short name	T1065
Test name
Test status
Simulation time	97414900 ps
CPU time	16.15 seconds
Started	Jul 16 05:37:24 PM PDT 24
Finished	Jul 16 05:37:41 PM PDT 24
Peak memory	274948 kb
Host	smart-61d871dc-b9f3-4189-9f42-17b737fd3732
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825483579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.825483579
Directory	/workspace/77.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/77.flash_ctrl_otp_reset.2703316375
Short name	T512
Test name
Test status
Simulation time	84140300 ps
CPU time	130.56 seconds
Started	Jul 16 05:37:25 PM PDT 24
Finished	Jul 16 05:39:36 PM PDT 24
Peak memory	265056 kb
Host	smart-8d995dac-d6a4-4e1f-a990-fc9c0f01d520
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703316375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o tp_reset.2703316375
Directory	/workspace/77.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/78.flash_ctrl_connect.2256365635
Short name	T944
Test name
Test status
Simulation time	76107300 ps
CPU time	16.08 seconds
Started	Jul 16 05:37:29 PM PDT 24
Finished	Jul 16 05:37:46 PM PDT 24
Peak memory	274972 kb
Host	smart-377f980d-cc88-4363-bb52-29a7d28c405e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2256365635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.2256365635
Directory	/workspace/78.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/78.flash_ctrl_otp_reset.2959877123
Short name	T17
Test name
Test status
Simulation time	133393900 ps
CPU time	110.32 seconds
Started	Jul 16 05:37:29 PM PDT 24
Finished	Jul 16 05:39:20 PM PDT 24
Peak memory	260988 kb
Host	smart-db7e4e4d-42fc-41db-8ae9-d48287f8d421
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959877123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o tp_reset.2959877123
Directory	/workspace/78.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/79.flash_ctrl_connect.645483332
Short name	T442
Test name
Test status
Simulation time	48039200 ps
CPU time	15.95 seconds
Started	Jul 16 05:37:31 PM PDT 24
Finished	Jul 16 05:37:48 PM PDT 24
Peak memory	274892 kb
Host	smart-1c60b142-f469-45b5-b50b-9403e48476cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645483332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.645483332
Directory	/workspace/79.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/79.flash_ctrl_otp_reset.2999923477
Short name	T320
Test name
Test status
Simulation time	39565900 ps
CPU time	135.88 seconds
Started	Jul 16 05:37:33 PM PDT 24
Finished	Jul 16 05:39:49 PM PDT 24
Peak memory	261084 kb
Host	smart-77f4f636-e5d1-4fc7-9949-f9a221617f76
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999923477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o tp_reset.2999923477
Directory	/workspace/79.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_alert_test.1568310250
Short name	T838
Test name
Test status
Simulation time	87535100 ps
CPU time	13.66 seconds
Started	Jul 16 05:32:19 PM PDT 24
Finished	Jul 16 05:32:34 PM PDT 24
Peak memory	258168 kb
Host	smart-74e2e157-5604-45bf-bd5a-a4b4cdc07ae6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568310250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.1 568310250
Directory	/workspace/8.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.flash_ctrl_connect.3993624349
Short name	T451
Test name
Test status
Simulation time	91012000 ps
CPU time	15.59 seconds
Started	Jul 16 05:32:19 PM PDT 24
Finished	Jul 16 05:32:36 PM PDT 24
Peak memory	274740 kb
Host	smart-536124a4-759b-4d54-8d05-0e86457d9c56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993624349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3993624349
Directory	/workspace/8.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/8.flash_ctrl_disable.2223377692
Short name	T606
Test name
Test status
Simulation time	16779200 ps
CPU time	20.51 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:37:18 PM PDT 24
Peak memory	266404 kb
Host	smart-989d567b-223d-4104-af71-49c732737024
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223377692 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_disable.2223377692
Directory	/workspace/8.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_mp.2627172631
Short name	T795
Test name
Test status
Simulation time	10883167900 ps
CPU time	2194.64 seconds
Started	Jul 16 05:32:09 PM PDT 24
Finished	Jul 16 06:08:44 PM PDT 24
Peak memory	264824 kb
Host	smart-5acaa4cd-772d-4460-a706-45bcb0a1f87a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2627172631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.2627172631
Directory	/workspace/8.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_prog_win.1348830994
Short name	T881
Test name
Test status
Simulation time	1489049000 ps
CPU time	912 seconds
Started	Jul 16 05:32:17 PM PDT 24
Finished	Jul 16 05:47:29 PM PDT 24
Peak memory	273460 kb
Host	smart-5cd8642f-ac29-4c5c-a276-d3962e7cbe98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348830994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.1348830994
Directory	/workspace/8.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/8.flash_ctrl_fetch_code.1842735653
Short name	T44
Test name
Test status
Simulation time	342953700 ps
CPU time	23.94 seconds
Started	Jul 16 05:32:08 PM PDT 24
Finished	Jul 16 05:32:32 PM PDT 24
Peak memory	262512 kb
Host	smart-e2828221-11c5-4eee-9a0f-a0826b959b41
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842735653 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.1842735653
Directory	/workspace/8.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3939609567
Short name	T427
Test name
Test status
Simulation time	10018685200 ps
CPU time	87.33 seconds
Started	Jul 16 05:32:16 PM PDT 24
Finished	Jul 16 05:33:44 PM PDT 24
Peak memory	327260 kb
Host	smart-d691fe04-807d-4101-b2c4-4b71f4868f7a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939609567 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3939609567
Directory	/workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3745741179
Short name	T1102
Test name
Test status
Simulation time	26357600 ps
CPU time	13.12 seconds
Started	Jul 16 05:32:19 PM PDT 24
Finished	Jul 16 05:32:33 PM PDT 24
Peak memory	265300 kb
Host	smart-e617de8d-3a0b-4e44-8edb-522b284d1fe4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745741179 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3745741179
Directory	/workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.4058013515
Short name	T756
Test name
Test status
Simulation time	80135045100 ps
CPU time	882.87 seconds
Started	Jul 16 05:36:51 PM PDT 24
Finished	Jul 16 05:51:36 PM PDT 24
Peak memory	264388 kb
Host	smart-cee5173a-ba3b-4976-8de6-06108b881d30
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058013515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.flash_ctrl_hw_rma_reset.4058013515
Directory	/workspace/8.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_sec_otp.1469827942
Short name	T529
Test name
Test status
Simulation time	5357554700 ps
CPU time	41.62 seconds
Started	Jul 16 05:32:11 PM PDT 24
Finished	Jul 16 05:32:54 PM PDT 24
Peak memory	262968 kb
Host	smart-4408c849-1c8c-4a7a-9290-f2235de91b12
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469827942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h w_sec_otp.1469827942
Directory	/workspace/8.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2828441160
Short name	T477
Test name
Test status
Simulation time	18110261300 ps
CPU time	188.42 seconds
Started	Jul 16 05:36:53 PM PDT 24
Finished	Jul 16 05:40:02 PM PDT 24
Peak memory	292972 kb
Host	smart-eb1facde-c023-4729-a03d-8c3ec9b9ee7a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828441160 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.2828441160
Directory	/workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr.3828030495
Short name	T528
Test name
Test status
Simulation time	9509451300 ps
CPU time	58.81 seconds
Started	Jul 16 05:32:15 PM PDT 24
Finished	Jul 16 05:33:14 PM PDT 24
Peak memory	260576 kb
Host	smart-b7b920b5-1fe9-4f25-9e1f-753cd205de13
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828030495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.flash_ctrl_intr_wr.3828030495
Directory	/workspace/8.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.3222218178
Short name	T27
Test name
Test status
Simulation time	71510301600 ps
CPU time	221.69 seconds
Started	Jul 16 05:36:39 PM PDT 24
Finished	Jul 16 05:40:22 PM PDT 24
Peak memory	260312 kb
Host	smart-4470f4c4-d2c1-43eb-b81d-72da10942fb4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322 2218178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.3222218178
Directory	/workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_invalid_op.74146324
Short name	T836
Test name
Test status
Simulation time	7578061700 ps
CPU time	66.75 seconds
Started	Jul 16 05:40:46 PM PDT 24
Finished	Jul 16 05:41:54 PM PDT 24
Peak memory	263632 kb
Host	smart-0805f612-cab3-45ff-a661-851dfdad0933
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74146324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.74146324
Directory	/workspace/8.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/8.flash_ctrl_lcmgr_intg.4158473101
Short name	T1109
Test name
Test status
Simulation time	19795800 ps
CPU time	13.4 seconds
Started	Jul 16 05:36:53 PM PDT 24
Finished	Jul 16 05:37:07 PM PDT 24
Peak memory	264928 kb
Host	smart-c2b1ac14-bdd0-4712-8c75-d322e8f493b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158473101 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.4158473101
Directory	/workspace/8.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/8.flash_ctrl_mp_regions.2218509466
Short name	T118
Test name
Test status
Simulation time	37925788400 ps
CPU time	757.43 seconds
Started	Jul 16 05:32:14 PM PDT 24
Finished	Jul 16 05:44:53 PM PDT 24
Peak memory	274484 kb
Host	smart-120f6f0b-3ece-41f5-a448-f5ed3c6e8bdd
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218509466 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.2218509466
Directory	/workspace/8.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/8.flash_ctrl_otp_reset.2778551597
Short name	T911
Test name
Test status
Simulation time	35749300 ps
CPU time	132.56 seconds
Started	Jul 16 05:36:35 PM PDT 24
Finished	Jul 16 05:38:49 PM PDT 24
Peak memory	260264 kb
Host	smart-55b78f43-1e3f-473e-bcbb-bdea34636801
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778551597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot p_reset.2778551597
Directory	/workspace/8.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_phy_arb.1492946594
Short name	T696
Test name
Test status
Simulation time	1472612100 ps
CPU time	473.71 seconds
Started	Jul 16 05:32:11 PM PDT 24
Finished	Jul 16 05:40:06 PM PDT 24
Peak memory	263124 kb
Host	smart-ee32bc60-5768-423b-aab6-d708a60ef78b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1492946594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.1492946594
Directory	/workspace/8.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/8.flash_ctrl_prog_reset.1506957829
Short name	T511
Test name
Test status
Simulation time	575987800 ps
CPU time	24.52 seconds
Started	Jul 16 05:32:18 PM PDT 24
Finished	Jul 16 05:32:43 PM PDT 24
Peak memory	265216 kb
Host	smart-1ddc589a-4140-4608-98a7-27790a321f96
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506957829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.flash_ctrl_prog_reset.1506957829
Directory	/workspace/8.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rand_ops.3974090314
Short name	T1088
Test name
Test status
Simulation time	71857900 ps
CPU time	194.88 seconds
Started	Jul 16 05:36:33 PM PDT 24
Finished	Jul 16 05:39:49 PM PDT 24
Peak memory	277408 kb
Host	smart-42ae03bf-eb42-45c9-9f9c-6b52fd41ab4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974090314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3974090314
Directory	/workspace/8.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/8.flash_ctrl_re_evict.1105710805
Short name	T995
Test name
Test status
Simulation time	120072400 ps
CPU time	31.96 seconds
Started	Jul 16 05:36:39 PM PDT 24
Finished	Jul 16 05:37:12 PM PDT 24
Peak memory	275648 kb
Host	smart-f485b3e7-858a-4e51-a863-d5d2958ebe52
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105710805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_re_evict.1105710805
Directory	/workspace/8.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro.3461593177
Short name	T314
Test name
Test status
Simulation time	557228500 ps
CPU time	125.86 seconds
Started	Jul 16 05:32:18 PM PDT 24
Finished	Jul 16 05:34:25 PM PDT 24
Peak memory	291284 kb
Host	smart-40636b12-017c-4824-9533-b7e120e6d586
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461593177 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_ro.3461593177
Directory	/workspace/8.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_derr.539160552
Short name	T985
Test name
Test status
Simulation time	2921773600 ps
CPU time	175.2 seconds
Started	Jul 16 05:32:16 PM PDT 24
Finished	Jul 16 05:35:12 PM PDT 24
Peak memory	283052 kb
Host	smart-1dfc43b1-7411-4be5-8d30-3483390ead74
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 539160552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.539160552
Directory	/workspace/8.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_serr.4191724983
Short name	T554
Test name
Test status
Simulation time	2745763500 ps
CPU time	143.83 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:39:20 PM PDT 24
Peak memory	290212 kb
Host	smart-f6dfce37-aca3-4e62-8505-cefe3ad4b61a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191724983 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.4191724983
Directory	/workspace/8.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw.2177305747
Short name	T689
Test name
Test status
Simulation time	4036072800 ps
CPU time	600.02 seconds
Started	Jul 16 05:32:13 PM PDT 24
Finished	Jul 16 05:42:14 PM PDT 24
Peak memory	309864 kb
Host	smart-5582c912-d5c0-4a5e-81e2-c44a9bbdccc8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177305747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.flash_ctrl_rw.2177305747
Directory	/workspace/8.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_derr.3220061092
Short name	T6
Test name
Test status
Simulation time	17899559200 ps
CPU time	632.69 seconds
Started	Jul 16 05:32:19 PM PDT 24
Finished	Jul 16 05:42:52 PM PDT 24
Peak memory	338676 kb
Host	smart-94d66430-4922-4a52-a24c-7da0c11f0242
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220061092 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_rw_derr.3220061092
Directory	/workspace/8.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict.801909703
Short name	T570
Test name
Test status
Simulation time	30304400 ps
CPU time	30.7 seconds
Started	Jul 16 05:32:19 PM PDT 24
Finished	Jul 16 05:32:51 PM PDT 24
Peak memory	268484 kb
Host	smart-6e2cbe58-b6df-481f-bf21-855b705d7043
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801909703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_rw_evict.801909703
Directory	/workspace/8.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.3372018191
Short name	T525
Test name
Test status
Simulation time	40758500 ps
CPU time	30.6 seconds
Started	Jul 16 05:36:52 PM PDT 24
Finished	Jul 16 05:37:23 PM PDT 24
Peak memory	275620 kb
Host	smart-373574ba-fe33-412c-bba9-30b6fa0ecc05
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372018191 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.3372018191
Directory	/workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_serr.4229962642
Short name	T613
Test name
Test status
Simulation time	4415919600 ps
CPU time	485 seconds
Started	Jul 16 05:32:15 PM PDT 24
Finished	Jul 16 05:40:21 PM PDT 24
Peak memory	312336 kb
Host	smart-44e9843a-f336-495d-ac1a-ca42f068c32d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229962642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s err.4229962642
Directory	/workspace/8.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_sec_info_access.1429464895
Short name	T405
Test name
Test status
Simulation time	1483470400 ps
CPU time	66.47 seconds
Started	Jul 16 05:32:19 PM PDT 24
Finished	Jul 16 05:33:26 PM PDT 24
Peak memory	264904 kb
Host	smart-ef050659-2d8b-4e9e-98c4-34aceae7f07d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1429464895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1429464895
Directory	/workspace/8.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/8.flash_ctrl_smoke.1340318929
Short name	T127
Test name
Test status
Simulation time	73325200 ps
CPU time	146.61 seconds
Started	Jul 16 05:36:14 PM PDT 24
Finished	Jul 16 05:38:41 PM PDT 24
Peak memory	276820 kb
Host	smart-96060b19-7c45-4bec-ad76-b512faff3167
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340318929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1340318929
Directory	/workspace/8.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.flash_ctrl_wo.589853936
Short name	T685
Test name
Test status
Simulation time	1692283500 ps
CPU time	146.55 seconds
Started	Jul 16 05:36:28 PM PDT 24
Finished	Jul 16 05:38:55 PM PDT 24
Peak memory	259988 kb
Host	smart-8a2380ef-a7f5-4228-a172-842a4c24e33a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589853936 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 8.flash_ctrl_wo.589853936
Directory	/workspace/8.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/9.flash_ctrl_alert_test.14108304
Short name	T640
Test name
Test status
Simulation time	169714300 ps
CPU time	13.55 seconds
Started	Jul 16 05:36:14 PM PDT 24
Finished	Jul 16 05:36:28 PM PDT 24
Peak memory	265156 kb
Host	smart-6cde8c96-988c-4e7b-bf81-fe71e90eb26e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14108304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.14108304
Directory	/workspace/9.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.flash_ctrl_connect.2017881878
Short name	T534
Test name
Test status
Simulation time	15223500 ps
CPU time	15.97 seconds
Started	Jul 16 05:36:16 PM PDT 24
Finished	Jul 16 05:36:33 PM PDT 24
Peak memory	284292 kb
Host	smart-6f5f24b3-7a36-47fb-a33f-dbafcdede336
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2017881878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.2017881878
Directory	/workspace/9.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/9.flash_ctrl_disable.1337163613
Short name	T923
Test name
Test status
Simulation time	12301800 ps
CPU time	21.81 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:37:18 PM PDT 24
Peak memory	273524 kb
Host	smart-a0f041c5-f8af-4528-ae0a-e58c0b62abd9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337163613 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_disable.1337163613
Directory	/workspace/9.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_mp.761102512
Short name	T999
Test name
Test status
Simulation time	42553210100 ps
CPU time	2211.06 seconds
Started	Jul 16 05:32:28 PM PDT 24
Finished	Jul 16 06:09:19 PM PDT 24
Peak memory	264764 kb
Host	smart-5bb70562-4e78-4a1f-aa13-3136352f0717
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=761102512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.761102512
Directory	/workspace/9.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_prog_win.3481333444
Short name	T292
Test name
Test status
Simulation time	2701050700 ps
CPU time	920.44 seconds
Started	Jul 16 05:32:28 PM PDT 24
Finished	Jul 16 05:47:50 PM PDT 24
Peak memory	270512 kb
Host	smart-9e3707f6-0549-41d9-b30f-ad02b34a1529
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481333444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.3481333444
Directory	/workspace/9.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/9.flash_ctrl_fetch_code.4225057523
Short name	T846
Test name
Test status
Simulation time	304659300 ps
CPU time	21.17 seconds
Started	Jul 16 05:32:26 PM PDT 24
Finished	Jul 16 05:32:48 PM PDT 24
Peak memory	263724 kb
Host	smart-48e58903-0e07-4325-b44b-3460719ab625
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225057523 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.4225057523
Directory	/workspace/9.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1444531802
Short name	T473
Test name
Test status
Simulation time	10015981100 ps
CPU time	107.05 seconds
Started	Jul 16 05:35:30 PM PDT 24
Finished	Jul 16 05:37:17 PM PDT 24
Peak memory	351228 kb
Host	smart-a5393174-3357-41b0-8349-c35daabfa9be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444531802 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.1444531802
Directory	/workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.467406709
Short name	T841
Test name
Test status
Simulation time	15348000 ps
CPU time	13.15 seconds
Started	Jul 16 05:32:35 PM PDT 24
Finished	Jul 16 05:32:49 PM PDT 24
Peak memory	260268 kb
Host	smart-c386692e-9508-4bf2-a6ec-c1e6cb74abad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467406709 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.467406709
Directory	/workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_rma_reset.356641958
Short name	T1117
Test name
Test status
Simulation time	160194708800 ps
CPU time	908.94 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:52:04 PM PDT 24
Peak memory	262160 kb
Host	smart-ba744950-27f3-465f-846c-4ca0e552ad2b
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356641958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.flash_ctrl_hw_rma_reset.356641958
Directory	/workspace/9.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1957622610
Short name	T882
Test name
Test status
Simulation time	1923751700 ps
CPU time	69.5 seconds
Started	Jul 16 05:32:28 PM PDT 24
Finished	Jul 16 05:33:38 PM PDT 24
Peak memory	261040 kb
Host	smart-57d47e8d-250a-4af3-a8f1-d51b3df0d283
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957622610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h w_sec_otp.1957622610
Directory	/workspace/9.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd.617680084
Short name	T574
Test name
Test status
Simulation time	1638011400 ps
CPU time	199.5 seconds
Started	Jul 16 05:34:21 PM PDT 24
Finished	Jul 16 05:37:41 PM PDT 24
Peak memory	291516 kb
Host	smart-0577a77f-2979-44d1-ad39-c1ddc182dd84
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617680084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash _ctrl_intr_rd.617680084
Directory	/workspace/9.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.344703435
Short name	T625
Test name
Test status
Simulation time	23501316900 ps
CPU time	134.78 seconds
Started	Jul 16 05:33:01 PM PDT 24
Finished	Jul 16 05:35:16 PM PDT 24
Peak memory	293100 kb
Host	smart-fef62bf0-ed82-41c1-a0e0-b176cada456a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344703435 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.344703435
Directory	/workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr.3768003874
Short name	T1031
Test name
Test status
Simulation time	3897583500 ps
CPU time	64 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:37:59 PM PDT 24
Peak memory	259876 kb
Host	smart-c882f1b3-c13b-4af3-befc-f5462efd9871
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768003874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_intr_wr.3768003874
Directory	/workspace/9.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1617110935
Short name	T690
Test name
Test status
Simulation time	27357948200 ps
CPU time	212.92 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:40:30 PM PDT 24
Peak memory	260464 kb
Host	smart-b990d4ef-b8f1-43f1-8217-9505673586d8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161 7110935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.1617110935
Directory	/workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_invalid_op.2879984400
Short name	T207
Test name
Test status
Simulation time	2338141100 ps
CPU time	66.64 seconds
Started	Jul 16 05:32:28 PM PDT 24
Finished	Jul 16 05:33:35 PM PDT 24
Peak memory	263332 kb
Host	smart-fcfbbc3a-0ba3-45fb-9a8d-9047b1b4a860
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879984400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2879984400
Directory	/workspace/9.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1577847502
Short name	T860
Test name
Test status
Simulation time	15414200 ps
CPU time	13.62 seconds
Started	Jul 16 05:32:24 PM PDT 24
Finished	Jul 16 05:32:38 PM PDT 24
Peak memory	264872 kb
Host	smart-5b6abe90-2a24-419a-81a7-bc610f5c695d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577847502 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1577847502
Directory	/workspace/9.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/9.flash_ctrl_mp_regions.2052679293
Short name	T598
Test name
Test status
Simulation time	4157827100 ps
CPU time	116.34 seconds
Started	Jul 16 05:32:28 PM PDT 24
Finished	Jul 16 05:34:26 PM PDT 24
Peak memory	263716 kb
Host	smart-3f3fb957-1bf0-4698-99a9-7d7db750d509
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052679293 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.2052679293
Directory	/workspace/9.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/9.flash_ctrl_otp_reset.2383194228
Short name	T648
Test name
Test status
Simulation time	65429100 ps
CPU time	133.88 seconds
Started	Jul 16 05:36:56 PM PDT 24
Finished	Jul 16 05:39:12 PM PDT 24
Peak memory	260112 kb
Host	smart-c7c6e3d8-85ad-42f9-b97e-155629a1e403
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383194228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot p_reset.2383194228
Directory	/workspace/9.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_phy_arb.450784772
Short name	T5
Test name
Test status
Simulation time	8872023100 ps
CPU time	336.88 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:42:34 PM PDT 24
Peak memory	263284 kb
Host	smart-5b60d416-0e78-489b-b3dd-c0e6a2cbb7b4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=450784772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.450784772
Directory	/workspace/9.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/9.flash_ctrl_prog_reset.631365396
Short name	T673
Test name
Test status
Simulation time	41756800 ps
CPU time	14.76 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:37:10 PM PDT 24
Peak memory	259660 kb
Host	smart-69766b59-a1e6-4862-9f06-1e88a70f4c75
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631365396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.flash_ctrl_prog_reset.631365396
Directory	/workspace/9.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rand_ops.857765181
Short name	T38
Test name
Test status
Simulation time	115998600 ps
CPU time	612.95 seconds
Started	Jul 16 05:36:37 PM PDT 24
Finished	Jul 16 05:46:51 PM PDT 24
Peak memory	283816 kb
Host	smart-ac9aa06c-3100-4928-8b10-668e4448ca15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=857765181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.857765181
Directory	/workspace/9.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/9.flash_ctrl_re_evict.4042252389
Short name	T774
Test name
Test status
Simulation time	531144200 ps
CPU time	31.7 seconds
Started	Jul 16 05:32:28 PM PDT 24
Finished	Jul 16 05:33:01 PM PDT 24
Peak memory	268548 kb
Host	smart-1218c1f6-0fd4-49ea-8907-b99040fc0a73
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042252389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_re_evict.4042252389
Directory	/workspace/9.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro.3090478580
Short name	T994
Test name
Test status
Simulation time	551521600 ps
CPU time	138.27 seconds
Started	Jul 16 05:38:01 PM PDT 24
Finished	Jul 16 05:40:20 PM PDT 24
Peak memory	289136 kb
Host	smart-f8aa6a0b-4b5b-4d7f-9a7c-623cef3e8526
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090478580 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_ro.3090478580
Directory	/workspace/9.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_derr.3836137634
Short name	T922
Test name
Test status
Simulation time	2290049900 ps
CPU time	161.64 seconds
Started	Jul 16 05:32:28 PM PDT 24
Finished	Jul 16 05:35:10 PM PDT 24
Peak memory	283000 kb
Host	smart-c7b4b667-c2dc-4757-a0b9-d0dffab4bed0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3836137634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.3836137634
Directory	/workspace/9.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_serr.1012108119
Short name	T1024
Test name
Test status
Simulation time	9145747700 ps
CPU time	129.01 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:39:05 PM PDT 24
Peak memory	294788 kb
Host	smart-7b2ded12-c92b-4595-8fdb-38886e368467
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012108119 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1012108119
Directory	/workspace/9.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw.1759271335
Short name	T83
Test name
Test status
Simulation time	8145070300 ps
CPU time	564.1 seconds
Started	Jul 16 05:32:29 PM PDT 24
Finished	Jul 16 05:41:55 PM PDT 24
Peak memory	314432 kb
Host	smart-e662132f-658f-45a6-a941-39a969906cd5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759271335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.flash_ctrl_rw.1759271335
Directory	/workspace/9.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_derr.4121979090
Short name	T21
Test name
Test status
Simulation time	8782374800 ps
CPU time	651.11 seconds
Started	Jul 16 05:32:26 PM PDT 24
Finished	Jul 16 05:43:18 PM PDT 24
Peak memory	335856 kb
Host	smart-6b59f20b-5ef9-485a-9873-29794bab2284
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121979090 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_rw_derr.4121979090
Directory	/workspace/9.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict.3909707044
Short name	T431
Test name
Test status
Simulation time	67370200 ps
CPU time	31.48 seconds
Started	Jul 16 05:32:29 PM PDT 24
Finished	Jul 16 05:33:02 PM PDT 24
Peak memory	275604 kb
Host	smart-be3739e0-499f-4bfb-9b03-f0f9c0a3cf61
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909707044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_rw_evict.3909707044
Directory	/workspace/9.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3442999376
Short name	T563
Test name
Test status
Simulation time	69583700 ps
CPU time	30.21 seconds
Started	Jul 16 05:36:55 PM PDT 24
Finished	Jul 16 05:37:27 PM PDT 24
Peak memory	268476 kb
Host	smart-93320d6f-94aa-4ef3-985c-e7ae5e3644cd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442999376 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.3442999376
Directory	/workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_serr.2605045627
Short name	T34
Test name
Test status
Simulation time	18706235600 ps
CPU time	656.28 seconds
Started	Jul 16 05:34:18 PM PDT 24
Finished	Jul 16 05:45:15 PM PDT 24
Peak memory	326292 kb
Host	smart-db9953f8-9908-4352-b61e-4f1d05bc8df6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605045627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s err.2605045627
Directory	/workspace/9.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_smoke.2466923184
Short name	T1114
Test name
Test status
Simulation time	103331600 ps
CPU time	168.16 seconds
Started	Jul 16 05:36:15 PM PDT 24
Finished	Jul 16 05:39:03 PM PDT 24
Peak memory	277300 kb
Host	smart-750b67eb-8df1-4a71-99c0-7c63b7126d67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466923184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2466923184
Directory	/workspace/9.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.flash_ctrl_wo.1958137584
Short name	T671
Test name
Test status
Simulation time	13882183400 ps
CPU time	176.69 seconds
Started	Jul 16 05:36:54 PM PDT 24
Finished	Jul 16 05:39:52 PM PDT 24
Peak memory	260056 kb
Host	smart-6549ba01-9a05-49b6-bec1-29c152f2711b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958137584 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.flash_ctrl_wo.1958137584
Directory	/workspace/9.flash_ctrl_wo/latest

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%