Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27423937	1		T1	92085		T2	15039		T3	421
full_word	7887798	1		T1	12807		T2	10194		T3	449

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35311445	1		T1	104892		T2	25233		T3	870
auto[TlIntgErrCmd]	93	1		T121	4		T122	4		T221	6
auto[TlIntgErrData]	104	1		T121	5		T122	4		T221	8
auto[TlIntgErrBoth]	93	1		T121	1		T122	2		T221	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30746967	1		T1	91654		T2	17617		T3	568
auto[1]	4564768	1		T1	13238		T2	7616		T3	302

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26657794	1		T1	90911		T2	14060		T3	383
auto[TlIntgErrNone]	partial	auto[1]	765876	1		T1	1174		T2	979		T3	38
auto[TlIntgErrNone]	full_word	auto[0]	4089048	1		T1	743		T2	3557		T3	185
auto[TlIntgErrNone]	full_word	auto[1]	3798727	1		T1	12064		T2	6637		T3	264
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T121	2		T122	2		T221	5
auto[TlIntgErrCmd]	partial	auto[1]	40	1		T121	2		T122	2		T221	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T222	1		T250	1		T364	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T216	1		T357	1		T254	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T122	4		T221	3		T186	1
auto[TlIntgErrData]	partial	auto[1]	54	1		T121	4		T221	4		T186	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T221	1		T358	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1		T121	1		T186	1		T250	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T122	1		T221	2		T186	3
auto[TlIntgErrBoth]	partial	auto[1]	54	1		T121	1		T122	1		T221	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T363	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T186	1		T222	1		T364	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20151	1		T120	104		T121	6		T122	8
full_word	4009882	1		T4	40908		T5	16518		T6	16448

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4029767	1		T4	40908		T5	16518		T6	16448
auto[TlIntgErrCmd]	91	1		T122	3		T221	5		T186	2
auto[TlIntgErrData]	88	1		T121	5		T122	4		T221	5
auto[TlIntgErrBoth]	87	1		T121	3		T122	2		T221	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4003590	1		T4	40908		T5	16518		T6	16448
auto[1]	26443	1		T120	130		T121	4		T122	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1273	1		T120	4		T184	21		T185	62
auto[TlIntgErrNone]	partial	auto[1]	18635	1		T120	100		T184	401		T185	877
auto[TlIntgErrNone]	full_word	auto[0]	4002191	1		T4	40908		T5	16518		T6	16448
auto[TlIntgErrNone]	full_word	auto[1]	7668	1		T120	30		T184	192		T185	519
auto[TlIntgErrCmd]	partial	auto[0]	40	1		T122	1		T221	3		T216	3
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T122	1		T221	2		T186	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T222	1		T359	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T122	1		T250	1		T361	1
auto[TlIntgErrData]	partial	auto[0]	40	1		T121	2		T122	1		T221	1
auto[TlIntgErrData]	partial	auto[1]	40	1		T121	3		T122	3		T221	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T357	1		T358	2		T363	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T221	1		T216	1		T359	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T121	1		T122	2		T221	3
auto[TlIntgErrBoth]	partial	auto[1]	43	1		T221	4		T186	1		T216	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T121	1		T222	1		T360	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T121	1		T216	1		T363	2