Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1503384796	1500147080	0	0
CheckNGreaterZero_A	4184	4184	0	0
GntImpliesReady_A	1503384796	408351630	0	0
GntImpliesValid_A	1503384796	408351630	0	0
GrantKnown_A	1503384796	1500147080	0	0
IdxKnown_A	1503384796	1500147080	0	0
IndexIsCorrect_A	1503384796	408351630	0	0
NoReadyValidNoGrant_A	1503384796	179142916	0	0
Priority_A	1503384796	432818728	0	0
ReadyAndValidImplyGrant_A	1503384796	408351630	0	0
ReqAndReadyImplyGrant_A	1503384796	408351630	0	0
ReqImpliesValid_A	1503384796	432818728	0	0
ValidKnown_A	1503384796	1500147080	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	1500147080	0	0
T1	843636	843292	0	0
T2	992660	952944	0	0
T3	29856	29524	0	0
T4	1107752	1107492	0	0
T10	1608072	1608016	0	0
T11	15808	13040	0	0
T12	524728	423724	0	0
T16	13212	12980	0	0
T17	302696	302304	0	0
T18	7696	7416	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4184	4184	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	408351630	0	0
T1	843636	362010	0	0
T2	992660	178534	0	0
T3	29856	5628	0	0
T4	1107752	365984	0	0
T5	0	84886	0	0
T6	0	39256	0	0
T10	1608072	544082	0	0
T11	15808	514	0	0
T12	524728	0	0	0
T16	13212	64	0	0
T17	302696	24612	0	0
T18	7696	1102	0	0
T25	0	1462938	0	0
T26	0	131080	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	408351630	0	0
T1	843636	362010	0	0
T2	992660	178534	0	0
T3	29856	5628	0	0
T4	1107752	365984	0	0
T5	0	84886	0	0
T6	0	39256	0	0
T10	1608072	544082	0	0
T11	15808	514	0	0
T12	524728	0	0	0
T16	13212	64	0	0
T17	302696	24612	0	0
T18	7696	1102	0	0
T25	0	1462938	0	0
T26	0	131080	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	1500147080	0	0
T1	843636	843292	0	0
T2	992660	952944	0	0
T3	29856	29524	0	0
T4	1107752	1107492	0	0
T10	1608072	1608016	0	0
T11	15808	13040	0	0
T12	524728	423724	0	0
T16	13212	12980	0	0
T17	302696	302304	0	0
T18	7696	7416	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	1500147080	0	0
T1	843636	843292	0	0
T2	992660	952944	0	0
T3	29856	29524	0	0
T4	1107752	1107492	0	0
T10	1608072	1608016	0	0
T11	15808	13040	0	0
T12	524728	423724	0	0
T16	13212	12980	0	0
T17	302696	302304	0	0
T18	7696	7416	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	408351630	0	0
T1	843636	362010	0	0
T2	992660	178534	0	0
T3	29856	5628	0	0
T4	1107752	365984	0	0
T5	0	84886	0	0
T6	0	39256	0	0
T10	1608072	544082	0	0
T11	15808	514	0	0
T12	524728	0	0	0
T16	13212	64	0	0
T17	302696	24612	0	0
T18	7696	1102	0	0
T25	0	1462938	0	0
T26	0	131080	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	179142916	0	0
T1	421818	256	0	0
T2	496330	49104	0	0
T3	29856	774	0	0
T4	1107752	149022	0	0
T5	239996	1458124	0	0
T6	0	1206540	0	0
T10	1608072	2127616	0	0
T11	15808	1856	0	0
T12	524728	10610	0	0
T16	13212	256	0	0
T17	302696	256	0	0
T18	7696	314	0	0
T20	0	712	0	0
T25	295068	4926	0	0
T28	0	170	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	432818728	0	0
T1	843636	362010	0	0
T2	992660	178534	0	0
T3	29856	5628	0	0
T4	1107752	431732	0	0
T5	0	643136	0	0
T6	0	268978	0	0
T10	1608072	544082	0	0
T11	15808	514	0	0
T12	524728	0	0	0
T16	13212	64	0	0
T17	302696	24612	0	0
T18	7696	1102	0	0
T25	0	1462938	0	0
T26	0	131080	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	408351630	0	0
T1	843636	362010	0	0
T2	992660	178534	0	0
T3	29856	5628	0	0
T4	1107752	365984	0	0
T5	0	84886	0	0
T6	0	39256	0	0
T10	1608072	544082	0	0
T11	15808	514	0	0
T12	524728	0	0	0
T16	13212	64	0	0
T17	302696	24612	0	0
T18	7696	1102	0	0
T25	0	1462938	0	0
T26	0	131080	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	408351630	0	0
T1	843636	362010	0	0
T2	992660	178534	0	0
T3	29856	5628	0	0
T4	1107752	365984	0	0
T5	0	84886	0	0
T6	0	39256	0	0
T10	1608072	544082	0	0
T11	15808	514	0	0
T12	524728	0	0	0
T16	13212	64	0	0
T17	302696	24612	0	0
T18	7696	1102	0	0
T25	0	1462938	0	0
T26	0	131080	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	432818728	0	0
T1	843636	362010	0	0
T2	992660	178534	0	0
T3	29856	5628	0	0
T4	1107752	431732	0	0
T5	0	643136	0	0
T6	0	268978	0	0
T10	1608072	544082	0	0
T11	15808	514	0	0
T12	524728	0	0	0
T16	13212	64	0	0
T17	302696	24612	0	0
T18	7696	1102	0	0
T25	0	1462938	0	0
T26	0	131080	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503384796	1500147080	0	0
T1	843636	843292	0	0
T2	992660	952944	0	0
T3	29856	29524	0	0
T4	1107752	1107492	0	0
T10	1608072	1608016	0	0
T11	15808	13040	0	0
T12	524728	423724	0	0
T16	13212	12980	0	0
T17	302696	302304	0	0
T18	7696	7416	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375846199	375036770	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	375846199	111943325	0	0
GntImpliesValid_A	375846199	111943325	0	0
GrantKnown_A	375846199	375036770	0	0
IdxKnown_A	375846199	375036770	0	0
IndexIsCorrect_A	375846199	111943325	0	0
NoReadyValidNoGrant_A	375846199	46840008	0	0
Priority_A	375846199	118133494	0	0
ReadyAndValidImplyGrant_A	375846199	111943325	0	0
ReqAndReadyImplyGrant_A	375846199	111943325	0	0
ReqImpliesValid_A	375846199	118133494	0	0
ValidKnown_A	375846199	375036770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	111943325	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	103435	0	0
T5	0	17239	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	111943325	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	103435	0	0
T5	0	17239	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	111943325	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	103435	0	0
T5	0	17239	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	46840008	0	0
T1	210909	128	0	0
T2	248165	24552	0	0
T3	7464	275	0	0
T4	276938	40911	0	0
T10	402018	537728	0	0
T11	3952	928	0	0
T12	131182	2369	0	0
T16	3303	128	0	0
T17	75674	128	0	0
T18	1924	140	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	118133494	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	121074	0	0
T5	0	131503	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	111943325	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	103435	0	0
T5	0	17239	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	111943325	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	103435	0	0
T5	0	17239	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	118133494	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	121074	0	0
T5	0	131503	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375846199	375036770	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	375846199	111943325	0	0
GntImpliesValid_A	375846199	111943325	0	0
GrantKnown_A	375846199	375036770	0	0
IdxKnown_A	375846199	375036770	0	0
IndexIsCorrect_A	375846199	111943325	0	0
NoReadyValidNoGrant_A	375846199	46840008	0	0
Priority_A	375846199	118133494	0	0
ReadyAndValidImplyGrant_A	375846199	111943325	0	0
ReqAndReadyImplyGrant_A	375846199	111943325	0	0
ReqImpliesValid_A	375846199	118133494	0	0
ValidKnown_A	375846199	375036770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	111943325	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	103435	0	0
T5	0	17239	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	111943325	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	103435	0	0
T5	0	17239	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	111943325	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	103435	0	0
T5	0	17239	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	46840008	0	0
T1	210909	128	0	0
T2	248165	24552	0	0
T3	7464	275	0	0
T4	276938	40911	0	0
T10	402018	537728	0	0
T11	3952	928	0	0
T12	131182	2369	0	0
T16	3303	128	0	0
T17	75674	128	0	0
T18	1924	140	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	118133494	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	121074	0	0
T5	0	131503	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	111943325	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	103435	0	0
T5	0	17239	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	111943325	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	103435	0	0
T5	0	17239	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	118133494	0	0
T1	210909	88667	0	0
T2	248165	89267	0	0
T3	7464	1405	0	0
T4	276938	121074	0	0
T5	0	131503	0	0
T10	402018	137278	0	0
T11	3952	257	0	0
T12	131182	0	0	0
T16	3303	32	0	0
T17	75674	7517	0	0
T18	1924	540	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375846199	375036770	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	375846199	92232454	0	0
GntImpliesValid_A	375846199	92232454	0	0
GrantKnown_A	375846199	375036770	0	0
IdxKnown_A	375846199	375036770	0	0
IndexIsCorrect_A	375846199	92232454	0	0
NoReadyValidNoGrant_A	375846199	42731453	0	0
Priority_A	375846199	98275831	0	0
ReadyAndValidImplyGrant_A	375846199	92232454	0	0
ReqAndReadyImplyGrant_A	375846199	92232454	0	0
ReqImpliesValid_A	375846199	98275831	0	0
ValidKnown_A	375846199	375036770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	92232454	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	79557	0	0
T5	0	25204	0	0
T6	0	19628	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	92232454	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	79557	0	0
T5	0	25204	0	0
T6	0	19628	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	92232454	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	79557	0	0
T5	0	25204	0	0
T6	0	19628	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	42731453	0	0
T3	7464	112	0	0
T4	276938	33600	0	0
T5	119998	729062	0	0
T6	0	603270	0	0
T10	402018	526080	0	0
T11	3952	0	0	0
T12	131182	2936	0	0
T16	3303	0	0	0
T17	75674	0	0	0
T18	1924	17	0	0
T20	0	356	0	0
T25	147534	2463	0	0
T28	0	85	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	98275831	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	94792	0	0
T5	0	190065	0	0
T6	0	134489	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	92232454	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	79557	0	0
T5	0	25204	0	0
T6	0	19628	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	92232454	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	79557	0	0
T5	0	25204	0	0
T6	0	19628	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	98275831	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	94792	0	0
T5	0	190065	0	0
T6	0	134489	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375846199	375036770	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	375846199	92232526	0	0
GntImpliesValid_A	375846199	92232526	0	0
GrantKnown_A	375846199	375036770	0	0
IdxKnown_A	375846199	375036770	0	0
IndexIsCorrect_A	375846199	92232526	0	0
NoReadyValidNoGrant_A	375846199	42731447	0	0
Priority_A	375846199	98275909	0	0
ReadyAndValidImplyGrant_A	375846199	92232526	0	0
ReqAndReadyImplyGrant_A	375846199	92232526	0	0
ReqImpliesValid_A	375846199	98275909	0	0
ValidKnown_A	375846199	375036770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	92232526	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	79557	0	0
T5	0	25204	0	0
T6	0	19628	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	92232526	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	79557	0	0
T5	0	25204	0	0
T6	0	19628	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	92232526	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	79557	0	0
T5	0	25204	0	0
T6	0	19628	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	42731447	0	0
T3	7464	112	0	0
T4	276938	33600	0	0
T5	119998	729062	0	0
T6	0	603270	0	0
T10	402018	526080	0	0
T11	3952	0	0	0
T12	131182	2936	0	0
T16	3303	0	0	0
T17	75674	0	0	0
T18	1924	17	0	0
T20	0	356	0	0
T25	147534	2463	0	0
T28	0	85	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	98275909	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	94792	0	0
T5	0	190065	0	0
T6	0	134489	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	92232526	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	79557	0	0
T5	0	25204	0	0
T6	0	19628	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	92232526	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	79557	0	0
T5	0	25204	0	0
T6	0	19628	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	98275909	0	0
T1	210909	92338	0	0
T2	248165	0	0	0
T3	7464	1409	0	0
T4	276938	94792	0	0
T5	0	190065	0	0
T6	0	134489	0	0
T10	402018	134763	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	4789	0	0
T18	1924	11	0	0
T25	0	731469	0	0
T26	0	65540	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	375036770	0	0
T1	210909	210823	0	0
T2	248165	238236	0	0
T3	7464	7381	0	0
T4	276938	276873	0	0
T10	402018	402004	0	0
T11	3952	3260	0	0
T12	131182	105931	0	0
T16	3303	3245	0	0
T17	75674	75576	0	0
T18	1924	1854	0	0