Unified Coverage Report :: Module :: prim_generic_ram_1p

Module : prim_generic_ram_1p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[0].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[1].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[2].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[0].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[1].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[2].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1p

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	8368	8368	0	0
gen_wmask[0].MaskCheck_A	2147483647	178348360	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8368	8368	0	0
T1	8	8	0	0
T2	8	8	0	0
T3	8	8	0	0
T4	8	8	0	0
T10	8	8	0	0
T11	8	8	0	0
T12	8	8	0	0
T16	8	8	0	0
T17	8	8	0	0
T18	8	8	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	178348360	0	0
T1	632727	1150	0	0
T2	744495	89832	0	0
T3	29856	356	0	0
T4	1107752	9350	0	0
T5	119998	0	0	0
T6	118386	0	0	0
T10	1608072	9216	0	0
T11	15808	19	0	0
T12	524728	0	0	0
T13	3474	3	0	0
T16	13212	0	0	0
T17	302696	0	0	0
T18	7696	0	0	0
T20	5200	0	0	0
T25	295068	1846528	0	0
T26	67498	0	0	0
T27	0	131072	0	0
T28	7822	1792	0	0
T53	0	650	0	0
T56	918	0	0	0
T59	6295	0	0	0
T69	1617	0	0	0
T80	3827	3	0	0
T86	0	65536	0	0
T87	0	851968	0	0
T88	0	512	0	0
T115	0	256	0	0
T131	0	65536	0	0
T132	0	12800	0	0
T133	0	12800	0	0
T134	0	393216	0	0
T135	0	524288	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1046	1046	0	0
gen_wmask[0].MaskCheck_A	375846199	67775136	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	67775136	0	0
T1	210909	77450	0	0
T2	248165	0	0	0
T3	7464	850	0	0
T4	276938	63850	0	0
T10	402018	460032	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	10150	0	0
T18	1924	450	0	0
T25	0	593022	0	0
T26	0	256	0	0
T28	0	256	0	0
T56	0	256	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1046	1046	0	0
gen_wmask[0].MaskCheck_A	375846199	16753639	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	16753639	0	0
T1	210909	900	0	0
T2	248165	89832	0	0
T3	7464	356	0	0
T4	276938	8900	0	0
T10	402018	9216	0	0
T11	3952	19	0	0
T12	131182	0	0	0
T13	0	3	0	0
T16	3303	0	0	0
T17	75674	0	0	0
T18	1924	0	0	0
T25	0	666880	0	0
T28	0	1536	0	0
T80	0	3	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T25,T27,T86
1	0	Covered	T3,T25,T53
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1046	1046	0	0
gen_wmask[0].MaskCheck_A	375846199	7260922	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	7260922	0	0
T6	118386	0	0	0
T13	3474	0	0	0
T20	5200	0	0	0
T25	147534	589824	0	0
T26	67498	0	0	0
T27	0	65536	0	0
T28	7822	0	0	0
T56	918	0	0	0
T59	6295	0	0	0
T69	1617	0	0	0
T80	3827	0	0	0
T86	0	65536	0	0
T87	0	851968	0	0
T115	0	256	0	0
T131	0	65536	0	0
T132	0	12800	0	0
T133	0	12800	0	0
T134	0	393216	0	0
T135	0	524288	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T25
1	0	Covered	T1,T4,T28
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1046	1046	0	0
gen_wmask[0].MaskCheck_A	375846199	7373394	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	7373394	0	0
T1	210909	250	0	0
T2	248165	0	0	0
T3	7464	0	0	0
T4	276938	450	0	0
T10	402018	0	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	0	0	0
T18	1924	0	0	0
T25	0	589824	0	0
T27	0	65536	0	0
T28	0	256	0	0
T53	0	650	0	0
T88	0	512	0	0
T89	0	100	0	0
T136	0	300	0	0
T137	0	450	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1046	1046	0	0
gen_wmask[0].MaskCheck_A	375846199	57014813	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	57014813	0	0
T1	210909	82350	0	0
T2	248165	0	0	0
T3	7464	700	0	0
T4	276938	52800	0	0
T10	402018	460032	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	6900	0	0
T18	1924	0	0	0
T25	0	659602	0	0
T26	0	65536	0	0
T28	0	512	0	0
T67	0	393216	0	0
T138	0	83350	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T25,T28
1	0	Covered	T3,T25,T28
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1046	1046	0	0
gen_wmask[0].MaskCheck_A	375846199	8226784	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	8226784	0	0
T3	7464	350	0	0
T4	276938	0	0	0
T5	119998	0	0	0
T10	402018	0	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	0	0	0
T18	1924	0	0	0
T25	147534	719360	0	0
T28	0	768	0	0
T29	0	50	0	0
T30	0	50	0	0
T77	0	602624	0	0
T86	0	1712	0	0
T88	0	768	0	0
T89	0	1156	0	0
T136	0	650	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T25,T77,T87
1	0	Covered	T3,T89,T136
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1046	1046	0	0
gen_wmask[0].MaskCheck_A	375846199	6959872	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	6959872	0	0
T6	118386	0	0	0
T13	3474	0	0	0
T20	5200	0	0	0
T25	147534	655360	0	0
T26	67498	0	0	0
T28	7822	0	0	0
T56	918	0	0	0
T59	6295	0	0	0
T69	1617	0	0	0
T77	0	589824	0	0
T80	3827	0	0	0
T87	0	655360	0	0
T134	0	393216	0	0
T139	0	393216	0	0
T140	0	524288	0	0
T141	0	65536	0	0
T142	0	65536	0	0
T143	0	524288	0	0
T144	0	393216	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T25,T28
1	0	Covered	T3,T28,T88
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1046	1046	0	0
gen_wmask[0].MaskCheck_A	375846199	6983800	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375846199	6983800	0	0
T3	7464	200	0	0
T4	276938	0	0	0
T5	119998	0	0	0
T10	402018	0	0	0
T11	3952	0	0	0
T12	131182	0	0	0
T16	3303	0	0	0
T17	75674	0	0	0
T18	1924	0	0	0
T25	147534	655360	0	0
T28	0	512	0	0
T77	0	589824	0	0
T86	0	550	0	0
T87	0	655360	0	0
T89	0	250	0	0
T136	0	350	0	0
T139	0	393216	0	0
T145	0	1156	0	0