Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl_info_cfg
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.82 69.64 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg 67.86 35.71 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg 67.86 35.71 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg 71.43 42.86 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg 71.43 42.86 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg 100.00 100.00 100.00


Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
67.86 35.71 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 70.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_creator_mubi 100.00 100.00 100.00 100.00
u_owner_mubi 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
67.86 35.71 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 70.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_creator_mubi 100.00 100.00 100.00 100.00
u_owner_mubi 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.43 42.86 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.11 73.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_creator_mubi 100.00 100.00 100.00 100.00
u_owner_mubi 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.43 42.86 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.11 73.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_creator_mubi 100.00 100.00 100.00 100.00
u_owner_mubi 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_creator_mubi 100.00 100.00 100.00 100.00
u_owner_mubi 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
52.96 52.96 u_region_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_creator_mubi 100.00 100.00 100.00 100.00
u_owner_mubi 100.00 100.00 100.00 100.00

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=0,gen_info_priv[0].CurAddr=0,gen_info_priv[1].CurAddr=1,gen_info_priv[2].CurAddr=2,gen_info_priv[3].CurAddr=3,gen_info_priv[4].CurAddr=4,gen_info_priv[5].CurAddr=5,gen_info_priv[6].CurAddr=6,gen_info_priv[7].CurAddr=7,gen_info_priv[8].CurAddr=8,gen_info_priv[9].CurAddr=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg

Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
62 1 1
72 1 1
103 1 1
107 1 1
111 1 1
116 1 1
120 7 7

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=1,gen_info_priv[0].CurAddr=512,gen_info_priv[1].CurAddr=513,gen_info_priv[2].CurAddr=514,gen_info_priv[3].CurAddr=515,gen_info_priv[4].CurAddr=516,gen_info_priv[5].CurAddr=517,gen_info_priv[6].CurAddr=518,gen_info_priv[7].CurAddr=519,gen_info_priv[8].CurAddr=520,gen_info_priv[9].CurAddr=521 + Bank=1,InfoSel=1,gen_info_priv[0].CurAddr=768,gen_info_priv[1].CurAddr=769,gen_info_priv[2].CurAddr=770,gen_info_priv[3].CurAddr=771,gen_info_priv[4].CurAddr=772,gen_info_priv[5].CurAddr=773,gen_info_priv[6].CurAddr=774,gen_info_priv[7].CurAddr=775,gen_info_priv[8].CurAddr=776,gen_info_priv[9].CurAddr=777 )
Line Coverage for Module self-instances :
SCORELINE
67.86 35.71
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

SCORELINE
67.86 35.71
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

Line No.TotalCoveredPercent
TOTAL14535.71
CONT_ASSIGN5211100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN120100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
62 1 1
72 1 1
99 0 8
120 1 2
127 1 1

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=2,gen_info_priv[0].CurAddr=1024,gen_info_priv[1].CurAddr=1025,gen_info_priv[2].CurAddr=1026,gen_info_priv[3].CurAddr=1027,gen_info_priv[4].CurAddr=1028,gen_info_priv[5].CurAddr=1029,gen_info_priv[6].CurAddr=1030,gen_info_priv[7].CurAddr=1031,gen_info_priv[8].CurAddr=1032,gen_info_priv[9].CurAddr=1033 + Bank=1,InfoSel=2,gen_info_priv[0].CurAddr=1280,gen_info_priv[1].CurAddr=1281,gen_info_priv[2].CurAddr=1282,gen_info_priv[3].CurAddr=1283,gen_info_priv[4].CurAddr=1284,gen_info_priv[5].CurAddr=1285,gen_info_priv[6].CurAddr=1286,gen_info_priv[7].CurAddr=1287,gen_info_priv[8].CurAddr=1288,gen_info_priv[9].CurAddr=1289 )
Line Coverage for Module self-instances :
SCORELINE
71.43 42.86
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

SCORELINE
71.43 42.86
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

Line No.TotalCoveredPercent
TOTAL14642.86
CONT_ASSIGN5211100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN120100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
62 1 1
72 1 1
99 0 7
120 2 3
127 1 1

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=1,InfoSel=0,gen_info_priv[0].CurAddr=256,gen_info_priv[1].CurAddr=257,gen_info_priv[2].CurAddr=258,gen_info_priv[3].CurAddr=259,gen_info_priv[4].CurAddr=260,gen_info_priv[5].CurAddr=261,gen_info_priv[6].CurAddr=262,gen_info_priv[7].CurAddr=263,gen_info_priv[8].CurAddr=264,gen_info_priv[9].CurAddr=265 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
62 1 1
72 1 1
120 10 10
127 1 1

Assert Coverage for Module : flash_ctrl_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 6276 6276 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6276 6276 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T10 6 6 0 0
T11 6 6 0 0
T12 6 6 0 0
T16 6 6 0 0
T17 6 6 0 0
T18 6 6 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg
Line No.TotalCoveredPercent
TOTAL14535.71
CONT_ASSIGN5211100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN120100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
62 1 1
72 1 1
99 0 8
120 1 2
127 1 1

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 1046 1046 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1046 1046 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg
Line No.TotalCoveredPercent
TOTAL14535.71
CONT_ASSIGN5211100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN120100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
62 1 1
72 1 1
99 0 8
120 1 2
127 1 1

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 1046 1046 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1046 1046 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg
Line No.TotalCoveredPercent
TOTAL14642.86
CONT_ASSIGN5211100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN120100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
62 1 1
72 1 1
99 0 7
120 2 3
127 1 1

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 1046 1046 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1046 1046 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg
Line No.TotalCoveredPercent
TOTAL14642.86
CONT_ASSIGN5211100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN99100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN120100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
62 1 1
72 1 1
99 0 7
120 2 3
127 1 1

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 1046 1046 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1046 1046 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
62 1 1
72 1 1
103 1 1
107 1 1
111 1 1
116 1 1
120 7 7

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 1046 1046 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1046 1046 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
62 1 1
72 1 1
120 10 10
127 1 1

Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InfoNoBiggerThanData_A 1046 1046 0 0


InfoNoBiggerThanData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1046 1046 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%