Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 18225 1 T105 355 T102 95 T103 133
full_word 3988480 1 T1 16777 T3 16359 T7 120


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 4006440 1 T1 16777 T3 16359 T7 120
auto[TlIntgErrCmd] 90 1 T206 4 T255 4 T273 3
auto[TlIntgErrData] 95 1 T206 7 T255 4 T273 3
auto[TlIntgErrBoth] 80 1 T206 8 T255 2 T273 2


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3981994 1 T1 16777 T3 16359 T7 120
auto[1] 24711 1 T105 494 T102 105 T103 145


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrBoth]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1085 1 T105 38 T102 4 T103 11
auto[TlIntgErrNone] partial auto[1] 16901 1 T105 317 T102 91 T103 122
auto[TlIntgErrNone] full_word auto[0] 3980810 1 T1 16777 T3 16359 T7 120
auto[TlIntgErrNone] full_word auto[1] 7644 1 T105 177 T102 14 T103 23
auto[TlIntgErrCmd] partial auto[0] 29 1 T206 2 T273 1 T280 1
auto[TlIntgErrCmd] partial auto[1] 50 1 T206 2 T255 4 T273 1
auto[TlIntgErrCmd] full_word auto[0] 2 1 T273 1 T404 1 - -
auto[TlIntgErrCmd] full_word auto[1] 9 1 T256 1 T280 1 T396 1
auto[TlIntgErrData] partial auto[0] 42 1 T206 2 T255 3 T273 1
auto[TlIntgErrData] partial auto[1] 46 1 T206 3 T273 2 T256 4
auto[TlIntgErrData] full_word auto[0] 2 1 T285 1 T405 1 - -
auto[TlIntgErrData] full_word auto[1] 5 1 T206 2 T255 1 T401 1
auto[TlIntgErrBoth] partial auto[0] 24 1 T206 2 T255 1 T256 2
auto[TlIntgErrBoth] partial auto[1] 48 1 T206 5 T273 2 T256 4
auto[TlIntgErrBoth] full_word auto[1] 8 1 T206 1 T255 1 T256 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 25218113 1 T1 7794 T2 13864 T3 946
full_word 7760587 1 T1 33979 T2 6031 T3 43


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 32978420 1 T1 41773 T2 19895 T3 989
auto[TlIntgErrCmd] 99 1 T206 7 T255 1 T273 3
auto[TlIntgErrData] 87 1 T206 8 T255 5 T273 2
auto[TlIntgErrBoth] 94 1 T206 5 T255 4 T273 5


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28458976 1 T1 34798 T2 13410 T3 942
auto[1] 4519724 1 T1 6975 T2 6485 T3 47


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 24518594 1 T1 5295 T2 13409 T3 941
auto[TlIntgErrNone] partial auto[1] 699256 1 T1 2499 T2 455 T3 5
auto[TlIntgErrNone] full_word auto[0] 3940269 1 T1 29503 T2 1 T3 1
auto[TlIntgErrNone] full_word auto[1] 3820301 1 T1 4476 T2 6030 T3 42
auto[TlIntgErrCmd] partial auto[0] 38 1 T206 3 T273 1 T256 4
auto[TlIntgErrCmd] partial auto[1] 56 1 T206 4 T255 1 T273 1
auto[TlIntgErrCmd] full_word auto[0] 3 1 T273 1 T256 1 T285 1
auto[TlIntgErrCmd] full_word auto[1] 2 1 T396 1 T297 1 - -
auto[TlIntgErrData] partial auto[0] 37 1 T206 5 T255 1 T273 1
auto[TlIntgErrData] partial auto[1] 46 1 T206 3 T255 4 T273 1
auto[TlIntgErrData] full_word auto[0] 1 1 T400 1 - - - -
auto[TlIntgErrData] full_word auto[1] 3 1 T398 1 T297 1 T405 1
auto[TlIntgErrBoth] partial auto[0] 29 1 T206 1 T255 1 T273 2
auto[TlIntgErrBoth] partial auto[1] 57 1 T206 4 T255 1 T273 3
auto[TlIntgErrBoth] full_word auto[0] 5 1 T255 1 T396 1 T404 1
auto[TlIntgErrBoth] full_word auto[1] 3 1 T255 1 T400 1 T406 1

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