Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1523985408	1520513224	0	0
CheckNGreaterZero_A	4184	4184	0	0
GntImpliesReady_A	1523985408	403532392	0	0
GntImpliesValid_A	1523985408	403532392	0	0
GrantKnown_A	1523985408	1520513224	0	0
IdxKnown_A	1523985408	1520513224	0	0
IndexIsCorrect_A	1523985408	403532392	0	0
NoReadyValidNoGrant_A	1523985408	174416002	0	0
Priority_A	1523985408	427894228	0	0
ReadyAndValidImplyGrant_A	1523985408	403532392	0	0
ReqAndReadyImplyGrant_A	1523985408	403532392	0	0
ReqImpliesValid_A	1523985408	427894228	0	0
ValidKnown_A	1523985408	1520513224	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	1520513224	0	0
T1	664852	664352	0	0
T2	162796	162432	0	0
T3	2281896	2281200	0	0
T4	866276	866068	0	0
T7	18108	17796	0	0
T11	4612	3692	0	0
T18	310864	310492	0	0
T19	9852	9560	0	0
T20	14496	14204	0	0
T21	885968	885948	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4184	4184	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	403532392	0	0
T1	664852	89106	0	0
T2	162796	51892	0	0
T3	2281896	32786	0	0
T4	866276	84958	0	0
T5	0	135626	0	0
T7	18108	3868	0	0
T11	4612	134	0	0
T18	310864	84872	0	0
T19	9852	64	0	0
T20	14496	4438	0	0
T21	885968	437006	0	0
T24	0	41578	0	0
T25	0	16	0	0
T26	0	140	0	0
T34	0	16778	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	403532392	0	0
T1	664852	89106	0	0
T2	162796	51892	0	0
T3	2281896	32786	0	0
T4	866276	84958	0	0
T5	0	135626	0	0
T7	18108	3868	0	0
T11	4612	134	0	0
T18	310864	84872	0	0
T19	9852	64	0	0
T20	14496	4438	0	0
T21	885968	437006	0	0
T24	0	41578	0	0
T25	0	16	0	0
T26	0	140	0	0
T34	0	16778	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	1520513224	0	0
T1	664852	664352	0	0
T2	162796	162432	0	0
T3	2281896	2281200	0	0
T4	866276	866068	0	0
T7	18108	17796	0	0
T11	4612	3692	0	0
T18	310864	310492	0	0
T19	9852	9560	0	0
T20	14496	14204	0	0
T21	885968	885948	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	1520513224	0	0
T1	664852	664352	0	0
T2	162796	162432	0	0
T3	2281896	2281200	0	0
T4	866276	866068	0	0
T7	18108	17796	0	0
T11	4612	3692	0	0
T18	310864	310492	0	0
T19	9852	9560	0	0
T20	14496	14204	0	0
T21	885968	885948	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	403532392	0	0
T1	664852	89106	0	0
T2	162796	51892	0	0
T3	2281896	32786	0	0
T4	866276	84958	0	0
T5	0	135626	0	0
T7	18108	3868	0	0
T11	4612	134	0	0
T18	310864	84872	0	0
T19	9852	64	0	0
T20	14496	4438	0	0
T21	885968	437006	0	0
T24	0	41578	0	0
T25	0	16	0	0
T26	0	140	0	0
T34	0	16778	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	174416002	0	0
T1	664852	217650	0	0
T2	162796	256	0	0
T3	2281896	1084636	0	0
T4	866276	5376	0	0
T5	0	540	0	0
T7	18108	668	0	0
T11	4612	536	0	0
T15	0	1048576	0	0
T18	310864	128	0	0
T19	9852	256	0	0
T20	14496	256	0	0
T21	885968	3392	0	0
T24	0	1257124	0	0
T25	0	52	0	0
T26	0	26	0	0
T34	0	51606	0	0
T41	0	852	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	427894228	0	0
T1	664852	95190	0	0
T2	162796	51892	0	0
T3	2281896	603586	0	0
T4	866276	84958	0	0
T5	0	135626	0	0
T7	18108	3974	0	0
T11	4612	134	0	0
T18	310864	84872	0	0
T19	9852	64	0	0
T20	14496	4438	0	0
T21	885968	437006	0	0
T24	0	276648	0	0
T25	0	16	0	0
T26	0	140	0	0
T34	0	19394	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	403532392	0	0
T1	664852	89106	0	0
T2	162796	51892	0	0
T3	2281896	32786	0	0
T4	866276	84958	0	0
T5	0	135626	0	0
T7	18108	3868	0	0
T11	4612	134	0	0
T18	310864	84872	0	0
T19	9852	64	0	0
T20	14496	4438	0	0
T21	885968	437006	0	0
T24	0	41578	0	0
T25	0	16	0	0
T26	0	140	0	0
T34	0	16778	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	403532392	0	0
T1	664852	89106	0	0
T2	162796	51892	0	0
T3	2281896	32786	0	0
T4	866276	84958	0	0
T5	0	135626	0	0
T7	18108	3868	0	0
T11	4612	134	0	0
T18	310864	84872	0	0
T19	9852	64	0	0
T20	14496	4438	0	0
T21	885968	437006	0	0
T24	0	41578	0	0
T25	0	16	0	0
T26	0	140	0	0
T34	0	16778	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	427894228	0	0
T1	664852	95190	0	0
T2	162796	51892	0	0
T3	2281896	603586	0	0
T4	866276	84958	0	0
T5	0	135626	0	0
T7	18108	3974	0	0
T11	4612	134	0	0
T18	310864	84872	0	0
T19	9852	64	0	0
T20	14496	4438	0	0
T21	885968	437006	0	0
T24	0	276648	0	0
T25	0	16	0	0
T26	0	140	0	0
T34	0	19394	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523985408	1520513224	0	0
T1	664852	664352	0	0
T2	162796	162432	0	0
T3	2281896	2281200	0	0
T4	866276	866068	0	0
T7	18108	17796	0	0
T11	4612	3692	0	0
T18	310864	310492	0	0
T19	9852	9560	0	0
T20	14496	14204	0	0
T21	885968	885948	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380996352	380128306	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	380996352	107185108	0	0
GntImpliesValid_A	380996352	107185108	0	0
GrantKnown_A	380996352	380128306	0	0
IdxKnown_A	380996352	380128306	0	0
IndexIsCorrect_A	380996352	107185108	0	0
NoReadyValidNoGrant_A	380996352	45289602	0	0
Priority_A	380996352	113346157	0	0
ReadyAndValidImplyGrant_A	380996352	107185108	0	0
ReqAndReadyImplyGrant_A	380996352	107185108	0	0
ReqImpliesValid_A	380996352	113346157	0	0
ValidKnown_A	380996352	380128306	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	107185108	0	0
T1	166213	23740	0	0
T2	40699	13894	0	0
T3	570474	8807	0	0
T4	216569	42479	0	0
T7	4527	942	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	107185108	0	0
T1	166213	23740	0	0
T2	40699	13894	0	0
T3	570474	8807	0	0
T4	216569	42479	0	0
T7	4527	942	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	107185108	0	0
T1	166213	23740	0	0
T2	40699	13894	0	0
T3	570474	8807	0	0
T4	216569	42479	0	0
T7	4527	942	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	45289602	0	0
T1	166213	54248	0	0
T2	40699	128	0	0
T3	570474	272011	0	0
T4	216569	2688	0	0
T7	4527	250	0	0
T11	1153	268	0	0
T18	77716	64	0	0
T19	2463	128	0	0
T20	3624	128	0	0
T21	221492	1696	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	113346157	0	0
T1	166213	25161	0	0
T2	40699	13894	0	0
T3	570474	181207	0	0
T4	216569	42479	0	0
T7	4527	995	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	107185108	0	0
T1	166213	23740	0	0
T2	40699	13894	0	0
T3	570474	8807	0	0
T4	216569	42479	0	0
T7	4527	942	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	107185108	0	0
T1	166213	23740	0	0
T2	40699	13894	0	0
T3	570474	8807	0	0
T4	216569	42479	0	0
T7	4527	942	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	113346157	0	0
T1	166213	25161	0	0
T2	40699	13894	0	0
T3	570474	181207	0	0
T4	216569	42479	0	0
T7	4527	995	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380996352	380128306	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	380996352	107185108	0	0
GntImpliesValid_A	380996352	107185108	0	0
GrantKnown_A	380996352	380128306	0	0
IdxKnown_A	380996352	380128306	0	0
IndexIsCorrect_A	380996352	107185108	0	0
NoReadyValidNoGrant_A	380996352	45289602	0	0
Priority_A	380996352	113346157	0	0
ReadyAndValidImplyGrant_A	380996352	107185108	0	0
ReqAndReadyImplyGrant_A	380996352	107185108	0	0
ReqImpliesValid_A	380996352	113346157	0	0
ValidKnown_A	380996352	380128306	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	107185108	0	0
T1	166213	23740	0	0
T2	40699	13894	0	0
T3	570474	8807	0	0
T4	216569	42479	0	0
T7	4527	942	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	107185108	0	0
T1	166213	23740	0	0
T2	40699	13894	0	0
T3	570474	8807	0	0
T4	216569	42479	0	0
T7	4527	942	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	107185108	0	0
T1	166213	23740	0	0
T2	40699	13894	0	0
T3	570474	8807	0	0
T4	216569	42479	0	0
T7	4527	942	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	45289602	0	0
T1	166213	54248	0	0
T2	40699	128	0	0
T3	570474	272011	0	0
T4	216569	2688	0	0
T7	4527	250	0	0
T11	1153	268	0	0
T18	77716	64	0	0
T19	2463	128	0	0
T20	3624	128	0	0
T21	221492	1696	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	113346157	0	0
T1	166213	25161	0	0
T2	40699	13894	0	0
T3	570474	181207	0	0
T4	216569	42479	0	0
T7	4527	995	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	107185108	0	0
T1	166213	23740	0	0
T2	40699	13894	0	0
T3	570474	8807	0	0
T4	216569	42479	0	0
T7	4527	942	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	107185108	0	0
T1	166213	23740	0	0
T2	40699	13894	0	0
T3	570474	8807	0	0
T4	216569	42479	0	0
T7	4527	942	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	113346157	0	0
T1	166213	25161	0	0
T2	40699	13894	0	0
T3	570474	181207	0	0
T4	216569	42479	0	0
T7	4527	995	0	0
T11	1153	67	0	0
T18	77716	42436	0	0
T19	2463	32	0	0
T20	3624	2219	0	0
T21	221492	107087	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T3,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T25
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T3,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T7

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380996352	380128306	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	380996352	94581088	0	0
GntImpliesValid_A	380996352	94581088	0	0
GrantKnown_A	380996352	380128306	0	0
IdxKnown_A	380996352	380128306	0	0
IndexIsCorrect_A	380996352	94581088	0	0
NoReadyValidNoGrant_A	380996352	41918399	0	0
Priority_A	380996352	100600957	0	0
ReadyAndValidImplyGrant_A	380996352	94581088	0	0
ReqAndReadyImplyGrant_A	380996352	94581088	0	0
ReqImpliesValid_A	380996352	100600957	0	0
ValidKnown_A	380996352	380128306	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	94581088	0	0
T1	166213	20813	0	0
T2	40699	12052	0	0
T3	570474	7586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	20789	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	8389	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	94581088	0	0
T1	166213	20813	0	0
T2	40699	12052	0	0
T3	570474	7586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	20789	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	8389	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	94581088	0	0
T1	166213	20813	0	0
T2	40699	12052	0	0
T3	570474	7586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	20789	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	8389	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	41918399	0	0
T1	166213	54577	0	0
T2	40699	0	0	0
T3	570474	270307	0	0
T4	216569	0	0	0
T5	0	270	0	0
T7	4527	84	0	0
T11	1153	0	0	0
T15	0	524288	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	0	0	0
T24	0	628562	0	0
T25	0	26	0	0
T26	0	13	0	0
T34	0	25803	0	0
T41	0	426	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	100600957	0	0
T1	166213	22434	0	0
T2	40699	12052	0	0
T3	570474	120586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	138324	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	9697	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	94581088	0	0
T1	166213	20813	0	0
T2	40699	12052	0	0
T3	570474	7586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	20789	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	8389	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	94581088	0	0
T1	166213	20813	0	0
T2	40699	12052	0	0
T3	570474	7586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	20789	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	8389	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	100600957	0	0
T1	166213	22434	0	0
T2	40699	12052	0	0
T3	570474	120586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	138324	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	9697	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T3,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T25
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T3,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T7

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T25
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380996352	380128306	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	380996352	94581088	0	0
GntImpliesValid_A	380996352	94581088	0	0
GrantKnown_A	380996352	380128306	0	0
IdxKnown_A	380996352	380128306	0	0
IndexIsCorrect_A	380996352	94581088	0	0
NoReadyValidNoGrant_A	380996352	41918399	0	0
Priority_A	380996352	100600957	0	0
ReadyAndValidImplyGrant_A	380996352	94581088	0	0
ReqAndReadyImplyGrant_A	380996352	94581088	0	0
ReqImpliesValid_A	380996352	100600957	0	0
ValidKnown_A	380996352	380128306	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	94581088	0	0
T1	166213	20813	0	0
T2	40699	12052	0	0
T3	570474	7586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	20789	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	8389	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	94581088	0	0
T1	166213	20813	0	0
T2	40699	12052	0	0
T3	570474	7586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	20789	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	8389	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	94581088	0	0
T1	166213	20813	0	0
T2	40699	12052	0	0
T3	570474	7586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	20789	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	8389	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	41918399	0	0
T1	166213	54577	0	0
T2	40699	0	0	0
T3	570474	270307	0	0
T4	216569	0	0	0
T5	0	270	0	0
T7	4527	84	0	0
T11	1153	0	0	0
T15	0	524288	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	0	0	0
T24	0	628562	0	0
T25	0	26	0	0
T26	0	13	0	0
T34	0	25803	0	0
T41	0	426	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	100600957	0	0
T1	166213	22434	0	0
T2	40699	12052	0	0
T3	570474	120586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	138324	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	9697	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	94581088	0	0
T1	166213	20813	0	0
T2	40699	12052	0	0
T3	570474	7586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	20789	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	8389	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	94581088	0	0
T1	166213	20813	0	0
T2	40699	12052	0	0
T3	570474	7586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	20789	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	8389	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	100600957	0	0
T1	166213	22434	0	0
T2	40699	12052	0	0
T3	570474	120586	0	0
T4	216569	0	0	0
T5	0	67813	0	0
T7	4527	992	0	0
T11	1153	0	0	0
T18	77716	0	0	0
T19	2463	0	0	0
T20	3624	0	0	0
T21	221492	111416	0	0
T24	0	138324	0	0
T25	0	8	0	0
T26	0	70	0	0
T34	0	9697	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380996352	380128306	0	0
T1	166213	166088	0	0
T2	40699	40608	0	0
T3	570474	570300	0	0
T4	216569	216517	0	0
T7	4527	4449	0	0
T11	1153	923	0	0
T18	77716	77623	0	0
T19	2463	2390	0	0
T20	3624	3551	0	0
T21	221492	221487	0	0