Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23494649	1		T1	179		T2	9171		T3	17645
full_word	8024235	1		T1	189		T2	11346		T3	9958

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31518584	1		T1	368		T2	20517		T3	27603
auto[TlIntgErrCmd]	109	1		T224	6		T237	4		T259	2
auto[TlIntgErrData]	93	1		T224	7		T237	2		T259	6
auto[TlIntgErrBoth]	98	1		T224	7		T237	4		T259	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26977732	1		T1	304		T2	16790		T3	20237
auto[1]	4541152	1		T1	64		T2	3727		T3	7366

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22781607	1		T1	169		T2	9012		T3	16734
auto[TlIntgErrNone]	partial	auto[1]	712762	1		T1	10		T2	159		T3	911
auto[TlIntgErrNone]	full_word	auto[0]	4195998	1		T1	135		T2	7778		T3	3503
auto[TlIntgErrNone]	full_word	auto[1]	3828217	1		T1	54		T2	3568		T3	6455
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T224	2		T237	3		T276	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1		T224	4		T237	1		T259	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T276	1		T274	1		T383	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T384	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1		T224	4		T259	4		T376	1
auto[TlIntgErrData]	partial	auto[1]	41	1		T224	2		T237	1		T259	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T237	1		T259	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1		T224	1		T276	1		T311	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1		T224	2		T237	1		T259	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T224	4		T237	3		T259	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T224	1		T276	1		T311	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T381	1		T274	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18868	1		T101	985		T64	227		T104	400
full_word	4069582	1		T5	15965		T6	16330		T19	20

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4088176	1		T5	15965		T6	16330		T19	20
auto[TlIntgErrCmd]	78	1		T224	5		T237	2		T259	3
auto[TlIntgErrData]	105	1		T224	8		T237	4		T259	4
auto[TlIntgErrBoth]	91	1		T224	6		T237	3		T259	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4064343	1		T5	15965		T6	16330		T19	20
auto[1]	24107	1		T101	1162		T64	272		T104	508

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1222	1		T101	86		T64	19		T104	17
auto[TlIntgErrNone]	partial	auto[1]	17399	1		T101	899		T64	208		T104	383
auto[TlIntgErrNone]	full_word	auto[0]	4063010	1		T5	15965		T6	16330		T19	20
auto[TlIntgErrNone]	full_word	auto[1]	6545	1		T101	263		T64	64		T104	125
auto[TlIntgErrCmd]	partial	auto[0]	20	1		T224	3		T259	1		T376	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T224	1		T237	2		T259	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T381	2		T382	1		T385	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T224	1		T274	1		T378	2
auto[TlIntgErrData]	partial	auto[0]	45	1		T224	4		T237	2		T259	1
auto[TlIntgErrData]	partial	auto[1]	46	1		T224	4		T259	2		T276	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T237	2		T259	1		T311	2
auto[TlIntgErrData]	full_word	auto[1]	8	1		T276	1		T379	2		T383	2
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T224	1		T237	1		T311	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T224	5		T237	2		T259	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T274	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T379	1		T385	1		T378	1