Module Definition
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Module : flash_phy_rd_buf_dep
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.54 100.00 90.17 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.76 100.00 91.05 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Module : flash_phy_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT2,T3,T4 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T4
110Not Covered
111CoveredT2,T3,T4 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T36,T21
11CoveredT2,T3,T4 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT20,T36,T21
10CoveredT1,T2,T3
11CoveredT2,T3,T4
Branch Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 - Covered T1,T2,T3
0 - 1 Covered T2,T3,T4
0 - 0 Covered T1,T2,T3

Assert Coverage for Module : flash_phy_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 818953408 7064593 0 0
BufferDepRsp_A 818953408 817262854 0 0
BufferIncrOverFlow_A 818953408 7064597 0 0
DepBufferRspOrder_A 818953410 17393473 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 818953408 7064593 0 0
T2 149403 1024 0 0
T3 211355 3136 0 0
T4 3406 5 0 0
T5 1087516 15965 0 0
T6 252590 44474 0 0
T7 0 20904 0 0
T11 400707 0 0 0
T12 7256 0 0 0
T16 3483 0 0 0
T17 3000 0 0 0
T18 2824 21 0 0
T19 6992 228 0 0
T20 0 9 0 0
T21 0 20912 0 0
T24 2024 43 0 0
T30 226214 0 0 0
T36 0 100 0 0
T39 2414 0 0 0
T40 0 106 0 0
T46 1396 0 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 818953408 817262854 0 0
T1 770096 770066 0 0
T2 298806 298636 0 0
T3 422710 403222 0 0
T4 3406 3286 0 0
T5 1087516 1087178 0 0
T11 801414 801378 0 0
T12 7256 5992 0 0
T16 6966 6808 0 0
T17 6000 5818 0 0
T18 2824 2694 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 818953408 7064597 0 0
T2 149403 1024 0 0
T3 211355 3136 0 0
T4 3406 5 0 0
T5 1087516 15965 0 0
T6 252590 44474 0 0
T7 0 20904 0 0
T11 400707 0 0 0
T12 7256 0 0 0
T16 3483 0 0 0
T17 3000 0 0 0
T18 2824 21 0 0
T19 6992 228 0 0
T20 0 9 0 0
T21 0 20912 0 0
T24 2024 43 0 0
T30 226214 0 0 0
T36 0 100 0 0
T39 2414 0 0 0
T40 0 106 0 0
T46 1396 0 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 818953410 17393473 0 0
T1 770096 263744 0 0
T2 298806 1056 0 0
T3 422710 7296 0 0
T4 3406 37 0 0
T5 1087516 16002 0 0
T6 0 24294 0 0
T7 0 8094 0 0
T11 801414 263744 0 0
T12 7256 200 0 0
T16 6966 32 0 0
T17 6000 32 0 0
T18 2824 53 0 0
T19 0 60 0 0
T20 0 9 0 0
T24 0 9 0 0
T40 0 131110 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT2,T3,T4 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T4
110Not Covered
111CoveredT2,T3,T4 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT36,T21,T57
11CoveredT2,T3,T4 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT36,T21,T57
10CoveredT1,T2,T3
11CoveredT2,T3,T4
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 - Covered T1,T2,T3
0 - 1 Covered T2,T3,T4
0 - 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 409476704 3067736 0 0
BufferDepRsp_A 409476704 408631427 0 0
BufferIncrOverFlow_A 409476704 3067737 0 0
DepBufferRspOrder_A 409476704 8772882 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 409476704 3067736 0 0
T2 149403 1024 0 0
T3 211355 3136 0 0
T4 1703 2 0 0
T5 543758 7942 0 0
T6 126295 20180 0 0
T7 0 12810 0 0
T11 400707 0 0 0
T12 3628 0 0 0
T16 3483 0 0 0
T17 3000 0 0 0
T18 1412 21 0 0
T19 0 168 0 0
T24 0 34 0 0
T40 0 68 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 409476704 408631427 0 0
T1 385048 385033 0 0
T2 149403 149318 0 0
T3 211355 201611 0 0
T4 1703 1643 0 0
T5 543758 543589 0 0
T11 400707 400689 0 0
T12 3628 2996 0 0
T16 3483 3404 0 0
T17 3000 2909 0 0
T18 1412 1347 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 409476704 3067737 0 0
T2 149403 1024 0 0
T3 211355 3136 0 0
T4 1703 2 0 0
T5 543758 7942 0 0
T6 126295 20180 0 0
T7 0 12810 0 0
T11 400707 0 0 0
T12 3628 0 0 0
T16 3483 0 0 0
T17 3000 0 0 0
T18 1412 21 0 0
T19 0 168 0 0
T24 0 34 0 0
T40 0 68 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 409476704 8772882 0 0
T1 385048 132672 0 0
T2 149403 1056 0 0
T3 211355 7296 0 0
T4 1703 34 0 0
T5 543758 7979 0 0
T11 400707 132672 0 0
T12 3628 200 0 0
T16 3483 32 0 0
T17 3000 32 0 0
T18 1412 53 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T11,T40
101CoveredT1,T2,T3
110Not Covered
111CoveredT4,T5,T6 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110Not Covered
111CoveredT4,T5,T6 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T36,T61
11CoveredT4,T5,T6 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT20,T36,T61
10CoveredT1,T2,T3
11CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T5,T6
0 0 - Covered T1,T2,T3
0 - 1 Covered T4,T5,T6
0 - 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 409476704 3996857 0 0
BufferDepRsp_A 409476704 408631427 0 0
BufferIncrOverFlow_A 409476704 3996860 0 0
DepBufferRspOrder_A 409476706 8620591 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 409476704 3996857 0 0
T4 1703 3 0 0
T5 543758 8023 0 0
T6 126295 24294 0 0
T7 0 8094 0 0
T12 3628 0 0 0
T18 1412 0 0 0
T19 6992 60 0 0
T20 0 9 0 0
T21 0 20912 0 0
T24 2024 9 0 0
T30 226214 0 0 0
T36 0 100 0 0
T39 2414 0 0 0
T40 0 38 0 0
T46 1396 0 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 409476704 408631427 0 0
T1 385048 385033 0 0
T2 149403 149318 0 0
T3 211355 201611 0 0
T4 1703 1643 0 0
T5 543758 543589 0 0
T11 400707 400689 0 0
T12 3628 2996 0 0
T16 3483 3404 0 0
T17 3000 2909 0 0
T18 1412 1347 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 409476704 3996860 0 0
T4 1703 3 0 0
T5 543758 8023 0 0
T6 126295 24294 0 0
T7 0 8094 0 0
T12 3628 0 0 0
T18 1412 0 0 0
T19 6992 60 0 0
T20 0 9 0 0
T21 0 20912 0 0
T24 2024 9 0 0
T30 226214 0 0 0
T36 0 100 0 0
T39 2414 0 0 0
T40 0 38 0 0
T46 1396 0 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 409476706 8620591 0 0
T1 385048 131072 0 0
T2 149403 0 0 0
T3 211355 0 0 0
T4 1703 3 0 0
T5 543758 8023 0 0
T6 0 24294 0 0
T7 0 8094 0 0
T11 400707 131072 0 0
T12 3628 0 0 0
T16 3483 0 0 0
T17 3000 0 0 0
T18 1412 0 0 0
T19 0 60 0 0
T20 0 9 0 0
T24 0 9 0 0
T40 0 131110 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%