Module Definition
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Module : tlul_sram_byte
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_to_prog_fifo.u_sram_byte 100.00 100.00 100.00
tb.dut.u_to_rd_fifo.u_sram_byte 100.00 100.00 100.00
tb.dut.u_tl_adapter_eflash.u_sram_byte 100.00 100.00 100.00



Module Instance : tb.dut.u_to_prog_fifo.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.96 100.00 65.52 85.71 84.62 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_rd_fifo.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.86 95.83 73.39 86.21 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.06 100.00 79.69 96.55 100.00 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : tlul_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN71000
CONT_ASSIGN71600
CONT_ASSIGN71700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
702 1 1
703 1 1
704 1 1
710 unreachable
716 unreachable
717 unreachable


Assert Coverage for Module : tlul_sram_byte
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SramReadbackAndIntg 3132 3132 0 0


SramReadbackAndIntg
NameAttemptsReal SuccessesFailuresIncomplete
Total 3132 3132 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T11 3 3 0 0
T12 3 3 0 0
T16 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN71000
CONT_ASSIGN71600
CONT_ASSIGN71700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
702 1 1
703 1 1
704 1 1
710 unreachable
716 unreachable
717 unreachable


Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SramReadbackAndIntg 1044 1044 0 0


SramReadbackAndIntg
NameAttemptsReal SuccessesFailuresIncomplete
Total 1044 1044 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN71000
CONT_ASSIGN71600
CONT_ASSIGN71700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
702 1 1
703 1 1
704 1 1
710 unreachable
716 unreachable
717 unreachable


Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SramReadbackAndIntg 1044 1044 0 0


SramReadbackAndIntg
NameAttemptsReal SuccessesFailuresIncomplete
Total 1044 1044 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN71000
CONT_ASSIGN71600
CONT_ASSIGN71700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
702 1 1
703 1 1
704 1 1
710 unreachable
716 unreachable
717 unreachable


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SramReadbackAndIntg 1044 1044 0 0


SramReadbackAndIntg
NameAttemptsReal SuccessesFailuresIncomplete
Total 1044 1044 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%