Module Definition
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Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.94 99.31 95.82 100.00 99.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 80.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_chk 100.00 100.00 100.00 100.00
u_csr0_regwen 100.00 100.00 100.00 100.00
u_csr10 100.00 100.00 100.00 100.00
u_csr11 100.00 100.00 100.00 100.00
u_csr12 100.00 100.00 100.00 100.00
u_csr13_field0 100.00 100.00 100.00 100.00
u_csr13_field1 100.00 100.00 100.00 100.00
u_csr14_field0 100.00 100.00 100.00 100.00
u_csr14_field1 100.00 100.00 100.00 100.00
u_csr15_field0 100.00 100.00 100.00 100.00
u_csr15_field1 100.00 100.00 100.00 100.00
u_csr16_field0 100.00 100.00 100.00 100.00
u_csr16_field1 100.00 100.00 100.00 100.00
u_csr17_field0 100.00 100.00 100.00 100.00
u_csr17_field1 100.00 100.00 100.00 100.00
u_csr18 100.00 100.00 100.00 100.00
u_csr19 100.00 100.00 100.00 100.00
u_csr1_field0 100.00 100.00 100.00 100.00
u_csr1_field1 100.00 100.00 100.00 100.00
u_csr20_field0 88.89 100.00 66.67 100.00
u_csr20_field1 88.89 100.00 66.67 100.00
u_csr20_field2 55.19 55.56 50.00 60.00
u_csr2_field0 88.89 100.00 66.67 100.00
u_csr2_field1 88.89 100.00 66.67 100.00
u_csr2_field2 88.89 100.00 66.67 100.00
u_csr2_field3 96.30 100.00 88.89 100.00
u_csr2_field4 88.89 100.00 66.67 100.00
u_csr2_field5 88.89 100.00 66.67 100.00
u_csr2_field6 88.89 100.00 66.67 100.00
u_csr2_field7 96.30 100.00 88.89 100.00
u_csr3_field0 100.00 100.00 100.00 100.00
u_csr3_field1 100.00 100.00 100.00 100.00
u_csr3_field2 100.00 100.00 100.00 100.00
u_csr3_field3 100.00 100.00 100.00 100.00
u_csr3_field4 100.00 100.00 100.00 100.00
u_csr3_field5 100.00 100.00 100.00 100.00
u_csr3_field6 100.00 100.00 100.00 100.00
u_csr3_field7 100.00 100.00 100.00 100.00
u_csr3_field8 100.00 100.00 100.00 100.00
u_csr3_field9 100.00 100.00 100.00 100.00
u_csr4_field0 100.00 100.00 100.00 100.00
u_csr4_field1 100.00 100.00 100.00 100.00
u_csr4_field2 100.00 100.00 100.00 100.00
u_csr4_field3 100.00 100.00 100.00 100.00
u_csr5_field0 100.00 100.00 100.00 100.00
u_csr5_field1 100.00 100.00 100.00 100.00
u_csr5_field2 100.00 100.00 100.00 100.00
u_csr5_field3 100.00 100.00 100.00 100.00
u_csr5_field4 100.00 100.00 100.00 100.00
u_csr6_field0 100.00 100.00 100.00 100.00
u_csr6_field1 100.00 100.00 100.00 100.00
u_csr6_field2 100.00 100.00 100.00 100.00
u_csr6_field3 100.00 100.00 100.00 100.00
u_csr6_field4 100.00 100.00 100.00 100.00
u_csr6_field5 100.00 100.00 100.00 100.00
u_csr6_field6 100.00 100.00 100.00 100.00
u_csr6_field7 100.00 100.00 100.00 100.00
u_csr6_field8 100.00 100.00 100.00 100.00
u_csr7_field0 100.00 100.00 100.00 100.00
u_csr7_field1 100.00 100.00 100.00 100.00
u_csr8 100.00 100.00 100.00 100.00
u_csr9 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.67 97.14 97.53 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_prim_reg_top
Line No.TotalCoveredPercent
TOTAL219219100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN85111100.00
CONT_ASSIGN96411100.00
CONT_ASSIGN110411100.00
CONT_ASSIGN135211100.00
CONT_ASSIGN141111100.00
CONT_ASSIGN144211100.00
CONT_ASSIGN147311100.00
CONT_ASSIGN150411100.00
CONT_ASSIGN153511100.00
CONT_ASSIGN156611100.00
CONT_ASSIGN162511100.00
CONT_ASSIGN168411100.00
CONT_ASSIGN174311100.00
CONT_ASSIGN180211100.00
CONT_ASSIGN186111100.00
CONT_ASSIGN189211100.00
ALWAYS20062222100.00
CONT_ASSIGN203011100.00
ALWAYS203411100.00
CONT_ASSIGN205911100.00
CONT_ASSIGN206111100.00
CONT_ASSIGN206211100.00
CONT_ASSIGN206411100.00
CONT_ASSIGN206611100.00
CONT_ASSIGN206711100.00
CONT_ASSIGN206911100.00
CONT_ASSIGN207111100.00
CONT_ASSIGN207311100.00
CONT_ASSIGN207511100.00
CONT_ASSIGN207711100.00
CONT_ASSIGN207911100.00
CONT_ASSIGN208111100.00
CONT_ASSIGN208311100.00
CONT_ASSIGN208411100.00
CONT_ASSIGN208611100.00
CONT_ASSIGN208811100.00
CONT_ASSIGN209011100.00
CONT_ASSIGN209211100.00
CONT_ASSIGN209411100.00
CONT_ASSIGN209611100.00
CONT_ASSIGN209811100.00
CONT_ASSIGN210011100.00
CONT_ASSIGN210211100.00
CONT_ASSIGN210411100.00
CONT_ASSIGN210511100.00
CONT_ASSIGN210711100.00
CONT_ASSIGN210911100.00
CONT_ASSIGN211111100.00
CONT_ASSIGN211311100.00
CONT_ASSIGN211411100.00
CONT_ASSIGN211611100.00
CONT_ASSIGN211811100.00
CONT_ASSIGN212011100.00
CONT_ASSIGN212211100.00
CONT_ASSIGN212411100.00
CONT_ASSIGN212511100.00
CONT_ASSIGN212711100.00
CONT_ASSIGN212911100.00
CONT_ASSIGN213111100.00
CONT_ASSIGN213311100.00
CONT_ASSIGN213511100.00
CONT_ASSIGN213711100.00
CONT_ASSIGN213911100.00
CONT_ASSIGN214111100.00
CONT_ASSIGN214311100.00
CONT_ASSIGN214411100.00
CONT_ASSIGN214611100.00
CONT_ASSIGN214811100.00
CONT_ASSIGN214911100.00
CONT_ASSIGN215111100.00
CONT_ASSIGN215211100.00
CONT_ASSIGN215411100.00
CONT_ASSIGN215511100.00
CONT_ASSIGN215711100.00
CONT_ASSIGN215811100.00
CONT_ASSIGN216011100.00
CONT_ASSIGN216111100.00
CONT_ASSIGN216311100.00
CONT_ASSIGN216411100.00
CONT_ASSIGN216611100.00
CONT_ASSIGN216811100.00
CONT_ASSIGN216911100.00
CONT_ASSIGN217111100.00
CONT_ASSIGN217311100.00
CONT_ASSIGN217411100.00
CONT_ASSIGN217611100.00
CONT_ASSIGN217811100.00
CONT_ASSIGN217911100.00
CONT_ASSIGN218111100.00
CONT_ASSIGN218311100.00
CONT_ASSIGN218411100.00
CONT_ASSIGN218611100.00
CONT_ASSIGN218811100.00
CONT_ASSIGN218911100.00
CONT_ASSIGN219111100.00
CONT_ASSIGN219211100.00
CONT_ASSIGN219411100.00
CONT_ASSIGN219511100.00
CONT_ASSIGN219711100.00
CONT_ASSIGN219911100.00
ALWAYS22032222100.00
ALWAYS22296363100.00
CONT_ASSIGN236600
CONT_ASSIGN237411100.00
CONT_ASSIGN237511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
299 1 1
576 1 1
851 1 1
964 1 1
1104 1 1
1352 1 1
1411 1 1
1442 1 1
1473 1 1
1504 1 1
1535 1 1
1566 1 1
1625 1 1
1684 1 1
1743 1 1
1802 1 1
1861 1 1
1892 1 1
2006 1 1
2007 1 1
2008 1 1
2009 1 1
2010 1 1
2011 1 1
2012 1 1
2013 1 1
2014 1 1
2015 1 1
2016 1 1
2017 1 1
2018 1 1
2019 1 1
2020 1 1
2021 1 1
2022 1 1
2023 1 1
2024 1 1
2025 1 1
2026 1 1
2027 1 1
2030 1 1
2034 1 1
2059 1 1
2061 1 1
2062 1 1
2064 1 1
2066 1 1
2067 1 1
2069 1 1
2071 1 1
2073 1 1
2075 1 1
2077 1 1
2079 1 1
2081 1 1
2083 1 1
2084 1 1
2086 1 1
2088 1 1
2090 1 1
2092 1 1
2094 1 1
2096 1 1
2098 1 1
2100 1 1
2102 1 1
2104 1 1
2105 1 1
2107 1 1
2109 1 1
2111 1 1
2113 1 1
2114 1 1
2116 1 1
2118 1 1
2120 1 1
2122 1 1
2124 1 1
2125 1 1
2127 1 1
2129 1 1
2131 1 1
2133 1 1
2135 1 1
2137 1 1
2139 1 1
2141 1 1
2143 1 1
2144 1 1
2146 1 1
2148 1 1
2149 1 1
2151 1 1
2152 1 1
2154 1 1
2155 1 1
2157 1 1
2158 1 1
2160 1 1
2161 1 1
2163 1 1
2164 1 1
2166 1 1
2168 1 1
2169 1 1
2171 1 1
2173 1 1
2174 1 1
2176 1 1
2178 1 1
2179 1 1
2181 1 1
2183 1 1
2184 1 1
2186 1 1
2188 1 1
2189 1 1
2191 1 1
2192 1 1
2194 1 1
2195 1 1
2197 1 1
2199 1 1
2203 1 1
2204 1 1
2205 1 1
2206 1 1
2207 1 1
2208 1 1
2209 1 1
2210 1 1
2211 1 1
2212 1 1
2213 1 1
2214 1 1
2215 1 1
2216 1 1
2217 1 1
2218 1 1
2219 1 1
2220 1 1
2221 1 1
2222 1 1
2223 1 1
2224 1 1
2229 1 1
2230 1 1
2232 1 1
2236 1 1
2237 1 1
2241 1 1
2242 1 1
2243 1 1
2244 1 1
2245 1 1
2246 1 1
2247 1 1
2248 1 1
2252 1 1
2253 1 1
2254 1 1
2255 1 1
2256 1 1
2257 1 1
2258 1 1
2259 1 1
2260 1 1
2261 1 1
2265 1 1
2266 1 1
2267 1 1
2268 1 1
2272 1 1
2273 1 1
2274 1 1
2275 1 1
2276 1 1
2280 1 1
2281 1 1
2282 1 1
2283 1 1
2284 1 1
2285 1 1
2286 1 1
2287 1 1
2288 1 1
2292 1 1
2293 1 1
2297 1 1
2301 1 1
2305 1 1
2309 1 1
2313 1 1
2317 1 1
2318 1 1
2322 1 1
2323 1 1
2327 1 1
2328 1 1
2332 1 1
2333 1 1
2337 1 1
2338 1 1
2342 1 1
2346 1 1
2350 1 1
2351 1 1
2352 1 1
2366 unreachable
2374 1 1
2375 1 1


Cond Coverage for Module : flash_ctrl_prim_reg_top
TotalCoveredPercent
Conditions287287100.00
Logical287287100.00
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT101,T104,T103
11CoveredT101,T63,T64

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T15
10CoveredT224,T237,T259

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT13,T14,T15
010CoveredT224,T237,T259
100CoveredT13,T14,T15

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT224,T237,T259
010CoveredT101,T64,T104
100CoveredT101,T64,T104

 LINE       299
 EXPRESSION (csr1_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT224,T237,T281
11CoveredT63,T64,T105

 LINE       576
 EXPRESSION (csr3_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT102,T224,T237
11CoveredT63,T64,T105

 LINE       851
 EXPRESSION (csr4_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT105,T224,T237
11CoveredT63,T64,T105

 LINE       964
 EXPRESSION (csr5_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT105,T224,T237
11CoveredT63,T64,T105

 LINE       1104
 EXPRESSION (csr6_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT224,T237,T281
11CoveredT63,T64,T105

 LINE       1352
 EXPRESSION (csr7_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT105,T102,T224
11CoveredT63,T64,T105

 LINE       1411
 EXPRESSION (csr8_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT224,T237,T281
11CoveredT63,T64,T105

 LINE       1442
 EXPRESSION (csr9_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT102,T224,T237
11CoveredT63,T64,T105

 LINE       1473
 EXPRESSION (csr10_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT105,T102,T224
11CoveredT63,T64,T105

 LINE       1504
 EXPRESSION (csr11_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT224,T237,T281
11CoveredT63,T64,T105

 LINE       1535
 EXPRESSION (csr12_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT105,T224,T237
11CoveredT63,T64,T105

 LINE       1566
 EXPRESSION (csr13_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT105,T102,T224
11CoveredT63,T64,T105

 LINE       1625
 EXPRESSION (csr14_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT105,T224,T237
11CoveredT63,T64,T105

 LINE       1684
 EXPRESSION (csr15_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT105,T102,T224
11CoveredT63,T64,T105

 LINE       1743
 EXPRESSION (csr16_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT224,T237,T259
11CoveredT63,T64,T105

 LINE       1802
 EXPRESSION (csr17_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT102,T224,T237
11CoveredT63,T64,T105

 LINE       1861
 EXPRESSION (csr18_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT102,T224,T237
11CoveredT63,T64,T105

 LINE       1892
 EXPRESSION (csr19_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT224,T237,T281
11CoveredT63,T64,T105

 LINE       2007
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR0_REGWEN_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT25,T320,T32

 LINE       2008
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR1_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT320,T321,T322

 LINE       2009
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR2_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT320,T321,T322

 LINE       2010
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR3_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT96,T100,T320

 LINE       2011
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR4_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT39,T320,T323

 LINE       2012
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR5_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT54,T100,T124

 LINE       2013
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR6_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT320,T321,T322

 LINE       2014
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR7_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT320,T108,T321

 LINE       2015
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR8_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT16,T30,T39
1CoveredT18,T7,T100

 LINE       2016
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR9_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT320,T321,T322

 LINE       2017
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR10_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT95,T26,T100

 LINE       2018
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR11_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT320,T321,T322

 LINE       2019
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR12_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT98,T320,T32

 LINE       2020
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR13_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT16,T18,T39
1CoveredT30,T320,T174

 LINE       2021
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR14_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT320,T146,T321

 LINE       2022
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR15_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT324,T100,T125

 LINE       2023
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR16_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT320,T174,T71

 LINE       2024
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR17_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT97,T125,T127

 LINE       2025
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR18_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT18,T30,T39
1CoveredT16,T26,T320

 LINE       2026
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR19_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT320,T321,T325

 LINE       2027
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR20_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT16,T18,T30
1CoveredT61,T124,T320

 LINE       2030
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT101,T63,T64

 LINE       2030
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT101,T63,T64
10CoveredT101,T63,T64

 LINE       2034
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT18,T39,T54
10CoveredT101,T63,T64
11CoveredT101,T64,T104

 LINE       2034
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT16,T30,T99
21 (addr_hit[20] & ((|(4'...CoveredT124,T320,T321
20 (addr_hit[19] & ((|(4'...CoveredT320,T321,T322
19 (addr_hit[18] & ((|(4'...CoveredT320,T321,T322
18 (addr_hit[17] & ((|(4'...CoveredT97,T125,T127
17 (addr_hit[16] & ((|(4'...CoveredT320,T174,T321
16 (addr_hit[15] & ((|(4'...CoveredT324,T100,T125
15 (addr_hit[14] & ((|(4'...CoveredT321,T326,T322
14 (addr_hit[13] & ((|(4'...CoveredT320,T174,T147
13 (addr_hit[12] & ((|(4'...CoveredT98,T320,T32
12 (addr_hit[11] & ((|(4'...CoveredT320,T321,T322
11 (addr_hit[10] & ((|(4'...CoveredT95,T26,T320
10 (addr_hit[9] & ((|(4'b...CoveredT320,T321,T322
9 (addr_hit[8] & ((|(4'b...CoveredT18,T7,T100
8 (addr_hit[7] & ((|(4'b...CoveredT320,T321,T168
7 (addr_hit[6] & ((|(4'b...CoveredT320,T321,T322
6 (addr_hit[5] & ((|(4'b...CoveredT54,T124,T320
5 (addr_hit[4] & ((|(4'b...CoveredT39,T320,T323
4 (addr_hit[3] & ((|(4'b...CoveredT96,T100,T320
3 (addr_hit[2] & ((|(4'b...CoveredT321,T322,T14
2 (addr_hit[1] & ((|(4'b...CoveredT320,T321,T322
1 (addr_hit[0] & ((|(4'b...CoveredT320,T32,T321

 LINE       2034
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT54,T25,T98
10CoveredT25,T320,T173
11CoveredT320,T32,T321

 LINE       2034
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT18,T39,T54
10CoveredT321,T322,T14
11CoveredT320,T321,T322

 LINE       2034
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT54,T25,T98
10CoveredT320,T321,T322
11CoveredT321,T322,T14

 LINE       2034
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT16,T18,T30
10CoveredT322,T14,T48
11CoveredT96,T100,T320

 LINE       2034
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT18,T54,T95
10CoveredT320,T321,T322
11CoveredT39,T320,T323

 LINE       2034
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT16,T18,T39
10CoveredT100,T321,T322
11CoveredT54,T124,T320

 LINE       2034
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT16,T18,T30
10CoveredT14,T327,T328
11CoveredT320,T321,T322

 LINE       2034
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT16,T18,T39
10CoveredT320,T108,T321
11CoveredT320,T321,T168

 LINE       2034
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT16,T30,T39
10CoveredT321,T14,T329
11CoveredT18,T7,T100

 LINE       2034
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT16,T18,T30
10CoveredT330,T331,T111
11CoveredT320,T321,T322

 LINE       2034
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT16,T18,T30
10CoveredT100,T14,T332
11CoveredT95,T26,T320

 LINE       2034
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT16,T18,T30
10CoveredT321,T333,T330
11CoveredT320,T321,T322

 LINE       2034
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT18,T39,T54
10CoveredT321,T322,T14
11CoveredT98,T320,T32

 LINE       2034
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT16,T18,T39
10CoveredT30,T320,T321
11CoveredT320,T174,T147

 LINE       2034
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT18,T39,T54
10CoveredT320,T146,T171
11CoveredT321,T326,T322

 LINE       2034
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT18,T39,T54
10CoveredT320,T173,T322
11CoveredT324,T100,T125

 LINE       2034
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT18,T39,T54
10CoveredT71,T321,T322
11CoveredT320,T174,T321

 LINE       2034
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT18,T39,T54
10CoveredT320,T321,T322
11CoveredT97,T125,T127

 LINE       2034
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT54,T25,T98
10CoveredT16,T26,T320
11CoveredT320,T321,T322

 LINE       2034
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT54,T25,T98
10CoveredT320,T321,T325
11CoveredT320,T321,T322

 LINE       2034
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT54,T25,T98
10CoveredT61,T320,T173
11CoveredT124,T320,T321

 LINE       2059
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT25,T125,T320
110CoveredT101,T64,T103
111CoveredT63,T64,T105

 LINE       2062
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT54,T320,T321
110CoveredT101,T64,T103
111CoveredT63,T64,T105

 LINE       2067
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT320,T108,T147
110CoveredT64,T104,T102
111CoveredT63,T64,T105

 LINE       2084
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT96,T100,T320
110CoveredT101,T102,T103
111CoveredT63,T64,T105

 LINE       2105
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT39,T320,T323
110CoveredT101,T64,T103
111CoveredT63,T64,T105

 LINE       2114
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT54,T25,T100
110CoveredT101,T64,T104
111CoveredT63,T64,T105

 LINE       2125
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT95,T26,T320
110CoveredT101,T64,T104
111CoveredT63,T64,T105

 LINE       2144
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT320,T108,T321
110CoveredT101,T104,T102
111CoveredT63,T64,T105

 LINE       2149
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT18,T7,T100
110CoveredT101,T103,T234
111CoveredT63,T64,T105

 LINE       2152
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT96,T320,T73
110CoveredT101,T64,T104
111CoveredT63,T64,T105

 LINE       2155
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT95,T26,T100
110CoveredT101,T64,T104
111CoveredT63,T64,T105

 LINE       2158
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT34,T320,T32
110CoveredT101,T64,T104
111CoveredT63,T64,T105

 LINE       2161
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT98,T324,T320
110CoveredT101,T64,T102
111CoveredT63,T64,T105

 LINE       2164
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT30,T320,T174
110CoveredT101,T64,T104
111CoveredT63,T64,T105

 LINE       2169
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT320,T146,T173
110CoveredT101,T103,T225
111CoveredT63,T64,T105

 LINE       2174
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT324,T100,T125
110CoveredT101,T104,T103
111CoveredT63,T64,T105

 LINE       2179
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT39,T99,T320
110CoveredT101,T64,T102
111CoveredT63,T64,T105

 LINE       2184
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT97,T125,T127
110CoveredT101,T64,T104
111CoveredT63,T64,T105

 LINE       2189
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT16,T26,T320
110CoveredT101,T64,T104
111CoveredT63,T64,T105

 LINE       2192
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT7,T320,T321
110CoveredT101,T64,T103
111CoveredT63,T64,T105

 LINE       2195
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT63,T64,T105
101CoveredT61,T124,T320
110CoveredT101,T104,T102
111CoveredT63,T64,T105

Branch Coverage for Module : flash_ctrl_prim_reg_top
Line No.TotalCoveredPercent
Branches 27 27 100.00
TERNARY 2030 2 2 100.00
IF 68 3 3 100.00
CASE 2230 22 22 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 2030 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T101,T63,T64
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T13,T14,T15
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 2230 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : flash_ctrl_prim_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 412271770 57884 0 0
reAfterRv 412271770 57884 0 0
rePulse 412271770 38600 0 0
wePulse 412271770 19284 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 412271770 57884 0 0
T63 3894 63 0 0
T64 2157 98 0 0
T101 5244 58 0 0
T102 3604 167 0 0
T103 4628 214 0 0
T104 2917 18 0 0
T105 2265 84 0 0
T224 73063 1223 0 0
T234 2238 11 0 0
T334 1582 66 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 412271770 57884 0 0
T63 3894 63 0 0
T64 2157 98 0 0
T101 5244 58 0 0
T102 3604 167 0 0
T103 4628 214 0 0
T104 2917 18 0 0
T105 2265 84 0 0
T224 73063 1223 0 0
T234 2238 11 0 0
T334 1582 66 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 412271770 38600 0 0
T63 3894 42 0 0
T64 2157 60 0 0
T101 5244 6 0 0
T102 3604 116 0 0
T103 4628 133 0 0
T104 2917 3 0 0
T105 2265 42 0 0
T224 73063 799 0 0
T234 2238 2 0 0
T334 1582 45 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 412271770 19284 0 0
T63 3894 21 0 0
T64 2157 38 0 0
T101 5244 52 0 0
T102 3604 51 0 0
T103 4628 81 0 0
T104 2917 15 0 0
T105 2265 42 0 0
T224 73063 424 0 0
T234 2238 9 0 0
T334 1582 21 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%