Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T19

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1637906816	1634525708	0	0
CheckNGreaterZero_A	4176	4176	0	0
GntImpliesReady_A	1637906816	399317062	0	0
GntImpliesValid_A	1637906816	399317062	0	0
GrantKnown_A	1637906816	1634525708	0	0
IdxKnown_A	1637906816	1634525708	0	0
IndexIsCorrect_A	1637906816	399317062	0	0
NoReadyValidNoGrant_A	1637906816	184120698	0	0
Priority_A	1637906816	423965726	0	0
ReadyAndValidImplyGrant_A	1637906816	399317062	0	0
ReqAndReadyImplyGrant_A	1637906816	399317062	0	0
ReqImpliesValid_A	1637906816	423965726	0	0
ValidKnown_A	1637906816	1634525708	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	1634525708	0	0
T1	1540192	1540132	0	0
T2	597612	597272	0	0
T3	845420	806444	0	0
T4	6812	6572	0	0
T5	2175032	2174356	0	0
T11	1602828	1602756	0	0
T12	14512	11984	0	0
T16	13932	13616	0	0
T17	12000	11636	0	0
T18	5648	5388	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4176	4176	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	399317062	0	0
T1	1540192	514600	0	0
T2	597612	30248	0	0
T3	845420	177788	0	0
T4	6812	930	0	0
T5	2175032	32004	0	0
T6	0	48588	0	0
T11	1602828	514600	0	0
T12	14512	424	0	0
T16	13932	64	0	0
T17	12000	64	0	0
T18	5648	106	0	0
T19	0	1680	0	0
T24	0	150	0	0
T39	0	446	0	0
T54	0	228	0	0
T58	0	218460	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	399317062	0	0
T1	1540192	514600	0	0
T2	597612	30248	0	0
T3	845420	177788	0	0
T4	6812	930	0	0
T5	2175032	32004	0	0
T6	0	48588	0	0
T11	1602828	514600	0	0
T12	14512	424	0	0
T16	13932	64	0	0
T17	12000	64	0	0
T18	5648	106	0	0
T19	0	1680	0	0
T24	0	150	0	0
T39	0	446	0	0
T54	0	228	0	0
T58	0	218460	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	1634525708	0	0
T1	1540192	1540132	0	0
T2	597612	597272	0	0
T3	845420	806444	0	0
T4	6812	6572	0	0
T5	2175032	2174356	0	0
T11	1602828	1602756	0	0
T12	14512	11984	0	0
T16	13932	13616	0	0
T17	12000	11636	0	0
T18	5648	5388	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	1634525708	0	0
T1	1540192	1540132	0	0
T2	597612	597272	0	0
T3	845420	806444	0	0
T4	6812	6572	0	0
T5	2175032	2174356	0	0
T11	1602828	1602756	0	0
T12	14512	11984	0	0
T16	13932	13616	0	0
T17	12000	11636	0	0
T18	5648	5388	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	399317062	0	0
T1	1540192	514600	0	0
T2	597612	30248	0	0
T3	845420	177788	0	0
T4	6812	930	0	0
T5	2175032	32004	0	0
T6	0	48588	0	0
T11	1602828	514600	0	0
T12	14512	424	0	0
T16	13932	64	0	0
T17	12000	64	0	0
T18	5648	106	0	0
T19	0	1680	0	0
T24	0	150	0	0
T39	0	446	0	0
T54	0	228	0	0
T58	0	218460	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	184120698	0	0
T1	1540192	2109952	0	0
T2	597612	5376	0	0
T3	845420	48480	0	0
T4	6812	274	0	0
T5	2175032	1194814	0	0
T6	0	1438582	0	0
T7	0	48606	0	0
T11	1602828	2109952	0	0
T12	14512	1600	0	0
T16	13932	256	0	0
T17	12000	256	0	0
T18	5648	320	0	0
T19	0	306	0	0
T20	0	28	0	0
T24	0	60	0	0
T40	0	1048694	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	423965726	0	0
T1	1540192	514600	0	0
T2	597612	30248	0	0
T3	845420	177788	0	0
T4	6812	930	0	0
T5	2175032	455230	0	0
T6	0	298816	0	0
T11	1602828	514600	0	0
T12	14512	424	0	0
T16	13932	64	0	0
T17	12000	64	0	0
T18	5648	106	0	0
T19	0	1680	0	0
T24	0	150	0	0
T39	0	446	0	0
T54	0	228	0	0
T58	0	218460	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	399317062	0	0
T1	1540192	514600	0	0
T2	597612	30248	0	0
T3	845420	177788	0	0
T4	6812	930	0	0
T5	2175032	32004	0	0
T6	0	48588	0	0
T11	1602828	514600	0	0
T12	14512	424	0	0
T16	13932	64	0	0
T17	12000	64	0	0
T18	5648	106	0	0
T19	0	1680	0	0
T24	0	150	0	0
T39	0	446	0	0
T54	0	228	0	0
T58	0	218460	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	399317062	0	0
T1	1540192	514600	0	0
T2	597612	30248	0	0
T3	845420	177788	0	0
T4	6812	930	0	0
T5	2175032	32004	0	0
T6	0	48588	0	0
T11	1602828	514600	0	0
T12	14512	424	0	0
T16	13932	64	0	0
T17	12000	64	0	0
T18	5648	106	0	0
T19	0	1680	0	0
T24	0	150	0	0
T39	0	446	0	0
T54	0	228	0	0
T58	0	218460	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	423965726	0	0
T1	1540192	514600	0	0
T2	597612	30248	0	0
T3	845420	177788	0	0
T4	6812	930	0	0
T5	2175032	455230	0	0
T6	0	298816	0	0
T11	1602828	514600	0	0
T12	14512	424	0	0
T16	13932	64	0	0
T17	12000	64	0	0
T18	5648	106	0	0
T19	0	1680	0	0
T24	0	150	0	0
T39	0	446	0	0
T54	0	228	0	0
T58	0	218460	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1637906816	1634525708	0	0
T1	1540192	1540132	0	0
T2	597612	597272	0	0
T3	845420	806444	0	0
T4	6812	6572	0	0
T5	2175032	2174356	0	0
T11	1602828	1602756	0	0
T12	14512	11984	0	0
T16	13932	13616	0	0
T17	12000	11636	0	0
T18	5648	5388	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409476704	408631427	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	409476704	97589130	0	0
GntImpliesValid_A	409476704	97589130	0	0
GrantKnown_A	409476704	408631427	0	0
IdxKnown_A	409476704	408631427	0	0
IndexIsCorrect_A	409476704	97589130	0	0
NoReadyValidNoGrant_A	409476704	47148823	0	0
Priority_A	409476704	103880772	0	0
ReadyAndValidImplyGrant_A	409476704	97589130	0	0
ReqAndReadyImplyGrant_A	409476704	97589130	0	0
ReqImpliesValid_A	409476704	103880772	0	0
ValidKnown_A	409476704	408631427	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	97589130	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	7979	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	97589130	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	7979	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	97589130	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	7979	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	47148823	0	0
T1	385048	530688	0	0
T2	149403	2688	0	0
T3	211355	24240	0	0
T4	1703	132	0	0
T5	543758	299757	0	0
T11	400707	530688	0	0
T12	3628	800	0	0
T16	3483	128	0	0
T17	3000	128	0	0
T18	1412	160	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	103880772	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	112016	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	97589130	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	7979	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	97589130	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	7979	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	103880772	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	112016	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409476704	408631427	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	409476704	97589130	0	0
GntImpliesValid_A	409476704	97589130	0	0
GrantKnown_A	409476704	408631427	0	0
IdxKnown_A	409476704	408631427	0	0
IndexIsCorrect_A	409476704	97589130	0	0
NoReadyValidNoGrant_A	409476704	47148823	0	0
Priority_A	409476704	103880772	0	0
ReadyAndValidImplyGrant_A	409476704	97589130	0	0
ReqAndReadyImplyGrant_A	409476704	97589130	0	0
ReqImpliesValid_A	409476704	103880772	0	0
ValidKnown_A	409476704	408631427	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	97589130	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	7979	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	97589130	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	7979	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	97589130	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	7979	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	47148823	0	0
T1	385048	530688	0	0
T2	149403	2688	0	0
T3	211355	24240	0	0
T4	1703	132	0	0
T5	543758	299757	0	0
T11	400707	530688	0	0
T12	3628	800	0	0
T16	3483	128	0	0
T17	3000	128	0	0
T18	1412	160	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	103880772	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	112016	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	97589130	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	7979	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	97589130	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	7979	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	103880772	0	0
T1	385048	129403	0	0
T2	149403	15124	0	0
T3	211355	88894	0	0
T4	1703	462	0	0
T5	543758	112016	0	0
T11	400707	129403	0	0
T12	3628	212	0	0
T16	3483	32	0	0
T17	3000	32	0	0
T18	1412	53	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T4
1	0	Covered	T5,T6,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T1,T11,T4
1	1	Covered	T5,T6,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T11,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T11,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409476704	408631427	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	409476704	102069401	0	0
GntImpliesValid_A	409476704	102069401	0	0
GrantKnown_A	409476704	408631427	0	0
IdxKnown_A	409476704	408631427	0	0
IndexIsCorrect_A	409476704	102069401	0	0
NoReadyValidNoGrant_A	409476704	44911526	0	0
Priority_A	409476704	108102091	0	0
ReadyAndValidImplyGrant_A	409476704	102069401	0	0
ReqAndReadyImplyGrant_A	409476704	102069401	0	0
ReqImpliesValid_A	409476704	108102091	0	0
ValidKnown_A	409476704	408631427	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	102069401	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	8023	0	0
T6	0	24294	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	102069401	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	8023	0	0
T6	0	24294	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	102069401	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	8023	0	0
T6	0	24294	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	44911526	0	0
T1	385048	524288	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	5	0	0
T5	543758	297650	0	0
T6	0	719291	0	0
T7	0	24303	0	0
T11	400707	524288	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	153	0	0
T20	0	14	0	0
T24	0	30	0	0
T40	0	524347	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	108102091	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	115599	0	0
T6	0	149408	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	102069401	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	8023	0	0
T6	0	24294	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	102069401	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	8023	0	0
T6	0	24294	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	108102091	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	115599	0	0
T6	0	149408	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T4
1	0	Covered	T5,T6,T19

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T1,T11,T4
1	1	Covered	T5,T6,T19

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T11,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T11,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T19

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T19

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409476704	408631427	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	409476704	102069401	0	0
GntImpliesValid_A	409476704	102069401	0	0
GrantKnown_A	409476704	408631427	0	0
IdxKnown_A	409476704	408631427	0	0
IndexIsCorrect_A	409476704	102069401	0	0
NoReadyValidNoGrant_A	409476704	44911526	0	0
Priority_A	409476704	108102091	0	0
ReadyAndValidImplyGrant_A	409476704	102069401	0	0
ReqAndReadyImplyGrant_A	409476704	102069401	0	0
ReqImpliesValid_A	409476704	108102091	0	0
ValidKnown_A	409476704	408631427	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	102069401	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	8023	0	0
T6	0	24294	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	102069401	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	8023	0	0
T6	0	24294	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	102069401	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	8023	0	0
T6	0	24294	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	44911526	0	0
T1	385048	524288	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	5	0	0
T5	543758	297650	0	0
T6	0	719291	0	0
T7	0	24303	0	0
T11	400707	524288	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	153	0	0
T20	0	14	0	0
T24	0	30	0	0
T40	0	524347	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	108102091	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	115599	0	0
T6	0	149408	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	102069401	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	8023	0	0
T6	0	24294	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	102069401	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	8023	0	0
T6	0	24294	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	108102091	0	0
T1	385048	127897	0	0
T2	149403	0	0	0
T3	211355	0	0	0
T4	1703	3	0	0
T5	543758	115599	0	0
T6	0	149408	0	0
T11	400707	127897	0	0
T12	3628	0	0	0
T16	3483	0	0	0
T17	3000	0	0	0
T18	1412	0	0	0
T19	0	840	0	0
T24	0	75	0	0
T39	0	223	0	0
T54	0	114	0	0
T58	0	109230	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409476704	408631427	0	0
T1	385048	385033	0	0
T2	149403	149318	0	0
T3	211355	201611	0	0
T4	1703	1643	0	0
T5	543758	543589	0	0
T11	400707	400689	0	0
T12	3628	2996	0	0
T16	3483	3404	0	0
T17	3000	2909	0	0
T18	1412	1347	0	0