Line Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
flash_phy_rd_buffers
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T20,T40,T70 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T19,T24 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T20,T40,T70 |
0 |
0 |
1 |
- |
- |
Covered |
T3,T19,T24 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T3,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buffers
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5407832 |
0 |
0 |
T2 |
597612 |
512 |
0 |
0 |
T3 |
845420 |
1488 |
0 |
0 |
T4 |
10218 |
4 |
0 |
0 |
T5 |
4350064 |
15950 |
0 |
0 |
T6 |
1010360 |
31168 |
0 |
0 |
T7 |
0 |
19120 |
0 |
0 |
T11 |
1602828 |
0 |
0 |
0 |
T12 |
29024 |
0 |
0 |
0 |
T16 |
13932 |
0 |
0 |
0 |
T17 |
12000 |
0 |
0 |
0 |
T18 |
11296 |
11 |
0 |
0 |
T19 |
27968 |
120 |
0 |
0 |
T20 |
0 |
5 |
0 |
0 |
T21 |
0 |
20484 |
0 |
0 |
T24 |
8096 |
27 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T30 |
904856 |
0 |
0 |
0 |
T36 |
0 |
112 |
0 |
0 |
T39 |
9656 |
0 |
0 |
0 |
T40 |
0 |
58 |
0 |
0 |
T46 |
5584 |
0 |
0 |
0 |
T54 |
4440 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5407828 |
0 |
0 |
T2 |
597612 |
512 |
0 |
0 |
T3 |
845420 |
1488 |
0 |
0 |
T4 |
10218 |
4 |
0 |
0 |
T5 |
4350064 |
15950 |
0 |
0 |
T6 |
1010360 |
31168 |
0 |
0 |
T7 |
0 |
19120 |
0 |
0 |
T11 |
1602828 |
0 |
0 |
0 |
T12 |
29024 |
0 |
0 |
0 |
T16 |
13932 |
0 |
0 |
0 |
T17 |
12000 |
0 |
0 |
0 |
T18 |
11296 |
11 |
0 |
0 |
T19 |
27968 |
120 |
0 |
0 |
T20 |
0 |
5 |
0 |
0 |
T21 |
0 |
20484 |
0 |
0 |
T24 |
8096 |
27 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T30 |
904856 |
0 |
0 |
0 |
T36 |
0 |
112 |
0 |
0 |
T39 |
9656 |
0 |
0 |
0 |
T40 |
0 |
58 |
0 |
0 |
T46 |
5584 |
0 |
0 |
0 |
T54 |
4440 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T40,T71,T72 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T19,T40 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T40,T71,T72 |
0 |
0 |
1 |
- |
- |
Covered |
T3,T19,T40 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T3,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
620616 |
0 |
0 |
T2 |
149403 |
128 |
0 |
0 |
T3 |
211355 |
372 |
0 |
0 |
T4 |
1703 |
1 |
0 |
0 |
T5 |
543758 |
1986 |
0 |
0 |
T6 |
126295 |
3669 |
0 |
0 |
T7 |
0 |
2749 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
3 |
0 |
0 |
T19 |
0 |
23 |
0 |
0 |
T24 |
0 |
5 |
0 |
0 |
T40 |
0 |
10 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
620615 |
0 |
0 |
T2 |
149403 |
128 |
0 |
0 |
T3 |
211355 |
372 |
0 |
0 |
T4 |
1703 |
1 |
0 |
0 |
T5 |
543758 |
1986 |
0 |
0 |
T6 |
126295 |
3669 |
0 |
0 |
T7 |
0 |
2749 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
3 |
0 |
0 |
T19 |
0 |
23 |
0 |
0 |
T24 |
0 |
5 |
0 |
0 |
T40 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T40,T71,T72 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T19,T40 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T40,T71,T72 |
0 |
0 |
1 |
- |
- |
Covered |
T3,T19,T40 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T3,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
620238 |
0 |
0 |
T2 |
149403 |
128 |
0 |
0 |
T3 |
211355 |
372 |
0 |
0 |
T4 |
1703 |
1 |
0 |
0 |
T5 |
543758 |
1986 |
0 |
0 |
T6 |
126295 |
3671 |
0 |
0 |
T7 |
0 |
2760 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
3 |
0 |
0 |
T19 |
0 |
23 |
0 |
0 |
T24 |
0 |
5 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
620238 |
0 |
0 |
T2 |
149403 |
128 |
0 |
0 |
T3 |
211355 |
372 |
0 |
0 |
T4 |
1703 |
1 |
0 |
0 |
T5 |
543758 |
1986 |
0 |
0 |
T6 |
126295 |
3671 |
0 |
0 |
T7 |
0 |
2760 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
3 |
0 |
0 |
T19 |
0 |
23 |
0 |
0 |
T24 |
0 |
5 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T40,T71,T72 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T5 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T19,T24 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T5 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T5 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T40,T71,T72 |
0 |
0 |
1 |
- |
- |
Covered |
T3,T19,T24 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T3,T5 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T5 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
620123 |
0 |
0 |
T2 |
149403 |
128 |
0 |
0 |
T3 |
211355 |
372 |
0 |
0 |
T4 |
1703 |
0 |
0 |
0 |
T5 |
543758 |
1985 |
0 |
0 |
T6 |
126295 |
3674 |
0 |
0 |
T7 |
0 |
2763 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
3 |
0 |
0 |
T19 |
0 |
21 |
0 |
0 |
T24 |
0 |
5 |
0 |
0 |
T36 |
0 |
24 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
620123 |
0 |
0 |
T2 |
149403 |
128 |
0 |
0 |
T3 |
211355 |
372 |
0 |
0 |
T4 |
1703 |
0 |
0 |
0 |
T5 |
543758 |
1985 |
0 |
0 |
T6 |
126295 |
3674 |
0 |
0 |
T7 |
0 |
2763 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
3 |
0 |
0 |
T19 |
0 |
21 |
0 |
0 |
T24 |
0 |
5 |
0 |
0 |
T36 |
0 |
24 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T40,T71,T72 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T5 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T19,T24 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T5 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T5 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T40,T71,T72 |
0 |
0 |
1 |
- |
- |
Covered |
T3,T19,T24 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T3,T5 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T5 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
619829 |
0 |
0 |
T2 |
149403 |
128 |
0 |
0 |
T3 |
211355 |
372 |
0 |
0 |
T4 |
1703 |
0 |
0 |
0 |
T5 |
543758 |
1985 |
0 |
0 |
T6 |
126295 |
3675 |
0 |
0 |
T7 |
0 |
2754 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
2 |
0 |
0 |
T19 |
0 |
20 |
0 |
0 |
T24 |
0 |
5 |
0 |
0 |
T36 |
0 |
24 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
619829 |
0 |
0 |
T2 |
149403 |
128 |
0 |
0 |
T3 |
211355 |
372 |
0 |
0 |
T4 |
1703 |
0 |
0 |
0 |
T5 |
543758 |
1985 |
0 |
0 |
T6 |
126295 |
3675 |
0 |
0 |
T7 |
0 |
2754 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
2 |
0 |
0 |
T19 |
0 |
20 |
0 |
0 |
T24 |
0 |
5 |
0 |
0 |
T36 |
0 |
24 |
0 |
0 |
T40 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T20,T40,T70 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T40,T34,T66 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T20,T40,T70 |
0 |
0 |
1 |
- |
- |
Covered |
T40,T34,T66 |
0 |
0 |
0 |
1 |
- |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
731817 |
0 |
0 |
T4 |
1703 |
1 |
0 |
0 |
T5 |
543758 |
2002 |
0 |
0 |
T6 |
126295 |
4115 |
0 |
0 |
T7 |
0 |
2024 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
9 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
5123 |
0 |
0 |
T24 |
2024 |
2 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
19 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
6 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
731817 |
0 |
0 |
T4 |
1703 |
1 |
0 |
0 |
T5 |
543758 |
2002 |
0 |
0 |
T6 |
126295 |
4115 |
0 |
0 |
T7 |
0 |
2024 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
9 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
5123 |
0 |
0 |
T24 |
2024 |
2 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
19 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
6 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T20,T40,T70 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T5,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T24,T40,T34 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T20,T40,T70 |
0 |
0 |
1 |
- |
- |
Covered |
T24,T40,T34 |
0 |
0 |
0 |
1 |
- |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
732126 |
0 |
0 |
T4 |
1703 |
1 |
0 |
0 |
T5 |
543758 |
2004 |
0 |
0 |
T6 |
126295 |
4121 |
0 |
0 |
T7 |
0 |
2024 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
8 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
5123 |
0 |
0 |
T24 |
2024 |
2 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
19 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
732126 |
0 |
0 |
T4 |
1703 |
1 |
0 |
0 |
T5 |
543758 |
2004 |
0 |
0 |
T6 |
126295 |
4121 |
0 |
0 |
T7 |
0 |
2024 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
8 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
5123 |
0 |
0 |
T24 |
2024 |
2 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
19 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T20,T40,T73 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T19 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T40,T34,T74 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T6,T19 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T6,T19 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T20,T40,T73 |
0 |
0 |
1 |
- |
- |
Covered |
T40,T34,T74 |
0 |
0 |
0 |
1 |
- |
Covered |
T5,T6,T19 |
0 |
0 |
0 |
0 |
1 |
Covered |
T5,T6,T19 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
731590 |
0 |
0 |
T5 |
543758 |
2003 |
0 |
0 |
T6 |
126295 |
4116 |
0 |
0 |
T7 |
0 |
2023 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
8 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
5118 |
0 |
0 |
T24 |
2024 |
2 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
11 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
731589 |
0 |
0 |
T5 |
543758 |
2003 |
0 |
0 |
T6 |
126295 |
4116 |
0 |
0 |
T7 |
0 |
2023 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
8 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
5118 |
0 |
0 |
T24 |
2024 |
2 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
11 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T20,T40,T73 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T19 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T40,T34,T66 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T6,T19 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T6,T19 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T20,T40,T73 |
0 |
0 |
1 |
- |
- |
Covered |
T40,T34,T66 |
0 |
0 |
0 |
1 |
- |
Covered |
T5,T6,T19 |
0 |
0 |
0 |
0 |
1 |
Covered |
T5,T6,T19 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
731493 |
0 |
0 |
T5 |
543758 |
1999 |
0 |
0 |
T6 |
126295 |
4127 |
0 |
0 |
T7 |
0 |
2023 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
8 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
5120 |
0 |
0 |
T24 |
2024 |
1 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
15 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
731491 |
0 |
0 |
T5 |
543758 |
1999 |
0 |
0 |
T6 |
126295 |
4127 |
0 |
0 |
T7 |
0 |
2023 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
8 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
5120 |
0 |
0 |
T24 |
2024 |
1 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
15 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |