Line Coverage for Module :
prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Line Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
2 |
2 |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 43 | 43 | 100.00 |
Logical | 43 | 43 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T69 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T7,T21,T61 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Unreachable | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | T68,T69 |
1 | 0 | 1 | Unreachable | T7,T21,T61 |
1 | 1 | 0 | Covered | T1,T11,T19 |
1 | 1 | 1 | Unreachable | T1,T11,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Unreachable | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T11,T19 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T21,T61 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T21,T61 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T11,T19 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Cond Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 51 | 50 | 98.04 |
Logical | 51 | 50 | 98.04 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T67,T154 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T67,T154 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T67,T154 |
1 | 0 | 1 | Covered | T67,T154 |
1 | 1 | 0 | Covered | T1,T11,T19 |
1 | 1 | 1 | Covered | T1,T11,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T11,T19 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T67,T154,T196 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T67,T154 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T11,T19 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Cond Coverage for Module :
prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T5,T6 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T5,T6 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T5,T6 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T197,T198,T199 |
1 | 1 | Covered | T2,T3,T5 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T5 |
1 | 1 | 0 | Covered | T2,T3,T5 |
1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T5 |
1 | 1 | 0 | Covered | T2,T3,T5 |
1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T5 |
1 | 1 | 0 | Covered | T2,T3,T5 |
1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T5 |
1 | 1 | 0 | Covered | T2,T3,T5 |
1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T61,T41 |
1 | 0 | Covered | T7,T61,T41 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T61,T41 |
1 | 0 | Covered | T2,T3,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T21 |
1 | 0 | Covered | T2,T3,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T19,T7 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
Branch Coverage for Module :
prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_arbiter_tree
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2310288 |
2310198 |
0 |
0 |
T2 |
896418 |
895908 |
0 |
0 |
T3 |
1268130 |
1209666 |
0 |
0 |
T4 |
10218 |
9858 |
0 |
0 |
T5 |
3262548 |
3261534 |
0 |
0 |
T11 |
2404242 |
2404134 |
0 |
0 |
T12 |
21768 |
17976 |
0 |
0 |
T16 |
20898 |
20424 |
0 |
0 |
T17 |
18000 |
17454 |
0 |
0 |
T18 |
8472 |
8082 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6264 |
6264 |
0 |
0 |
T1 |
6 |
6 |
0 |
0 |
T2 |
6 |
6 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
6 |
6 |
0 |
0 |
T5 |
6 |
6 |
0 |
0 |
T11 |
6 |
6 |
0 |
0 |
T12 |
6 |
6 |
0 |
0 |
T16 |
6 |
6 |
0 |
0 |
T17 |
6 |
6 |
0 |
0 |
T18 |
6 |
6 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
72549014 |
0 |
0 |
T1 |
1540192 |
1582336 |
0 |
0 |
T2 |
747015 |
3708 |
0 |
0 |
T3 |
1056775 |
26140 |
0 |
0 |
T4 |
8515 |
128 |
0 |
0 |
T5 |
3262548 |
16088 |
0 |
0 |
T6 |
252590 |
31160 |
0 |
0 |
T7 |
0 |
19112 |
0 |
0 |
T11 |
2003535 |
1582336 |
0 |
0 |
T12 |
21768 |
800 |
0 |
0 |
T16 |
17415 |
128 |
0 |
0 |
T17 |
15000 |
128 |
0 |
0 |
T18 |
8472 |
135 |
0 |
0 |
T19 |
6992 |
103 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
20480 |
0 |
0 |
T24 |
2024 |
16 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
94 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
42 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
72549014 |
0 |
0 |
T1 |
1540192 |
1582336 |
0 |
0 |
T2 |
747015 |
3708 |
0 |
0 |
T3 |
1056775 |
26140 |
0 |
0 |
T4 |
8515 |
128 |
0 |
0 |
T5 |
3262548 |
16088 |
0 |
0 |
T6 |
252590 |
31160 |
0 |
0 |
T7 |
0 |
19112 |
0 |
0 |
T11 |
2003535 |
1582336 |
0 |
0 |
T12 |
21768 |
800 |
0 |
0 |
T16 |
17415 |
128 |
0 |
0 |
T17 |
15000 |
128 |
0 |
0 |
T18 |
8472 |
135 |
0 |
0 |
T19 |
6992 |
103 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
20480 |
0 |
0 |
T24 |
2024 |
16 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
94 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
42 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2310288 |
2310198 |
0 |
0 |
T2 |
896418 |
895908 |
0 |
0 |
T3 |
1268130 |
1209666 |
0 |
0 |
T4 |
10218 |
9858 |
0 |
0 |
T5 |
3262548 |
3261534 |
0 |
0 |
T11 |
2404242 |
2404134 |
0 |
0 |
T12 |
21768 |
17976 |
0 |
0 |
T16 |
20898 |
20424 |
0 |
0 |
T17 |
18000 |
17454 |
0 |
0 |
T18 |
8472 |
8082 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2310288 |
2310198 |
0 |
0 |
T2 |
896418 |
895908 |
0 |
0 |
T3 |
1268130 |
1209666 |
0 |
0 |
T4 |
10218 |
9858 |
0 |
0 |
T5 |
3262548 |
3261534 |
0 |
0 |
T11 |
2404242 |
2404134 |
0 |
0 |
T12 |
21768 |
17976 |
0 |
0 |
T16 |
20898 |
20424 |
0 |
0 |
T17 |
18000 |
17454 |
0 |
0 |
T18 |
8472 |
8082 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
72549014 |
0 |
0 |
T1 |
1540192 |
1582336 |
0 |
0 |
T2 |
747015 |
3708 |
0 |
0 |
T3 |
1056775 |
26140 |
0 |
0 |
T4 |
8515 |
128 |
0 |
0 |
T5 |
3262548 |
16088 |
0 |
0 |
T6 |
252590 |
31160 |
0 |
0 |
T7 |
0 |
19112 |
0 |
0 |
T11 |
2003535 |
1582336 |
0 |
0 |
T12 |
21768 |
800 |
0 |
0 |
T16 |
17415 |
128 |
0 |
0 |
T17 |
15000 |
128 |
0 |
0 |
T18 |
8472 |
135 |
0 |
0 |
T19 |
6992 |
103 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
20480 |
0 |
0 |
T24 |
2024 |
16 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
94 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
42 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
67357870 |
0 |
0 |
T1 |
1540192 |
1582336 |
0 |
0 |
T2 |
597612 |
3200 |
0 |
0 |
T3 |
845420 |
25536 |
0 |
0 |
T4 |
6812 |
128 |
0 |
0 |
T5 |
2175032 |
146 |
0 |
0 |
T11 |
1602828 |
1582336 |
0 |
0 |
T12 |
14512 |
800 |
0 |
0 |
T16 |
13932 |
128 |
0 |
0 |
T17 |
12000 |
128 |
0 |
0 |
T18 |
5648 |
128 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2082777587 |
0 |
0 |
T1 |
2310288 |
1967356 |
0 |
0 |
T2 |
896418 |
740540 |
0 |
0 |
T3 |
1268130 |
1073645 |
0 |
0 |
T4 |
10218 |
9566 |
0 |
0 |
T5 |
3262548 |
2178902 |
0 |
0 |
T11 |
2404242 |
2061296 |
0 |
0 |
T12 |
21768 |
16176 |
0 |
0 |
T16 |
20898 |
20136 |
0 |
0 |
T17 |
18000 |
17166 |
0 |
0 |
T18 |
8472 |
6959 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
72549014 |
0 |
0 |
T1 |
1540192 |
1582336 |
0 |
0 |
T2 |
747015 |
3708 |
0 |
0 |
T3 |
1056775 |
26140 |
0 |
0 |
T4 |
8515 |
128 |
0 |
0 |
T5 |
3262548 |
16088 |
0 |
0 |
T6 |
252590 |
31160 |
0 |
0 |
T7 |
0 |
19112 |
0 |
0 |
T11 |
2003535 |
1582336 |
0 |
0 |
T12 |
21768 |
800 |
0 |
0 |
T16 |
17415 |
128 |
0 |
0 |
T17 |
15000 |
128 |
0 |
0 |
T18 |
8472 |
135 |
0 |
0 |
T19 |
6992 |
103 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
20480 |
0 |
0 |
T24 |
2024 |
16 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
94 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
42 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
72549014 |
0 |
0 |
T1 |
1540192 |
1582336 |
0 |
0 |
T2 |
747015 |
3708 |
0 |
0 |
T3 |
1056775 |
26140 |
0 |
0 |
T4 |
8515 |
128 |
0 |
0 |
T5 |
3262548 |
16088 |
0 |
0 |
T6 |
252590 |
31160 |
0 |
0 |
T7 |
0 |
19112 |
0 |
0 |
T11 |
2003535 |
1582336 |
0 |
0 |
T12 |
21768 |
800 |
0 |
0 |
T16 |
17415 |
128 |
0 |
0 |
T17 |
15000 |
128 |
0 |
0 |
T18 |
8472 |
135 |
0 |
0 |
T19 |
6992 |
103 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
20480 |
0 |
0 |
T24 |
2024 |
16 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
94 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
42 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
358464953 |
0 |
0 |
T1 |
1540192 |
3164672 |
0 |
0 |
T2 |
747015 |
155332 |
0 |
0 |
T3 |
1056775 |
130977 |
0 |
0 |
T4 |
8515 |
256 |
0 |
0 |
T5 |
3262548 |
1082587 |
0 |
0 |
T6 |
252590 |
252101 |
0 |
0 |
T7 |
0 |
102556 |
0 |
0 |
T11 |
2003535 |
3164672 |
0 |
0 |
T12 |
21768 |
1600 |
0 |
0 |
T16 |
17415 |
256 |
0 |
0 |
T17 |
15000 |
256 |
0 |
0 |
T18 |
8472 |
1087 |
0 |
0 |
T19 |
6992 |
10026 |
0 |
0 |
T20 |
0 |
13 |
0 |
0 |
T21 |
0 |
310662 |
0 |
0 |
T24 |
2024 |
1198 |
0 |
0 |
T25 |
0 |
781 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
1614 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
700487 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
67357144 |
0 |
0 |
T1 |
1540192 |
1582336 |
0 |
0 |
T2 |
597612 |
3200 |
0 |
0 |
T3 |
845420 |
25536 |
0 |
0 |
T4 |
6812 |
128 |
0 |
0 |
T5 |
2175032 |
146 |
0 |
0 |
T11 |
1602828 |
1582336 |
0 |
0 |
T12 |
14512 |
800 |
0 |
0 |
T16 |
13932 |
128 |
0 |
0 |
T17 |
12000 |
128 |
0 |
0 |
T18 |
5648 |
128 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
6234 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2310288 |
2310198 |
0 |
0 |
T2 |
896418 |
895908 |
0 |
0 |
T3 |
1268130 |
1209666 |
0 |
0 |
T4 |
10218 |
9858 |
0 |
0 |
T5 |
3262548 |
3261534 |
0 |
0 |
T11 |
2404242 |
2404134 |
0 |
0 |
T12 |
21768 |
17976 |
0 |
0 |
T16 |
20898 |
20424 |
0 |
0 |
T17 |
18000 |
17454 |
0 |
0 |
T18 |
8472 |
8082 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1637906816 |
67358173 |
0 |
0 |
T1 |
1540192 |
1582336 |
0 |
0 |
T2 |
597612 |
3200 |
0 |
0 |
T3 |
845420 |
25536 |
0 |
0 |
T4 |
6812 |
128 |
0 |
0 |
T5 |
2175032 |
146 |
0 |
0 |
T11 |
1602828 |
1582336 |
0 |
0 |
T12 |
14512 |
800 |
0 |
0 |
T16 |
13932 |
128 |
0 |
0 |
T17 |
12000 |
128 |
0 |
0 |
T18 |
5648 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T6,T19 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T6,T19 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T6,T19 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T197,T198,T199 |
1 | 1 | Covered | T2,T3,T5 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T5 |
1 | 1 | 0 | Covered | T2,T3,T5 |
1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T5 |
1 | 1 | 0 | Covered | T2,T3,T5 |
1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T5 |
1 | 1 | 0 | Covered | T2,T3,T5 |
1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T2,T3,T5 |
1 | 1 | 0 | Covered | T2,T3,T5 |
1 | 1 | 1 | Covered | T2,T3,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T5 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T61,T41 |
1 | 0 | Covered | T7,T61,T41 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T61,T41 |
1 | 0 | Covered | T2,T3,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T21 |
1 | 0 | Covered | T2,T3,T5 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T2,T3,T5 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T5 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T2,T3,T5 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T19,T7 |
1 | 0 | Covered | T2,T3,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T2,T3,T5 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T5 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1044 |
1044 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
2345612 |
0 |
0 |
T2 |
149403 |
508 |
0 |
0 |
T3 |
211355 |
604 |
0 |
0 |
T4 |
1703 |
0 |
0 |
0 |
T5 |
543758 |
7938 |
0 |
0 |
T6 |
126295 |
14685 |
0 |
0 |
T7 |
0 |
11022 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
7 |
0 |
0 |
T19 |
0 |
74 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
29 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
2345612 |
0 |
0 |
T2 |
149403 |
508 |
0 |
0 |
T3 |
211355 |
604 |
0 |
0 |
T4 |
1703 |
0 |
0 |
0 |
T5 |
543758 |
7938 |
0 |
0 |
T6 |
126295 |
14685 |
0 |
0 |
T7 |
0 |
11022 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
7 |
0 |
0 |
T19 |
0 |
74 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
29 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
2345612 |
0 |
0 |
T2 |
149403 |
508 |
0 |
0 |
T3 |
211355 |
604 |
0 |
0 |
T4 |
1703 |
0 |
0 |
0 |
T5 |
543758 |
7938 |
0 |
0 |
T6 |
126295 |
14685 |
0 |
0 |
T7 |
0 |
11022 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
7 |
0 |
0 |
T19 |
0 |
74 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
29 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
294980816 |
0 |
0 |
T1 |
385048 |
371766 |
0 |
0 |
T2 |
149403 |
350 |
0 |
0 |
T3 |
211355 |
116662 |
0 |
0 |
T4 |
1703 |
1609 |
0 |
0 |
T5 |
543758 |
2349 |
0 |
0 |
T11 |
400707 |
387422 |
0 |
0 |
T12 |
3628 |
2796 |
0 |
0 |
T16 |
3483 |
3372 |
0 |
0 |
T17 |
3000 |
2877 |
0 |
0 |
T18 |
1412 |
480 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
2345612 |
0 |
0 |
T2 |
149403 |
508 |
0 |
0 |
T3 |
211355 |
604 |
0 |
0 |
T4 |
1703 |
0 |
0 |
0 |
T5 |
543758 |
7938 |
0 |
0 |
T6 |
126295 |
14685 |
0 |
0 |
T7 |
0 |
11022 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
7 |
0 |
0 |
T19 |
0 |
74 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
29 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
2345612 |
0 |
0 |
T2 |
149403 |
508 |
0 |
0 |
T3 |
211355 |
604 |
0 |
0 |
T4 |
1703 |
0 |
0 |
0 |
T5 |
543758 |
7938 |
0 |
0 |
T6 |
126295 |
14685 |
0 |
0 |
T7 |
0 |
11022 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
7 |
0 |
0 |
T19 |
0 |
74 |
0 |
0 |
T24 |
0 |
14 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
29 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
107810269 |
0 |
0 |
T2 |
149403 |
148932 |
0 |
0 |
T3 |
211355 |
79905 |
0 |
0 |
T4 |
1703 |
0 |
0 |
0 |
T5 |
543758 |
541199 |
0 |
0 |
T6 |
126295 |
126050 |
0 |
0 |
T7 |
0 |
51292 |
0 |
0 |
T11 |
400707 |
0 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T16 |
3483 |
0 |
0 |
0 |
T17 |
3000 |
0 |
0 |
0 |
T18 |
1412 |
831 |
0 |
0 |
T19 |
0 |
4399 |
0 |
0 |
T24 |
0 |
442 |
0 |
0 |
T36 |
0 |
1387 |
0 |
0 |
T40 |
0 |
392057 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
0 |
0 |
1039 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
TOTAL | | 52 | 48 | 92.31 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
4 |
4 |
118 |
4 |
4 |
122 |
0 |
4 |
126 |
4 |
4 |
128 |
4 |
4 |
148 |
3 |
3 |
150 |
3 |
3 |
151 |
3 |
3 |
155 |
3 |
3 |
156 |
3 |
3 |
160 |
3 |
3 |
161 |
3 |
3 |
163 |
1 |
1(2 unreachable) |
164 |
3 |
3 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Total | Covered | Percent |
Conditions | 130 | 127 | 97.69 |
Logical | 130 | 127 | 97.69 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T36 |
1 | 0 | Covered | T5,T6,T19 |
1 | 1 | Covered | T5,T6,T19 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T24 |
1 | 0 | Covered | T5,T6,T19 |
1 | 1 | Covered | T5,T6,T19 |
LINE 118
EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T24 |
1 | 0 | Covered | T5,T6,T19 |
1 | 1 | Covered | T5,T6,T19 |
LINE 118
EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T197,T198,T199 |
1 | 1 | Covered | T5,T6,T19 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T5,T6,T19 |
1 | 1 | 0 | Covered | T5,T6,T19 |
1 | 1 | 1 | Covered | T5,T6,T19 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T5,T6,T19 |
1 | 1 | 0 | Covered | T5,T6,T19 |
1 | 1 | 1 | Covered | T5,T6,T19 |
LINE 126
EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T5,T6,T19 |
1 | 1 | 0 | Covered | T5,T6,T19 |
1 | 1 | 1 | Covered | T5,T6,T19 |
LINE 126
EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T11,T4 |
1 | 0 | 1 | Covered | T5,T6,T19 |
1 | 1 | 0 | Covered | T5,T6,T19 |
1 | 1 | 1 | Covered | T5,T6,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T19 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T19 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
1 | 1 | Covered | T5,T6,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T19 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T19 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
1 | 1 | Covered | T5,T6,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T19 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T19 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
1 | 1 | Covered | T5,T6,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T19 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T19 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
1 | 1 | Covered | T5,T6,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T19 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T19 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T19 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T19 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T61,T41 |
1 | 0 | Covered | T7,T61,T41 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T61,T41 |
1 | 0 | Covered | T5,T6,T19 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T21,T61 |
1 | 0 | Covered | T5,T6,T19 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T5,T6,T19 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T5,T6,T19 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T5,T6,T19 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T5,T6,T19 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T5,T6,T19 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1- | Status | Tests |
0 | Covered | T5,T6,T19 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T19 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
1 | 1 | Covered | T5,T6,T19 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T19 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T5,T6,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T19 |
1 | 1 | Covered | T5,T6,T19 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T21 |
1 | 0 | Covered | T5,T6,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Unreachable | |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T19 |
1 | 0 | Covered | T5,T6,T19 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
22 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T6,T19 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T6,T19 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T6,T19 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T6,T19 |
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T6,T19 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T6,T19 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T19 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1044 |
1044 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
2845229 |
0 |
0 |
T5 |
543758 |
8004 |
0 |
0 |
T6 |
126295 |
16475 |
0 |
0 |
T7 |
0 |
8090 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
29 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
20480 |
0 |
0 |
T24 |
2024 |
2 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
9 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
13 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
2845229 |
0 |
0 |
T5 |
543758 |
8004 |
0 |
0 |
T6 |
126295 |
16475 |
0 |
0 |
T7 |
0 |
8090 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
29 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
20480 |
0 |
0 |
T24 |
2024 |
2 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
9 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
13 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
2845229 |
0 |
0 |
T5 |
543758 |
8004 |
0 |
0 |
T6 |
126295 |
16475 |
0 |
0 |
T7 |
0 |
8090 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
29 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
20480 |
0 |
0 |
T24 |
2024 |
2 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
9 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
13 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
0 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
287987692 |
0 |
0 |
T1 |
385048 |
371926 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1641 |
0 |
0 |
T5 |
543758 |
2489 |
0 |
0 |
T11 |
400707 |
387582 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
2845229 |
0 |
0 |
T5 |
543758 |
8004 |
0 |
0 |
T6 |
126295 |
16475 |
0 |
0 |
T7 |
0 |
8090 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
29 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
20480 |
0 |
0 |
T24 |
2024 |
2 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
9 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
13 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
2845229 |
0 |
0 |
T5 |
543758 |
8004 |
0 |
0 |
T6 |
126295 |
16475 |
0 |
0 |
T7 |
0 |
8090 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
29 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
20480 |
0 |
0 |
T24 |
2024 |
2 |
0 |
0 |
T25 |
0 |
9 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
9 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
13 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
115938208 |
0 |
0 |
T5 |
543758 |
541096 |
0 |
0 |
T6 |
126295 |
126051 |
0 |
0 |
T7 |
0 |
51264 |
0 |
0 |
T12 |
3628 |
0 |
0 |
0 |
T18 |
1412 |
0 |
0 |
0 |
T19 |
6992 |
5627 |
0 |
0 |
T20 |
0 |
13 |
0 |
0 |
T21 |
0 |
310662 |
0 |
0 |
T24 |
2024 |
756 |
0 |
0 |
T25 |
0 |
781 |
0 |
0 |
T30 |
226214 |
0 |
0 |
0 |
T36 |
0 |
227 |
0 |
0 |
T39 |
2414 |
0 |
0 |
0 |
T40 |
0 |
308430 |
0 |
0 |
T46 |
1396 |
0 |
0 |
0 |
T54 |
2220 |
0 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
0 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
0 |
0 |
1039 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
2 |
2 |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 51 | 46 | 90.20 |
Logical | 51 | 46 | 90.20 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T67,T154 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T11,T19 |
1 | 1 | 1 | Covered | T1,T11,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T11,T19 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T196 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T11,T19 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1044 |
1044 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840291 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840291 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840291 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409464042 |
15840213 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
376950680 |
0 |
0 |
T1 |
385048 |
305916 |
0 |
0 |
T2 |
149403 |
147718 |
0 |
0 |
T3 |
211355 |
188843 |
0 |
0 |
T4 |
1703 |
1579 |
0 |
0 |
T5 |
543758 |
543517 |
0 |
0 |
T11 |
400707 |
321573 |
0 |
0 |
T12 |
3628 |
2596 |
0 |
0 |
T16 |
3483 |
3340 |
0 |
0 |
T17 |
3000 |
2845 |
0 |
0 |
T18 |
1412 |
1283 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840291 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840291 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
31680675 |
0 |
0 |
T1 |
385048 |
791168 |
0 |
0 |
T2 |
149403 |
1600 |
0 |
0 |
T3 |
211355 |
12768 |
0 |
0 |
T4 |
1703 |
64 |
0 |
0 |
T5 |
543758 |
72 |
0 |
0 |
T11 |
400707 |
791168 |
0 |
0 |
T12 |
3628 |
400 |
0 |
0 |
T16 |
3483 |
64 |
0 |
0 |
T17 |
3000 |
64 |
0 |
0 |
T18 |
1412 |
64 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409370359 |
15840028 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
0 |
0 |
1039 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840291 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
|
unreachable |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 43 | 42 | 97.67 |
Logical | 43 | 42 | 97.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T7,T21,T61 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Unreachable | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T7,T21,T61 |
1 | 1 | 0 | Covered | T1,T11,T19 |
1 | 1 | 1 | Unreachable | T1,T11,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Unreachable | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T11,T19 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T21,T61 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T21,T61 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T11,T19 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1044 |
1044 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838800 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838800 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838800 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476542 |
17838722 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
372953813 |
0 |
0 |
T1 |
385048 |
305916 |
0 |
0 |
T2 |
149403 |
147718 |
0 |
0 |
T3 |
211355 |
188843 |
0 |
0 |
T4 |
1703 |
1579 |
0 |
0 |
T5 |
543758 |
543515 |
0 |
0 |
T11 |
400707 |
321573 |
0 |
0 |
T12 |
3628 |
2596 |
0 |
0 |
T16 |
3483 |
3340 |
0 |
0 |
T17 |
3000 |
2845 |
0 |
0 |
T18 |
1412 |
1283 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838800 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838800 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
35677614 |
0 |
0 |
T1 |
385048 |
791168 |
0 |
0 |
T2 |
149403 |
1600 |
0 |
0 |
T3 |
211355 |
12768 |
0 |
0 |
T4 |
1703 |
64 |
0 |
0 |
T5 |
543758 |
74 |
0 |
0 |
T11 |
400707 |
791168 |
0 |
0 |
T12 |
3628 |
400 |
0 |
0 |
T16 |
3483 |
64 |
0 |
0 |
T17 |
3000 |
64 |
0 |
0 |
T18 |
1412 |
64 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409437705 |
17838544 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
0 |
0 |
1039 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838800 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 25 | 25 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
2 |
2 |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 51 | 50 | 98.04 |
Logical | 51 | 50 | 98.04 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T67,T154 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T67,T154 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T67,T154 |
1 | 0 | 1 | Covered | T67,T154 |
1 | 1 | 0 | Covered | T1,T11,T19 |
1 | 1 | 1 | Covered | T1,T11,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T11,T19 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T67,T154 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T67,T154 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T11,T19 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1044 |
1044 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840361 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840361 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840361 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409464042 |
15840213 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
376950695 |
0 |
0 |
T1 |
385048 |
305916 |
0 |
0 |
T2 |
149403 |
147718 |
0 |
0 |
T3 |
211355 |
188843 |
0 |
0 |
T4 |
1703 |
1579 |
0 |
0 |
T5 |
543758 |
543517 |
0 |
0 |
T11 |
400707 |
321573 |
0 |
0 |
T12 |
3628 |
2596 |
0 |
0 |
T16 |
3483 |
3340 |
0 |
0 |
T17 |
3000 |
2845 |
0 |
0 |
T18 |
1412 |
1283 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840361 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840361 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
31680730 |
0 |
0 |
T1 |
385048 |
791168 |
0 |
0 |
T2 |
149403 |
1600 |
0 |
0 |
T3 |
211355 |
12768 |
0 |
0 |
T4 |
1703 |
64 |
0 |
0 |
T5 |
543758 |
72 |
0 |
0 |
T11 |
400707 |
791168 |
0 |
0 |
T12 |
3628 |
400 |
0 |
0 |
T16 |
3483 |
64 |
0 |
0 |
T17 |
3000 |
64 |
0 |
0 |
T18 |
1412 |
64 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409370359 |
15840028 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
0 |
0 |
1039 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
15840361 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
36 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
CONT_ASSIGN | 62 | 0 | 0 | |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 126 | 0 | 0 | |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
|
unreachable |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
2 |
2 |
126 |
|
unreachable |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
171 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Total | Covered | Percent |
Conditions | 43 | 43 | 100.00 |
Logical | 43 | 43 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T69 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | |
1 | 0 | 1 | Unreachable | T7,T21,T61 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Unreachable | T1,T2,T3 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Unreachable | T68,T69 |
1 | 0 | 1 | Unreachable | T7,T21,T61 |
1 | 1 | 0 | Covered | T1,T11,T19 |
1 | 1 | 1 | Unreachable | T1,T11,T19 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Unreachable | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T11,T19 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | T1,T11,T19 |
1 | 1 | Covered | T1,T11,T19 |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T7,T21,T61 |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T21,T61 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T11,T19 |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T11,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T11,T19 |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1044 |
1044 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838721 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838721 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838721 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476542 |
17838722 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
372953891 |
0 |
0 |
T1 |
385048 |
305916 |
0 |
0 |
T2 |
149403 |
147718 |
0 |
0 |
T3 |
211355 |
188843 |
0 |
0 |
T4 |
1703 |
1579 |
0 |
0 |
T5 |
543758 |
543515 |
0 |
0 |
T11 |
400707 |
321573 |
0 |
0 |
T12 |
3628 |
2596 |
0 |
0 |
T16 |
3483 |
3340 |
0 |
0 |
T17 |
3000 |
2845 |
0 |
0 |
T18 |
1412 |
1283 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838721 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838721 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
35677457 |
0 |
0 |
T1 |
385048 |
791168 |
0 |
0 |
T2 |
149403 |
1600 |
0 |
0 |
T3 |
211355 |
12768 |
0 |
0 |
T4 |
1703 |
64 |
0 |
0 |
T5 |
543758 |
74 |
0 |
0 |
T11 |
400707 |
791168 |
0 |
0 |
T12 |
3628 |
400 |
0 |
0 |
T16 |
3483 |
64 |
0 |
0 |
T17 |
3000 |
64 |
0 |
0 |
T18 |
1412 |
64 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409437705 |
17838544 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
0 |
0 |
1039 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
408631427 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
gen_data_port_assertion.DataFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476704 |
17838721 |
0 |
0 |
T1 |
385048 |
395584 |
0 |
0 |
T2 |
149403 |
800 |
0 |
0 |
T3 |
211355 |
6384 |
0 |
0 |
T4 |
1703 |
32 |
0 |
0 |
T5 |
543758 |
37 |
0 |
0 |
T11 |
400707 |
395584 |
0 |
0 |
T12 |
3628 |
200 |
0 |
0 |
T16 |
3483 |
32 |
0 |
0 |
T17 |
3000 |
32 |
0 |
0 |
T18 |
1412 |
32 |
0 |
0 |