Line Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Module :
prim_mubi4_sender
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
2147483647 |
2147483647 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
4620576 |
4620396 |
0 |
0 |
T2 |
1792836 |
1791816 |
0 |
0 |
T3 |
2536260 |
2419332 |
0 |
0 |
T4 |
20436 |
19716 |
0 |
0 |
T5 |
6525096 |
6523068 |
0 |
0 |
T11 |
4808484 |
4808268 |
0 |
0 |
T12 |
43536 |
35952 |
0 |
0 |
T16 |
41796 |
40848 |
0 |
0 |
T17 |
36000 |
34908 |
0 |
0 |
T18 |
16944 |
16164 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
ALWAYS | 55 | 3 | 3 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
48 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
58 |
1 |
1 |
85 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
55 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 55 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
OutputsKnown_A |
409476809 |
408631532 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
409476809 |
408631532 |
0 |
0 |
T1 |
385048 |
385033 |
0 |
0 |
T2 |
149403 |
149318 |
0 |
0 |
T3 |
211355 |
201611 |
0 |
0 |
T4 |
1703 |
1643 |
0 |
0 |
T5 |
543758 |
543589 |
0 |
0 |
T11 |
400707 |
400689 |
0 |
0 |
T12 |
3628 |
2996 |
0 |
0 |
T16 |
3483 |
3404 |
0 |
0 |
T17 |
3000 |
2909 |
0 |
0 |
T18 |
1412 |
1347 |
0 |
0 |