Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24086198	1		T1	3063		T2	1787		T3	468
full_word	7712086	1		T1	388		T2	409		T3	195

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31797994	1		T1	3451		T2	2196		T3	663
auto[TlIntgErrCmd]	105	1		T67	3		T100	3		T207	3
auto[TlIntgErrData]	95	1		T67	1		T100	4		T207	3
auto[TlIntgErrBoth]	90	1		T67	6		T100	3		T207	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27360713	1		T1	3051		T2	1993		T3	562
auto[1]	4437571	1		T1	400		T2	203		T3	101

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23417752	1		T1	3031		T2	1744		T3	447
auto[TlIntgErrNone]	partial	auto[1]	668178	1		T1	32		T2	43		T3	21
auto[TlIntgErrNone]	full_word	auto[0]	3942820	1		T1	20		T2	249		T3	115
auto[TlIntgErrNone]	full_word	auto[1]	3769244	1		T1	368		T2	160		T3	80
auto[TlIntgErrCmd]	partial	auto[0]	48	1		T100	1		T208	4		T235	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T67	2		T100	2		T207	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T67	1		T208	1		T317	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T234	1		T337	1		T335	1
auto[TlIntgErrData]	partial	auto[0]	38	1		T100	1		T207	1		T208	3
auto[TlIntgErrData]	partial	auto[1]	50	1		T100	3		T207	2		T208	5
auto[TlIntgErrData]	full_word	auto[0]	6	1		T67	1		T268	1		T335	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T338	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T67	3		T100	1		T207	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T67	3		T100	2		T207	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T268	1		T339	3		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T335	1		-	-		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18816	1		T67	7		T68	282		T100	7
full_word	3969730	1		T2	17		T3	3		T12	26

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3988273	1		T2	17		T3	3		T12	26
auto[TlIntgErrCmd]	97	1		T67	4		T100	2		T207	5
auto[TlIntgErrData]	97	1		T67	4		T100	5		T207	3
auto[TlIntgErrBoth]	79	1		T67	2		T100	1		T207	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3963373	1		T2	17		T3	3		T12	26
auto[1]	25173	1		T67	6		T68	352		T100	6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1106	1		T68	31		T101	3		T206	10
auto[TlIntgErrNone]	partial	auto[1]	17461	1		T68	251		T101	23		T206	145
auto[TlIntgErrNone]	full_word	auto[0]	3962155	1		T2	17		T3	3		T12	26
auto[TlIntgErrNone]	full_word	auto[1]	7551	1		T68	101		T101	20		T206	44
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T67	2		T207	4		T208	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T100	1		T207	1		T208	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T268	1		T271	1		T262	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1		T67	2		T100	1		T208	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T67	1		T100	2		T207	1
auto[TlIntgErrData]	partial	auto[1]	50	1		T67	3		T100	3		T207	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T208	1		T338	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1		T207	1		T261	1		T271	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T207	1		T208	1		T235	3
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T67	1		T100	1		T207	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T67	1		T317	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T208	1		T338	1		-	-