Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T12

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T12

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1560798368	1557358392	0	0
CheckNGreaterZero_A	4160	4160	0	0
GntImpliesReady_A	1560798368	412389757	0	0
GntImpliesValid_A	1560798368	412389757	0	0
GrantKnown_A	1560798368	1557358392	0	0
IdxKnown_A	1560798368	1557358392	0	0
IndexIsCorrect_A	1560798368	412389757	0	0
NoReadyValidNoGrant_A	1560798368	172938493	0	0
Priority_A	1560798368	436305810	0	0
ReadyAndValidImplyGrant_A	1560798368	412389757	0	0
ReqAndReadyImplyGrant_A	1560798368	412389757	0	0
ReqImpliesValid_A	1560798368	436305810	0	0
ValidKnown_A	1560798368	1557358392	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	1557358392	0	0
T1	33504	32820	0	0
T2	20708	20176	0	0
T3	12496	11932	0	0
T4	3398012	3397736	0	0
T5	388292	384952	0	0
T6	210928	210300	0	0
T12	2696	2432	0	0
T19	6192	5620	0	0
T20	330920	330400	0	0
T21	10120	9792	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4160	4160	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T12	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	412389757	0	0
T1	16752	12232	0	0
T2	20708	5286	0	0
T3	12496	594	0	0
T4	3398012	1104914	0	0
T5	388292	48676	0	0
T6	210928	44002	0	0
T7	0	48452	0	0
T12	2696	116	0	0
T13	0	839486	0	0
T19	6192	132	0	0
T20	330920	42610	0	0
T21	10120	500	0	0
T31	304288	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	412389757	0	0
T1	16752	12232	0	0
T2	20708	5286	0	0
T3	12496	594	0	0
T4	3398012	1104914	0	0
T5	388292	48676	0	0
T6	210928	44002	0	0
T7	0	48452	0	0
T12	2696	116	0	0
T13	0	839486	0	0
T19	6192	132	0	0
T20	330920	42610	0	0
T21	10120	500	0	0
T31	304288	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	1557358392	0	0
T1	33504	32820	0	0
T2	20708	20176	0	0
T3	12496	11932	0	0
T4	3398012	3397736	0	0
T5	388292	384952	0	0
T6	210928	210300	0	0
T12	2696	2432	0	0
T19	6192	5620	0	0
T20	330920	330400	0	0
T21	10120	9792	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	1557358392	0	0
T1	33504	32820	0	0
T2	20708	20176	0	0
T3	12496	11932	0	0
T4	3398012	3397736	0	0
T5	388292	384952	0	0
T6	210928	210300	0	0
T12	2696	2432	0	0
T19	6192	5620	0	0
T20	330920	330400	0	0
T21	10120	9792	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	412389757	0	0
T1	16752	12232	0	0
T2	20708	5286	0	0
T3	12496	594	0	0
T4	3398012	1104914	0	0
T5	388292	48676	0	0
T6	210928	44002	0	0
T7	0	48452	0	0
T12	2696	116	0	0
T13	0	839486	0	0
T19	6192	132	0	0
T20	330920	42610	0	0
T21	10120	500	0	0
T31	304288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	172938493	0	0
T1	16752	512	0	0
T2	20708	1670	0	0
T3	12496	898	0	0
T4	3398012	8684	0	0
T5	388292	256	0	0
T6	210928	69050	0	0
T7	0	1437630	0	0
T8	0	109500	0	0
T12	2696	386	0	0
T13	0	1048962	0	0
T19	6192	512	0	0
T20	330920	422	0	0
T21	10120	276	0	0
T31	304288	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	436305810	0	0
T1	16752	12232	0	0
T2	20708	5286	0	0
T3	12496	594	0	0
T4	3398012	1104914	0	0
T5	388292	48676	0	0
T6	210928	54472	0	0
T7	0	326734	0	0
T12	2696	116	0	0
T13	0	839486	0	0
T19	6192	132	0	0
T20	330920	42610	0	0
T21	10120	500	0	0
T31	304288	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	412389757	0	0
T1	16752	12232	0	0
T2	20708	5286	0	0
T3	12496	594	0	0
T4	3398012	1104914	0	0
T5	388292	48676	0	0
T6	210928	44002	0	0
T7	0	48452	0	0
T12	2696	116	0	0
T13	0	839486	0	0
T19	6192	132	0	0
T20	330920	42610	0	0
T21	10120	500	0	0
T31	304288	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	412389757	0	0
T1	16752	12232	0	0
T2	20708	5286	0	0
T3	12496	594	0	0
T4	3398012	1104914	0	0
T5	388292	48676	0	0
T6	210928	44002	0	0
T7	0	48452	0	0
T12	2696	116	0	0
T13	0	839486	0	0
T19	6192	132	0	0
T20	330920	42610	0	0
T21	10120	500	0	0
T31	304288	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	436305810	0	0
T1	16752	12232	0	0
T2	20708	5286	0	0
T3	12496	594	0	0
T4	3398012	1104914	0	0
T5	388292	48676	0	0
T6	210928	54472	0	0
T7	0	326734	0	0
T12	2696	116	0	0
T13	0	839486	0	0
T19	6192	132	0	0
T20	330920	42610	0	0
T21	10120	500	0	0
T31	304288	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560798368	1557358392	0	0
T1	33504	32820	0	0
T2	20708	20176	0	0
T3	12496	11932	0	0
T4	3398012	3397736	0	0
T5	388292	384952	0	0
T6	210928	210300	0	0
T12	2696	2432	0	0
T19	6192	5620	0	0
T20	330920	330400	0	0
T21	10120	9792	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	390199592	389339598	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	390199592	107119867	0	0
GntImpliesValid_A	390199592	107119867	0	0
GrantKnown_A	390199592	389339598	0	0
IdxKnown_A	390199592	389339598	0	0
IndexIsCorrect_A	390199592	107119867	0	0
NoReadyValidNoGrant_A	390199592	45098738	0	0
Priority_A	390199592	113116273	0	0
ReadyAndValidImplyGrant_A	390199592	107119867	0	0
ReqAndReadyImplyGrant_A	390199592	107119867	0	0
ReqImpliesValid_A	390199592	113116273	0	0
ValidKnown_A	390199592	389339598	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	107119867	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	13749	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	107119867	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	13749	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	107119867	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	13749	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	45098738	0	0
T1	8376	256	0	0
T2	5177	678	0	0
T3	3124	447	0	0
T4	849503	3391	0	0
T5	97073	128	0	0
T6	52732	22957	0	0
T12	674	128	0	0
T19	1548	256	0	0
T20	82730	159	0	0
T21	2530	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	113116273	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	17038	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	107119867	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	13749	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	107119867	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	13749	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	113116273	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	17038	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	390199592	389339598	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	390199592	107119941	0	0
GntImpliesValid_A	390199592	107119941	0	0
GrantKnown_A	390199592	389339598	0	0
IdxKnown_A	390199592	389339598	0	0
IndexIsCorrect_A	390199592	107119941	0	0
NoReadyValidNoGrant_A	390199592	45098730	0	0
Priority_A	390199592	113116355	0	0
ReadyAndValidImplyGrant_A	390199592	107119941	0	0
ReqAndReadyImplyGrant_A	390199592	107119941	0	0
ReqImpliesValid_A	390199592	113116355	0	0
ValidKnown_A	390199592	389339598	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	107119941	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	13749	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	107119941	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	13749	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	107119941	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	13749	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	45098730	0	0
T1	8376	256	0	0
T2	5177	678	0	0
T3	3124	447	0	0
T4	849503	3391	0	0
T5	97073	128	0	0
T6	52732	22957	0	0
T12	674	128	0	0
T19	1548	256	0	0
T20	82730	159	0	0
T21	2530	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	113116355	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	17038	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	107119941	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	13749	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	107119941	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	13749	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	113116355	0	0
T1	8376	6116	0	0
T2	5177	1540	0	0
T3	3124	296	0	0
T4	849503	488943	0	0
T5	97073	11497	0	0
T6	52732	17038	0	0
T12	674	32	0	0
T19	1548	66	0	0
T20	82730	12018	0	0
T21	2530	244	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T6
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T3,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T12
1	1	Covered	T2,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T12,T6
1	1	Covered	T2,T3,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T12

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	390199592	389339598	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	390199592	99074947	0	0
GntImpliesValid_A	390199592	99074947	0	0
GrantKnown_A	390199592	389339598	0	0
IdxKnown_A	390199592	389339598	0	0
IndexIsCorrect_A	390199592	99074947	0	0
NoReadyValidNoGrant_A	390199592	41370518	0	0
Priority_A	390199592	105036558	0	0
ReadyAndValidImplyGrant_A	390199592	99074947	0	0
ReqAndReadyImplyGrant_A	390199592	99074947	0	0
ReqImpliesValid_A	390199592	105036558	0	0
ValidKnown_A	390199592	389339598	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	99074947	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	8252	0	0
T7	0	24226	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	99074947	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	8252	0	0
T7	0	24226	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	99074947	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	8252	0	0
T7	0	24226	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	41370518	0	0
T2	5177	157	0	0
T3	3124	2	0	0
T4	849503	951	0	0
T5	97073	0	0	0
T6	52732	11568	0	0
T7	0	718815	0	0
T8	0	54750	0	0
T12	674	65	0	0
T13	0	524481	0	0
T19	1548	0	0	0
T20	82730	52	0	0
T21	2530	10	0	0
T31	152144	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	105036558	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	10198	0	0
T7	0	163367	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	99074947	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	8252	0	0
T7	0	24226	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	99074947	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	8252	0	0
T7	0	24226	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	105036558	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	10198	0	0
T7	0	163367	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T6
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T3,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T12
1	1	Covered	T2,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T12,T6
1	1	Covered	T2,T3,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T12

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	390199592	389339598	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	390199592	99075002	0	0
GntImpliesValid_A	390199592	99075002	0	0
GrantKnown_A	390199592	389339598	0	0
IdxKnown_A	390199592	389339598	0	0
IndexIsCorrect_A	390199592	99075002	0	0
NoReadyValidNoGrant_A	390199592	41370507	0	0
Priority_A	390199592	105036624	0	0
ReadyAndValidImplyGrant_A	390199592	99075002	0	0
ReqAndReadyImplyGrant_A	390199592	99075002	0	0
ReqImpliesValid_A	390199592	105036624	0	0
ValidKnown_A	390199592	389339598	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	99075002	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	8252	0	0
T7	0	24226	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	99075002	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	8252	0	0
T7	0	24226	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	99075002	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	8252	0	0
T7	0	24226	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	41370507	0	0
T2	5177	157	0	0
T3	3124	2	0	0
T4	849503	951	0	0
T5	97073	0	0	0
T6	52732	11568	0	0
T7	0	718815	0	0
T8	0	54750	0	0
T12	674	65	0	0
T13	0	524481	0	0
T19	1548	0	0	0
T20	82730	52	0	0
T21	2530	10	0	0
T31	152144	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	105036624	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	10198	0	0
T7	0	163367	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	99075002	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	8252	0	0
T7	0	24226	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	99075002	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	8252	0	0
T7	0	24226	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	105036624	0	0
T2	5177	1103	0	0
T3	3124	1	0	0
T4	849503	63514	0	0
T5	97073	12841	0	0
T6	52732	10198	0	0
T7	0	163367	0	0
T12	674	26	0	0
T13	0	419743	0	0
T19	1548	0	0	0
T20	82730	9287	0	0
T21	2530	6	0	0
T31	152144	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390199592	389339598	0	0
T1	8376	8205	0	0
T2	5177	5044	0	0
T3	3124	2983	0	0
T4	849503	849434	0	0
T5	97073	96238	0	0
T6	52732	52575	0	0
T12	674	608	0	0
T19	1548	1405	0	0
T20	82730	82600	0	0
T21	2530	2448	0	0