Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	314420	1		T1	13680		T2	1		T3	1
all_values[1]	314420	1		T1	13680		T2	1		T3	1
all_values[2]	314420	1		T1	13680		T2	1		T3	1
all_values[3]	314420	1		T1	13680		T2	1		T3	1
all_values[4]	314420	1		T1	13680		T2	1		T3	1
all_values[5]	314420	1		T1	13680		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	635315	1		T1	27364		T2	6		T3	6
auto[1]	1251205	1		T1	54716		T26	31408		T23	6228

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	917628	1		T1	39969		T2	4		T3	4
auto[1]	968892	1		T1	42111		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	314274	1		T1	13680		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	146	1		T248	6		T249	5		T250	6
all_values[1]	auto[0]	auto[1]	314271	1		T1	13680		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	149	1		T248	1		T249	4		T250	4
all_values[2]	auto[0]	auto[0]	1646	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	62	1		T249	2		T250	1		T322	1
all_values[2]	auto[1]	auto[0]	312646	1		T1	13679		T26	7852		T23	1557
all_values[2]	auto[1]	auto[1]	66	1		T248	2		T249	3		T250	2
all_values[3]	auto[0]	auto[0]	1618	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	57	1		T248	1		T249	2		T250	2
all_values[3]	auto[1]	auto[0]	82160	1		T1	567		T26	212		T23	1557
all_values[3]	auto[1]	auto[1]	230585	1		T1	13112		T26	7640		T37	1567
all_values[4]	auto[0]	auto[0]	1163	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	533	1		T6	1		T20	1		T38	1
all_values[4]	auto[1]	auto[0]	204135	1		T1	12040		T26	6142		T23	1
all_values[4]	auto[1]	auto[1]	108589	1		T1	1639		T26	1710		T23	1556
all_values[5]	auto[0]	auto[0]	1586	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	105	1		T20	1		T38	1		T39	1
all_values[5]	auto[1]	auto[0]	312674	1		T1	13679		T26	7852		T23	1557
all_values[5]	auto[1]	auto[1]	55	1		T248	3		T249	2		T250	2