Testbench Group List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Groups Coverage Summary 
COVEREDEXPECTEDSCORECOVEREDEXPECTEDINST SCOREWEIGHT
3185 3244 98.18 3185 3244 98.18 1


Total groups in report: 31
NAMECOVEREDEXPECTEDSCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSINGCOMMENT
dv_base_reg_pkg::dv_base_shadowed_field_cov::shadow_field_errs_cg 1 2 50.00 50.00 1 100 1 1 64 64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5} 40 48 83.33 1 100 1 0 64 64
flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg 15 18 83.33 1 100 1 0 64 64
flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg 6 7 85.71 1 100 1 0 64 64
flash_ctrl_env_pkg::flash_ctrl_env_cov::std_fault_cg 7 8 87.50 1 100 1 0 64 64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5} 30 34 88.24 1 100 1 0 64 64
flash_ctrl_env_pkg::flash_ctrl_env_cov::hw_error_cg 11 12 91.67 1 100 1 0 64 64
alert_esc_agent_pkg::alert_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5} 34 34 100.00 1 100 1 0 64 64
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg 15 15 100.00 92.59 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg 14 14 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg 24 24 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg 2 2 100.00 98.41 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg 6 6 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg 6 6 100.00 98.25 1 100 1 1 64 64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg 4 4 100.00 100.00 1 100 1 1 64 64
flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg 31 31 100.00 1 100 1 0 64 64
flash_ctrl_env_pkg::flash_ctrl_env_cov::erase_susp_cg 1 1 100.00 1 100 1 0 64 64
flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg 42 42 100.00 1 100 1 0 64 64
flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg 11 11 100.00 1 100 1 0 64 64
flash_ctrl_env_pkg::flash_ctrl_env_cov::rma_init_cg 1 1 100.00 1 100 1 0 64 64
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg 99 99 100.00 1 100 1 0 64 64
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg 99 99 100.00 1 100 1 0 64 64
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::phy_rd_cg 3 3 100.00 1 100 1 0 64 64
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::phy_rd_cg 3 3 100.00 1 100 1 0 64 64
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg 2 2 100.00 100.00 1 100 1 1 64 64
tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} 1 1 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=2} 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::pending_req_on_rst_cg 2 2 100.00 83.33 1 100 1 1 64 64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} 137 137 100.00 100.00 1 100 1 1 64 64
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%