Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T38 |
1 |
|
T31 |
7 |
|
T43 |
2 |
| others[1] |
264 |
1 |
|
T31 |
14 |
|
T43 |
1 |
|
T24 |
1 |
| others[2] |
259 |
1 |
|
T6 |
1 |
|
T20 |
1 |
|
T31 |
12 |
| others[3] |
394 |
1 |
|
T16 |
1 |
|
T5 |
1 |
|
T31 |
20 |
| false |
119 |
1 |
|
T31 |
4 |
|
T43 |
1 |
|
T130 |
6 |
| true |
5612 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1039 |
1 |
|
T19 |
1 |
|
T31 |
22 |
|
T49 |
9 |
| others[1] |
1034 |
1 |
|
T4 |
1 |
|
T31 |
16 |
|
T49 |
13 |
| others[2] |
1056 |
1 |
|
T6 |
1 |
|
T31 |
27 |
|
T49 |
8 |
| others[3] |
1839 |
1 |
|
T10 |
1 |
|
T23 |
1 |
|
T31 |
29 |
| false |
526 |
1 |
|
T1 |
1 |
|
T20 |
1 |
|
T31 |
7 |
| true |
1390 |
1 |
|
T16 |
1 |
|
T5 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T31 |
10 |
|
T43 |
1 |
|
T111 |
1 |
| others[1] |
231 |
1 |
|
T31 |
11 |
|
T43 |
1 |
|
T24 |
1 |
| others[2] |
250 |
1 |
|
T6 |
1 |
|
T31 |
8 |
|
T124 |
1 |
| others[3] |
407 |
1 |
|
T26 |
1 |
|
T38 |
1 |
|
T31 |
19 |
| false |
111 |
1 |
|
T31 |
5 |
|
T21 |
1 |
|
T37 |
1 |
| true |
5662 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T31 |
10 |
|
T43 |
2 |
|
T130 |
7 |
| others[1] |
226 |
1 |
|
T6 |
1 |
|
T31 |
10 |
|
T130 |
10 |
| others[2] |
235 |
1 |
|
T16 |
1 |
|
T31 |
3 |
|
T43 |
2 |
| others[3] |
383 |
1 |
|
T20 |
1 |
|
T31 |
18 |
|
T21 |
1 |
| false |
120 |
1 |
|
T31 |
9 |
|
T130 |
9 |
|
T372 |
1 |
| true |
5691 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T31 |
22 |
|
T49 |
14 |
|
T161 |
1 |
| others[1] |
1264 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T12 |
1 |
| others[2] |
1198 |
1 |
|
T31 |
21 |
|
T49 |
7 |
|
T43 |
2 |
| others[3] |
2047 |
1 |
|
T1 |
1 |
|
T31 |
36 |
|
T49 |
17 |
| false |
661 |
1 |
|
T31 |
7 |
|
T49 |
7 |
|
T43 |
2 |
| true |
464 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1314 |
1 |
|
T31 |
24 |
|
T49 |
11 |
|
T43 |
2 |
| others[1] |
1242 |
1 |
|
T31 |
13 |
|
T49 |
9 |
|
T43 |
2 |
| others[2] |
1165 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T31 |
22 |
| others[3] |
2071 |
1 |
|
T19 |
1 |
|
T31 |
35 |
|
T49 |
22 |
| false |
630 |
1 |
|
T31 |
7 |
|
T49 |
5 |
|
T43 |
3 |
| true |
462 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T31 |
5 |
|
T43 |
4 |
|
T224 |
2 |
| others[1] |
107 |
1 |
|
T31 |
3 |
|
T43 |
2 |
|
T237 |
1 |
| others[2] |
108 |
1 |
|
T31 |
5 |
|
T43 |
1 |
|
T130 |
3 |
| others[3] |
163 |
1 |
|
T31 |
6 |
|
T43 |
2 |
|
T130 |
2 |
| false |
63 |
1 |
|
T31 |
2 |
|
T43 |
2 |
|
T130 |
2 |
| true |
6330 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T31 |
14 |
|
T21 |
1 |
|
T46 |
1 |
| others[1] |
262 |
1 |
|
T5 |
1 |
|
T38 |
1 |
|
T31 |
13 |
| others[2] |
217 |
1 |
|
T23 |
1 |
|
T20 |
1 |
|
T31 |
4 |
| others[3] |
388 |
1 |
|
T26 |
1 |
|
T31 |
13 |
|
T37 |
1 |
| false |
138 |
1 |
|
T31 |
6 |
|
T303 |
1 |
|
T218 |
1 |
| true |
5648 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1091 |
1 |
|
T19 |
1 |
|
T31 |
23 |
|
T49 |
11 |
| others[1] |
1015 |
1 |
|
T20 |
1 |
|
T31 |
20 |
|
T49 |
13 |
| others[2] |
1101 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T6 |
1 |
| others[3] |
1757 |
1 |
|
T4 |
1 |
|
T26 |
1 |
|
T23 |
1 |
| false |
565 |
1 |
|
T31 |
11 |
|
T49 |
3 |
|
T161 |
1 |
| true |
1355 |
1 |
|
T16 |
1 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T6 |
1 |
|
T23 |
1 |
|
T31 |
11 |
| others[1] |
220 |
1 |
|
T26 |
1 |
|
T31 |
10 |
|
T43 |
1 |
| others[2] |
239 |
1 |
|
T31 |
8 |
|
T28 |
1 |
|
T39 |
1 |
| others[3] |
377 |
1 |
|
T31 |
6 |
|
T124 |
1 |
|
T43 |
2 |
| false |
121 |
1 |
|
T31 |
7 |
|
T130 |
3 |
|
T40 |
1 |
| true |
5698 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T31 |
8 |
|
T43 |
1 |
|
T123 |
1 |
| others[1] |
188 |
1 |
|
T31 |
7 |
|
T21 |
1 |
|
T43 |
1 |
| others[2] |
231 |
1 |
|
T16 |
1 |
|
T31 |
19 |
|
T43 |
2 |
| others[3] |
396 |
1 |
|
T31 |
12 |
|
T43 |
1 |
|
T39 |
1 |
| false |
93 |
1 |
|
T31 |
2 |
|
T130 |
5 |
|
T375 |
1 |
| true |
5730 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T31 |
14 |
|
T49 |
11 |
|
T43 |
3 |
| others[1] |
1214 |
1 |
|
T19 |
1 |
|
T31 |
21 |
|
T49 |
7 |
| others[2] |
1192 |
1 |
|
T31 |
21 |
|
T49 |
14 |
|
T44 |
1 |
| others[3] |
2105 |
1 |
|
T1 |
1 |
|
T26 |
1 |
|
T31 |
34 |
| false |
655 |
1 |
|
T31 |
11 |
|
T49 |
6 |
|
T46 |
1 |
| true |
462 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1206 |
1 |
|
T19 |
1 |
|
T26 |
1 |
|
T31 |
19 |
| others[1] |
1276 |
1 |
|
T31 |
18 |
|
T49 |
12 |
|
T43 |
3 |
| others[2] |
1206 |
1 |
|
T31 |
16 |
|
T49 |
9 |
|
T43 |
1 |
| others[3] |
2126 |
1 |
|
T1 |
1 |
|
T31 |
37 |
|
T49 |
22 |
| false |
622 |
1 |
|
T31 |
11 |
|
T49 |
5 |
|
T43 |
1 |
| true |
448 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T31 |
7 |
|
T43 |
2 |
|
T62 |
1 |
| others[1] |
94 |
1 |
|
T31 |
3 |
|
T43 |
3 |
|
T111 |
1 |
| others[2] |
103 |
1 |
|
T31 |
1 |
|
T224 |
1 |
|
T130 |
1 |
| others[3] |
188 |
1 |
|
T31 |
11 |
|
T43 |
5 |
|
T237 |
1 |
| false |
63 |
1 |
|
T31 |
2 |
|
T43 |
1 |
|
T112 |
3 |
| true |
6321 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T16 |
1 |
|
T31 |
10 |
|
T43 |
2 |
| others[1] |
229 |
1 |
|
T31 |
7 |
|
T43 |
1 |
|
T122 |
1 |
| others[2] |
259 |
1 |
|
T5 |
1 |
|
T31 |
11 |
|
T124 |
1 |
| others[3] |
394 |
1 |
|
T26 |
1 |
|
T23 |
1 |
|
T20 |
1 |
| false |
126 |
1 |
|
T31 |
6 |
|
T43 |
2 |
|
T303 |
1 |
| true |
5624 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1047 |
1 |
|
T38 |
1 |
|
T31 |
18 |
|
T49 |
11 |
| others[1] |
1069 |
1 |
|
T19 |
1 |
|
T31 |
17 |
|
T49 |
12 |
| others[2] |
1046 |
1 |
|
T16 |
1 |
|
T23 |
1 |
|
T12 |
1 |
| others[3] |
1744 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T31 |
30 |
| false |
550 |
1 |
|
T31 |
10 |
|
T49 |
6 |
|
T124 |
1 |
| true |
1428 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T31 |
16 |
|
T28 |
1 |
|
T123 |
1 |
| others[1] |
243 |
1 |
|
T31 |
14 |
|
T124 |
1 |
|
T126 |
1 |
| others[2] |
234 |
1 |
|
T16 |
1 |
|
T26 |
1 |
|
T31 |
8 |
| others[3] |
357 |
1 |
|
T23 |
1 |
|
T20 |
1 |
|
T31 |
15 |
| false |
121 |
1 |
|
T31 |
6 |
|
T224 |
1 |
|
T207 |
1 |
| true |
5700 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T16 |
1 |
|
T23 |
1 |
|
T31 |
11 |
| others[1] |
232 |
1 |
|
T6 |
1 |
|
T31 |
9 |
|
T43 |
3 |
| others[2] |
224 |
1 |
|
T31 |
6 |
|
T130 |
12 |
|
T148 |
1 |
| others[3] |
371 |
1 |
|
T31 |
17 |
|
T43 |
2 |
|
T62 |
1 |
| false |
126 |
1 |
|
T20 |
1 |
|
T31 |
5 |
|
T39 |
1 |
| true |
5716 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1305 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T31 |
17 |
| others[1] |
1252 |
1 |
|
T31 |
15 |
|
T49 |
10 |
|
T43 |
1 |
| others[2] |
1157 |
1 |
|
T19 |
1 |
|
T31 |
19 |
|
T49 |
10 |
| others[3] |
2016 |
1 |
|
T12 |
1 |
|
T31 |
40 |
|
T49 |
21 |
| false |
688 |
1 |
|
T31 |
10 |
|
T49 |
5 |
|
T43 |
1 |
| true |
466 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1197 |
1 |
|
T31 |
24 |
|
T49 |
9 |
|
T44 |
3 |
| others[1] |
1271 |
1 |
|
T1 |
1 |
|
T31 |
20 |
|
T49 |
10 |
| others[2] |
1239 |
1 |
|
T31 |
18 |
|
T49 |
9 |
|
T43 |
2 |
| others[3] |
2041 |
1 |
|
T19 |
1 |
|
T31 |
27 |
|
T49 |
24 |
| false |
688 |
1 |
|
T31 |
12 |
|
T49 |
4 |
|
T161 |
1 |
| true |
448 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T31 |
6 |
|
T43 |
3 |
|
T224 |
1 |
| others[1] |
89 |
1 |
|
T31 |
2 |
|
T124 |
1 |
|
T43 |
2 |
| others[2] |
113 |
1 |
|
T31 |
5 |
|
T43 |
1 |
|
T224 |
1 |
| others[3] |
188 |
1 |
|
T31 |
7 |
|
T43 |
4 |
|
T237 |
1 |
| false |
68 |
1 |
|
T43 |
1 |
|
T39 |
1 |
|
T63 |
1 |
| true |
6322 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T5 |
1 |
|
T31 |
4 |
|
T46 |
1 |
| others[1] |
234 |
1 |
|
T26 |
1 |
|
T20 |
1 |
|
T31 |
12 |
| others[2] |
241 |
1 |
|
T6 |
1 |
|
T23 |
1 |
|
T31 |
9 |
| others[3] |
373 |
1 |
|
T31 |
11 |
|
T43 |
3 |
|
T24 |
1 |
| false |
123 |
1 |
|
T31 |
4 |
|
T28 |
1 |
|
T130 |
9 |
| true |
5667 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1095 |
1 |
|
T5 |
1 |
|
T20 |
1 |
|
T31 |
12 |
| others[1] |
1068 |
1 |
|
T19 |
1 |
|
T26 |
1 |
|
T23 |
1 |
| others[2] |
1051 |
1 |
|
T38 |
1 |
|
T31 |
23 |
|
T49 |
7 |
| others[3] |
1746 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| false |
557 |
1 |
|
T31 |
11 |
|
T49 |
7 |
|
T43 |
3 |
| true |
1367 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
260 |
1 |
|
T6 |
1 |
|
T26 |
1 |
|
T31 |
12 |
| others[1] |
208 |
1 |
|
T31 |
5 |
|
T24 |
1 |
|
T122 |
1 |
| others[2] |
255 |
1 |
|
T31 |
10 |
|
T123 |
1 |
|
T237 |
1 |
| others[3] |
390 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T31 |
24 |
| false |
134 |
1 |
|
T31 |
3 |
|
T130 |
5 |
|
T374 |
1 |
| true |
5637 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T6 |
1 |
|
T31 |
10 |
|
T39 |
1 |
| others[1] |
201 |
1 |
|
T31 |
6 |
|
T124 |
1 |
|
T43 |
2 |
| others[2] |
209 |
1 |
|
T31 |
10 |
|
T43 |
2 |
|
T218 |
1 |
| others[3] |
356 |
1 |
|
T31 |
17 |
|
T43 |
2 |
|
T224 |
1 |
| false |
121 |
1 |
|
T31 |
6 |
|
T302 |
1 |
|
T130 |
8 |
| true |
5754 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T31 |
27 |
|
T49 |
9 |
|
T43 |
1 |
| others[1] |
1247 |
1 |
|
T26 |
1 |
|
T31 |
11 |
|
T49 |
15 |
| others[2] |
1215 |
1 |
|
T31 |
18 |
|
T49 |
10 |
|
T43 |
1 |
| others[3] |
2058 |
1 |
|
T1 |
1 |
|
T31 |
30 |
|
T49 |
17 |
| false |
640 |
1 |
|
T19 |
1 |
|
T38 |
1 |
|
T31 |
15 |
| true |
471 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1254 |
1 |
|
T5 |
1 |
|
T31 |
21 |
|
T49 |
10 |
| others[1] |
1245 |
1 |
|
T1 |
1 |
|
T31 |
19 |
|
T49 |
12 |
| others[2] |
1202 |
1 |
|
T4 |
1 |
|
T31 |
14 |
|
T49 |
14 |
| others[3] |
2073 |
1 |
|
T31 |
29 |
|
T49 |
17 |
|
T43 |
2 |
| false |
669 |
1 |
|
T19 |
1 |
|
T31 |
18 |
|
T49 |
3 |
| true |
441 |
1 |
|
T10 |
1 |
|
T16 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T31 |
4 |
|
T43 |
3 |
|
T62 |
1 |
| others[1] |
90 |
1 |
|
T20 |
1 |
|
T31 |
3 |
|
T43 |
2 |
| others[2] |
110 |
1 |
|
T31 |
2 |
|
T111 |
1 |
|
T224 |
1 |
| others[3] |
175 |
1 |
|
T31 |
11 |
|
T43 |
5 |
|
T224 |
1 |
| false |
65 |
1 |
|
T16 |
1 |
|
T31 |
1 |
|
T43 |
1 |
| true |
6339 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T26 |
1 |
|
T31 |
9 |
|
T21 |
1 |
| others[1] |
233 |
1 |
|
T31 |
8 |
|
T37 |
1 |
|
T28 |
1 |
| others[2] |
244 |
1 |
|
T31 |
7 |
|
T43 |
2 |
|
T130 |
4 |
| others[3] |
415 |
1 |
|
T20 |
1 |
|
T38 |
1 |
|
T31 |
17 |
| false |
130 |
1 |
|
T31 |
6 |
|
T43 |
1 |
|
T130 |
4 |
| true |
5615 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1048 |
1 |
|
T5 |
1 |
|
T31 |
17 |
|
T49 |
5 |
| others[1] |
1097 |
1 |
|
T12 |
1 |
|
T31 |
24 |
|
T49 |
12 |
| others[2] |
1081 |
1 |
|
T1 |
1 |
|
T31 |
23 |
|
T49 |
16 |
| others[3] |
1738 |
1 |
|
T19 |
1 |
|
T23 |
1 |
|
T38 |
1 |
| false |
520 |
1 |
|
T26 |
1 |
|
T31 |
7 |
|
T49 |
3 |
| true |
1400 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
275 |
1 |
|
T31 |
13 |
|
T63 |
1 |
|
T130 |
10 |
| others[1] |
235 |
1 |
|
T31 |
9 |
|
T43 |
2 |
|
T62 |
1 |
| others[2] |
228 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T31 |
11 |
| others[3] |
394 |
1 |
|
T23 |
1 |
|
T38 |
1 |
|
T31 |
15 |
| false |
111 |
1 |
|
T126 |
1 |
|
T130 |
4 |
|
T376 |
1 |
| true |
5641 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |