Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9966 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
810 |
1 |
|
T31 |
21 |
|
T49 |
13 |
|
T34 |
1 |
| others[2] |
791 |
1 |
|
T1 |
1 |
|
T31 |
26 |
|
T49 |
11 |
| others[3] |
1267 |
1 |
|
T19 |
1 |
|
T31 |
27 |
|
T49 |
16 |
| false |
431 |
1 |
|
T4 |
1 |
|
T31 |
11 |
|
T49 |
9 |
| true |
557 |
1 |
|
T10 |
1 |
|
T16 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2368 |
1 |
|
T3 |
39 |
|
T25 |
23 |
|
T31 |
11 |
| others[1] |
2419 |
1 |
|
T3 |
43 |
|
T25 |
27 |
|
T31 |
8 |
| others[2] |
2307 |
1 |
|
T3 |
47 |
|
T25 |
22 |
|
T13 |
2 |
| others[3] |
3890 |
1 |
|
T1 |
1 |
|
T3 |
64 |
|
T25 |
41 |
| false |
1234 |
1 |
|
T3 |
26 |
|
T25 |
5 |
|
T23 |
1 |
| true |
1604 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9379 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T20 |
1 |
| others[1] |
261 |
1 |
|
T31 |
7 |
|
T43 |
1 |
|
T44 |
2 |
| others[2] |
304 |
1 |
|
T1 |
1 |
|
T16 |
1 |
|
T6 |
1 |
| others[3] |
435 |
1 |
|
T5 |
1 |
|
T31 |
19 |
|
T124 |
1 |
| false |
144 |
1 |
|
T23 |
1 |
|
T38 |
1 |
|
T31 |
4 |
| true |
3299 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9677 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
480 |
1 |
|
T31 |
7 |
|
T49 |
6 |
|
T43 |
2 |
| others[2] |
488 |
1 |
|
T26 |
1 |
|
T31 |
11 |
|
T49 |
4 |
| others[3] |
792 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T20 |
1 |
| false |
231 |
1 |
|
T31 |
4 |
|
T49 |
6 |
|
T43 |
2 |
| true |
2154 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9407 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T23 |
1 |
| others[1] |
266 |
1 |
|
T19 |
1 |
|
T31 |
9 |
|
T28 |
1 |
| others[2] |
252 |
1 |
|
T38 |
1 |
|
T31 |
14 |
|
T43 |
2 |
| others[3] |
441 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T31 |
19 |
| false |
137 |
1 |
|
T31 |
3 |
|
T43 |
1 |
|
T34 |
1 |
| true |
3319 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9386 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
284 |
1 |
|
T19 |
1 |
|
T31 |
10 |
|
T43 |
1 |
| others[2] |
238 |
1 |
|
T31 |
10 |
|
T124 |
1 |
|
T43 |
1 |
| others[3] |
401 |
1 |
|
T31 |
17 |
|
T43 |
2 |
|
T44 |
3 |
| false |
128 |
1 |
|
T31 |
3 |
|
T130 |
9 |
|
T332 |
1 |
| true |
3385 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10005 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
783 |
1 |
|
T1 |
1 |
|
T31 |
26 |
|
T49 |
14 |
| others[2] |
769 |
1 |
|
T19 |
1 |
|
T31 |
17 |
|
T49 |
9 |
| others[3] |
1317 |
1 |
|
T31 |
30 |
|
T49 |
13 |
|
T43 |
1 |
| false |
402 |
1 |
|
T31 |
8 |
|
T49 |
3 |
|
T122 |
1 |
| true |
546 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9950 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
788 |
1 |
|
T31 |
24 |
|
T49 |
10 |
|
T43 |
2 |
| others[2] |
755 |
1 |
|
T12 |
1 |
|
T31 |
19 |
|
T49 |
11 |
| others[3] |
1323 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T31 |
32 |
| false |
418 |
1 |
|
T31 |
3 |
|
T49 |
5 |
|
T44 |
2 |
| true |
546 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2352 |
1 |
|
T3 |
45 |
|
T25 |
23 |
|
T19 |
1 |
| others[1] |
2351 |
1 |
|
T3 |
41 |
|
T16 |
1 |
|
T25 |
22 |
| others[2] |
2318 |
1 |
|
T3 |
31 |
|
T6 |
1 |
|
T25 |
16 |
| others[3] |
3931 |
1 |
|
T1 |
1 |
|
T3 |
79 |
|
T25 |
41 |
| false |
1203 |
1 |
|
T3 |
23 |
|
T25 |
16 |
|
T31 |
4 |
| true |
1625 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9443 |
1 |
|
T1 |
1 |
|
T3 |
219 |
|
T25 |
118 |
| others[1] |
284 |
1 |
|
T5 |
1 |
|
T38 |
1 |
|
T31 |
7 |
| others[2] |
266 |
1 |
|
T31 |
7 |
|
T302 |
1 |
|
T130 |
8 |
| others[3] |
460 |
1 |
|
T6 |
1 |
|
T31 |
21 |
|
T43 |
2 |
| false |
143 |
1 |
|
T31 |
6 |
|
T207 |
1 |
|
T130 |
7 |
| true |
3184 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9639 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
468 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T20 |
1 |
| others[2] |
472 |
1 |
|
T16 |
1 |
|
T31 |
18 |
|
T49 |
8 |
| others[3] |
731 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T31 |
12 |
| false |
256 |
1 |
|
T31 |
1 |
|
T49 |
6 |
|
T44 |
1 |
| true |
2214 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9394 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
258 |
1 |
|
T1 |
1 |
|
T31 |
10 |
|
T43 |
1 |
| others[2] |
257 |
1 |
|
T26 |
1 |
|
T23 |
1 |
|
T38 |
1 |
| others[3] |
440 |
1 |
|
T31 |
25 |
|
T124 |
1 |
|
T44 |
1 |
| false |
144 |
1 |
|
T19 |
1 |
|
T31 |
5 |
|
T21 |
1 |
| true |
3287 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9397 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
248 |
1 |
|
T6 |
1 |
|
T31 |
9 |
|
T43 |
1 |
| others[2] |
258 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T31 |
14 |
| others[3] |
415 |
1 |
|
T23 |
1 |
|
T20 |
1 |
|
T38 |
1 |
| false |
120 |
1 |
|
T31 |
4 |
|
T43 |
2 |
|
T44 |
1 |
| true |
3342 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9917 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T26 |
1 |
| others[1] |
807 |
1 |
|
T19 |
1 |
|
T31 |
23 |
|
T49 |
10 |
| others[2] |
766 |
1 |
|
T5 |
1 |
|
T31 |
12 |
|
T49 |
5 |
| others[3] |
1327 |
1 |
|
T31 |
35 |
|
T49 |
25 |
|
T43 |
2 |
| false |
428 |
1 |
|
T1 |
1 |
|
T31 |
17 |
|
T49 |
7 |
| true |
535 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9857 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
783 |
1 |
|
T31 |
14 |
|
T49 |
12 |
|
T58 |
1 |
| others[2] |
832 |
1 |
|
T19 |
1 |
|
T12 |
1 |
|
T31 |
21 |
| others[3] |
1334 |
1 |
|
T1 |
1 |
|
T31 |
28 |
|
T49 |
17 |
| false |
395 |
1 |
|
T31 |
12 |
|
T49 |
7 |
|
T43 |
1 |
| true |
579 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2316 |
1 |
|
T3 |
50 |
|
T25 |
24 |
|
T13 |
2 |
| others[1] |
2413 |
1 |
|
T1 |
1 |
|
T3 |
44 |
|
T25 |
21 |
| others[2] |
2357 |
1 |
|
T3 |
44 |
|
T25 |
26 |
|
T20 |
1 |
| others[3] |
3910 |
1 |
|
T3 |
64 |
|
T16 |
1 |
|
T25 |
37 |
| false |
1200 |
1 |
|
T3 |
17 |
|
T25 |
10 |
|
T31 |
13 |
| true |
1584 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9416 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T20 |
1 |
| others[1] |
285 |
1 |
|
T1 |
1 |
|
T31 |
13 |
|
T43 |
2 |
| others[2] |
298 |
1 |
|
T19 |
1 |
|
T31 |
10 |
|
T124 |
1 |
| others[3] |
435 |
1 |
|
T31 |
15 |
|
T21 |
1 |
|
T43 |
1 |
| false |
124 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T31 |
6 |
| true |
3222 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9569 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
464 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T12 |
1 |
| others[2] |
484 |
1 |
|
T4 |
1 |
|
T31 |
9 |
|
T49 |
11 |
| others[3] |
774 |
1 |
|
T26 |
1 |
|
T38 |
1 |
|
T31 |
19 |
| false |
280 |
1 |
|
T31 |
6 |
|
T49 |
5 |
|
T43 |
3 |
| true |
2209 |
1 |
|
T1 |
1 |
|
T16 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9394 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T20 |
1 |
| others[1] |
250 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T26 |
1 |
| others[2] |
262 |
1 |
|
T31 |
11 |
|
T46 |
1 |
|
T24 |
1 |
| others[3] |
458 |
1 |
|
T38 |
1 |
|
T31 |
14 |
|
T124 |
1 |
| false |
120 |
1 |
|
T31 |
7 |
|
T130 |
4 |
|
T30 |
1 |
| true |
3296 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9379 |
1 |
|
T3 |
219 |
|
T16 |
1 |
|
T25 |
118 |
| others[1] |
244 |
1 |
|
T1 |
1 |
|
T31 |
7 |
|
T44 |
1 |
| others[2] |
247 |
1 |
|
T23 |
1 |
|
T31 |
12 |
|
T46 |
1 |
| others[3] |
429 |
1 |
|
T6 |
1 |
|
T31 |
19 |
|
T21 |
1 |
| false |
122 |
1 |
|
T31 |
2 |
|
T130 |
3 |
|
T142 |
1 |
| true |
3359 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9924 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
793 |
1 |
|
T1 |
1 |
|
T31 |
16 |
|
T49 |
14 |
| others[2] |
817 |
1 |
|
T31 |
14 |
|
T49 |
9 |
|
T43 |
1 |
| others[3] |
1304 |
1 |
|
T31 |
38 |
|
T49 |
16 |
|
T43 |
2 |
| false |
405 |
1 |
|
T19 |
1 |
|
T31 |
10 |
|
T49 |
6 |
| true |
537 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9904 |
1 |
|
T1 |
1 |
|
T3 |
219 |
|
T25 |
118 |
| others[1] |
804 |
1 |
|
T19 |
1 |
|
T31 |
22 |
|
T49 |
13 |
| others[2] |
802 |
1 |
|
T31 |
24 |
|
T49 |
9 |
|
T43 |
1 |
| others[3] |
1280 |
1 |
|
T31 |
24 |
|
T49 |
17 |
|
T43 |
1 |
| false |
428 |
1 |
|
T31 |
9 |
|
T49 |
7 |
|
T43 |
2 |
| true |
562 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2270 |
1 |
|
T3 |
32 |
|
T25 |
25 |
|
T13 |
1 |
| others[1] |
2380 |
1 |
|
T3 |
53 |
|
T25 |
28 |
|
T31 |
8 |
| others[2] |
2305 |
1 |
|
T3 |
46 |
|
T25 |
16 |
|
T20 |
1 |
| others[3] |
4074 |
1 |
|
T1 |
1 |
|
T3 |
71 |
|
T25 |
41 |
| false |
1161 |
1 |
|
T3 |
17 |
|
T25 |
8 |
|
T13 |
1 |
| true |
1590 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9390 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
284 |
1 |
|
T16 |
1 |
|
T31 |
9 |
|
T43 |
1 |
| others[2] |
281 |
1 |
|
T31 |
10 |
|
T43 |
1 |
|
T39 |
1 |
| others[3] |
457 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T31 |
12 |
| false |
136 |
1 |
|
T31 |
5 |
|
T130 |
2 |
|
T142 |
1 |
| true |
3232 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9575 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T23 |
1 |
| others[1] |
478 |
1 |
|
T19 |
1 |
|
T26 |
1 |
|
T31 |
11 |
| others[2] |
485 |
1 |
|
T31 |
8 |
|
T49 |
4 |
|
T43 |
6 |
| others[3] |
790 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T31 |
17 |
| false |
221 |
1 |
|
T6 |
1 |
|
T31 |
6 |
|
T49 |
1 |
| true |
2231 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9409 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
300 |
1 |
|
T20 |
1 |
|
T31 |
9 |
|
T43 |
2 |
| others[2] |
262 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T31 |
10 |
| others[3] |
416 |
1 |
|
T16 |
1 |
|
T19 |
1 |
|
T26 |
1 |
| false |
139 |
1 |
|
T31 |
6 |
|
T302 |
1 |
|
T130 |
3 |
| true |
3254 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9400 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
257 |
1 |
|
T31 |
7 |
|
T130 |
12 |
|
T145 |
1 |
| others[2] |
245 |
1 |
|
T6 |
1 |
|
T31 |
9 |
|
T21 |
1 |
| others[3] |
406 |
1 |
|
T16 |
1 |
|
T31 |
13 |
|
T124 |
1 |
| false |
140 |
1 |
|
T1 |
1 |
|
T31 |
1 |
|
T43 |
2 |
| true |
3332 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9917 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
789 |
1 |
|
T6 |
1 |
|
T31 |
17 |
|
T49 |
9 |
| others[2] |
766 |
1 |
|
T4 |
1 |
|
T31 |
13 |
|
T49 |
13 |
| others[3] |
1346 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T31 |
40 |
| false |
407 |
1 |
|
T31 |
6 |
|
T49 |
3 |
|
T124 |
1 |
| true |
555 |
1 |
|
T10 |
1 |
|
T16 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9911 |
1 |
|
T3 |
219 |
|
T25 |
118 |
|
T13 |
2 |
| others[1] |
786 |
1 |
|
T31 |
20 |
|
T49 |
4 |
|
T161 |
1 |
| others[2] |
753 |
1 |
|
T19 |
1 |
|
T31 |
24 |
|
T49 |
11 |
| others[3] |
1319 |
1 |
|
T1 |
1 |
|
T31 |
35 |
|
T49 |
21 |
| false |
445 |
1 |
|
T31 |
4 |
|
T49 |
9 |
|
T43 |
1 |
| true |
566 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2425 |
1 |
|
T3 |
47 |
|
T25 |
27 |
|
T31 |
12 |
| others[1] |
2396 |
1 |
|
T3 |
40 |
|
T25 |
19 |
|
T31 |
15 |
| others[2] |
2311 |
1 |
|
T3 |
41 |
|
T25 |
22 |
|
T23 |
1 |
| others[3] |
3859 |
1 |
|
T1 |
1 |
|
T3 |
66 |
|
T16 |
1 |
| false |
1189 |
1 |
|
T3 |
25 |
|
T25 |
13 |
|
T31 |
5 |
| true |
1600 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9400 |
1 |
|
T3 |
219 |
|
T5 |
1 |
|
T25 |
118 |
| others[1] |
287 |
1 |
|
T31 |
9 |
|
T46 |
1 |
|
T302 |
1 |
| others[2] |
258 |
1 |
|
T31 |
7 |
|
T43 |
1 |
|
T62 |
1 |
| others[3] |
510 |
1 |
|
T23 |
1 |
|
T38 |
1 |
|
T31 |
12 |
| false |
141 |
1 |
|
T16 |
1 |
|
T19 |
1 |
|
T31 |
2 |
| true |
3184 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |